abyss.c 11 KB

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  1. /*
  2. * abyss.c: Network driver for the Madge Smart 16/4 PCI Mk2 token ring card.
  3. *
  4. * Written 1999-2000 by Adam Fritzler
  5. *
  6. * This software may be used and distributed according to the terms
  7. * of the GNU General Public License, incorporated herein by reference.
  8. *
  9. * This driver module supports the following cards:
  10. * - Madge Smart 16/4 PCI Mk2
  11. *
  12. * Maintainer(s):
  13. * AF Adam Fritzler mid@auk.cx
  14. *
  15. * Modification History:
  16. * 30-Dec-99 AF Split off from the tms380tr driver.
  17. * 22-Jan-00 AF Updated to use indirect read/writes
  18. * 23-Nov-00 JG New PCI API, cleanups
  19. *
  20. *
  21. * TODO:
  22. * 1. See if we can use MMIO instead of inb/outb/inw/outw
  23. * 2. Add support for Mk1 (has AT24 attached to the PCI
  24. * config registers)
  25. *
  26. */
  27. #include <linux/module.h>
  28. #include <linux/kernel.h>
  29. #include <linux/errno.h>
  30. #include <linux/pci.h>
  31. #include <linux/init.h>
  32. #include <linux/netdevice.h>
  33. #include <linux/trdevice.h>
  34. #include <asm/system.h>
  35. #include <asm/io.h>
  36. #include <asm/irq.h>
  37. #include "tms380tr.h"
  38. #include "abyss.h" /* Madge-specific constants */
  39. static char version[] __devinitdata =
  40. "abyss.c: v1.02 23/11/2000 by Adam Fritzler\n";
  41. #define ABYSS_IO_EXTENT 64
  42. static struct pci_device_id abyss_pci_tbl[] = {
  43. { PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_MK2,
  44. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_TOKEN_RING << 8, 0x00ffffff, },
  45. { } /* Terminating entry */
  46. };
  47. MODULE_DEVICE_TABLE(pci, abyss_pci_tbl);
  48. MODULE_LICENSE("GPL");
  49. static int abyss_open(struct net_device *dev);
  50. static int abyss_close(struct net_device *dev);
  51. static void abyss_enable(struct net_device *dev);
  52. static int abyss_chipset_init(struct net_device *dev);
  53. static void abyss_read_eeprom(struct net_device *dev);
  54. static unsigned short abyss_setnselout_pins(struct net_device *dev);
  55. static void at24_writedatabyte(unsigned long regaddr, unsigned char byte);
  56. static int at24_sendfullcmd(unsigned long regaddr, unsigned char cmd, unsigned char addr);
  57. static int at24_sendcmd(unsigned long regaddr, unsigned char cmd);
  58. static unsigned char at24_readdatabit(unsigned long regaddr);
  59. static unsigned char at24_readdatabyte(unsigned long regaddr);
  60. static int at24_waitforack(unsigned long regaddr);
  61. static int at24_waitfornack(unsigned long regaddr);
  62. static void at24_setlines(unsigned long regaddr, unsigned char clock, unsigned char data);
  63. static void at24_start(unsigned long regaddr);
  64. static unsigned char at24_readb(unsigned long regaddr, unsigned char addr);
  65. static unsigned short abyss_sifreadb(struct net_device *dev, unsigned short reg)
  66. {
  67. return inb(dev->base_addr + reg);
  68. }
  69. static unsigned short abyss_sifreadw(struct net_device *dev, unsigned short reg)
  70. {
  71. return inw(dev->base_addr + reg);
  72. }
  73. static void abyss_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
  74. {
  75. outb(val, dev->base_addr + reg);
  76. }
  77. static void abyss_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
  78. {
  79. outw(val, dev->base_addr + reg);
  80. }
  81. static int __devinit abyss_attach(struct pci_dev *pdev, const struct pci_device_id *ent)
  82. {
  83. static int versionprinted;
  84. struct net_device *dev;
  85. struct net_local *tp;
  86. int ret, pci_irq_line;
  87. unsigned long pci_ioaddr;
  88. DECLARE_MAC_BUF(mac);
  89. if (versionprinted++ == 0)
  90. printk("%s", version);
  91. if (pci_enable_device(pdev))
  92. return -EIO;
  93. /* Remove I/O space marker in bit 0. */
  94. pci_irq_line = pdev->irq;
  95. pci_ioaddr = pci_resource_start (pdev, 0);
  96. /* At this point we have found a valid card. */
  97. dev = alloc_trdev(sizeof(struct net_local));
  98. if (!dev)
  99. return -ENOMEM;
  100. if (!request_region(pci_ioaddr, ABYSS_IO_EXTENT, dev->name)) {
  101. ret = -EBUSY;
  102. goto err_out_trdev;
  103. }
  104. ret = request_irq(pdev->irq, tms380tr_interrupt, IRQF_SHARED,
  105. dev->name, dev);
  106. if (ret)
  107. goto err_out_region;
  108. dev->base_addr = pci_ioaddr;
  109. dev->irq = pci_irq_line;
  110. printk("%s: Madge Smart 16/4 PCI Mk2 (Abyss)\n", dev->name);
  111. printk("%s: IO: %#4lx IRQ: %d\n",
  112. dev->name, pci_ioaddr, dev->irq);
  113. /*
  114. * The TMS SIF registers lay 0x10 above the card base address.
  115. */
  116. dev->base_addr += 0x10;
  117. ret = tmsdev_init(dev, &pdev->dev);
  118. if (ret) {
  119. printk("%s: unable to get memory for dev->priv.\n",
  120. dev->name);
  121. goto err_out_irq;
  122. }
  123. abyss_read_eeprom(dev);
  124. printk("%s: Ring Station Address: %s\n",
  125. dev->name, print_mac(mac, dev->dev_addr));
  126. tp = netdev_priv(dev);
  127. tp->setnselout = abyss_setnselout_pins;
  128. tp->sifreadb = abyss_sifreadb;
  129. tp->sifreadw = abyss_sifreadw;
  130. tp->sifwriteb = abyss_sifwriteb;
  131. tp->sifwritew = abyss_sifwritew;
  132. memcpy(tp->ProductID, "Madge PCI 16/4 Mk2", PROD_ID_SIZE + 1);
  133. dev->open = abyss_open;
  134. dev->stop = abyss_close;
  135. pci_set_drvdata(pdev, dev);
  136. SET_NETDEV_DEV(dev, &pdev->dev);
  137. ret = register_netdev(dev);
  138. if (ret)
  139. goto err_out_tmsdev;
  140. return 0;
  141. err_out_tmsdev:
  142. pci_set_drvdata(pdev, NULL);
  143. tmsdev_term(dev);
  144. err_out_irq:
  145. free_irq(pdev->irq, dev);
  146. err_out_region:
  147. release_region(pci_ioaddr, ABYSS_IO_EXTENT);
  148. err_out_trdev:
  149. free_netdev(dev);
  150. return ret;
  151. }
  152. static unsigned short abyss_setnselout_pins(struct net_device *dev)
  153. {
  154. unsigned short val = 0;
  155. struct net_local *tp = netdev_priv(dev);
  156. if(tp->DataRate == SPEED_4)
  157. val |= 0x01; /* Set 4Mbps */
  158. else
  159. val |= 0x00; /* Set 16Mbps */
  160. return val;
  161. }
  162. /*
  163. * The following Madge boards should use this code:
  164. * - Smart 16/4 PCI Mk2 (Abyss)
  165. * - Smart 16/4 PCI Mk1 (PCI T)
  166. * - Smart 16/4 Client Plus PnP (Big Apple)
  167. * - Smart 16/4 Cardbus Mk2
  168. *
  169. * These access an Atmel AT24 SEEPROM using their glue chip registers.
  170. *
  171. */
  172. static void at24_writedatabyte(unsigned long regaddr, unsigned char byte)
  173. {
  174. int i;
  175. for (i = 0; i < 8; i++) {
  176. at24_setlines(regaddr, 0, (byte >> (7-i))&0x01);
  177. at24_setlines(regaddr, 1, (byte >> (7-i))&0x01);
  178. at24_setlines(regaddr, 0, (byte >> (7-i))&0x01);
  179. }
  180. }
  181. static int at24_sendfullcmd(unsigned long regaddr, unsigned char cmd, unsigned char addr)
  182. {
  183. if (at24_sendcmd(regaddr, cmd)) {
  184. at24_writedatabyte(regaddr, addr);
  185. return at24_waitforack(regaddr);
  186. }
  187. return 0;
  188. }
  189. static int at24_sendcmd(unsigned long regaddr, unsigned char cmd)
  190. {
  191. int i;
  192. for (i = 0; i < 10; i++) {
  193. at24_start(regaddr);
  194. at24_writedatabyte(regaddr, cmd);
  195. if (at24_waitforack(regaddr))
  196. return 1;
  197. }
  198. return 0;
  199. }
  200. static unsigned char at24_readdatabit(unsigned long regaddr)
  201. {
  202. unsigned char val;
  203. at24_setlines(regaddr, 0, 1);
  204. at24_setlines(regaddr, 1, 1);
  205. val = (inb(regaddr) & AT24_DATA)?1:0;
  206. at24_setlines(regaddr, 1, 1);
  207. at24_setlines(regaddr, 0, 1);
  208. return val;
  209. }
  210. static unsigned char at24_readdatabyte(unsigned long regaddr)
  211. {
  212. unsigned char data = 0;
  213. int i;
  214. for (i = 0; i < 8; i++) {
  215. data <<= 1;
  216. data |= at24_readdatabit(regaddr);
  217. }
  218. return data;
  219. }
  220. static int at24_waitforack(unsigned long regaddr)
  221. {
  222. int i;
  223. for (i = 0; i < 10; i++) {
  224. if ((at24_readdatabit(regaddr) & 0x01) == 0x00)
  225. return 1;
  226. }
  227. return 0;
  228. }
  229. static int at24_waitfornack(unsigned long regaddr)
  230. {
  231. int i;
  232. for (i = 0; i < 10; i++) {
  233. if ((at24_readdatabit(regaddr) & 0x01) == 0x01)
  234. return 1;
  235. }
  236. return 0;
  237. }
  238. static void at24_setlines(unsigned long regaddr, unsigned char clock, unsigned char data)
  239. {
  240. unsigned char val = AT24_ENABLE;
  241. if (clock)
  242. val |= AT24_CLOCK;
  243. if (data)
  244. val |= AT24_DATA;
  245. outb(val, regaddr);
  246. tms380tr_wait(20); /* Very necessary. */
  247. }
  248. static void at24_start(unsigned long regaddr)
  249. {
  250. at24_setlines(regaddr, 0, 1);
  251. at24_setlines(regaddr, 1, 1);
  252. at24_setlines(regaddr, 1, 0);
  253. at24_setlines(regaddr, 0, 1);
  254. }
  255. static unsigned char at24_readb(unsigned long regaddr, unsigned char addr)
  256. {
  257. unsigned char data = 0xff;
  258. if (at24_sendfullcmd(regaddr, AT24_WRITE, addr)) {
  259. if (at24_sendcmd(regaddr, AT24_READ)) {
  260. data = at24_readdatabyte(regaddr);
  261. if (!at24_waitfornack(regaddr))
  262. data = 0xff;
  263. }
  264. }
  265. return data;
  266. }
  267. /*
  268. * Enable basic functions of the Madge chipset needed
  269. * for initialization.
  270. */
  271. static void abyss_enable(struct net_device *dev)
  272. {
  273. unsigned char reset_reg;
  274. unsigned long ioaddr;
  275. ioaddr = dev->base_addr;
  276. reset_reg = inb(ioaddr + PCIBM2_RESET_REG);
  277. reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
  278. outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
  279. tms380tr_wait(100);
  280. }
  281. /*
  282. * Enable the functions of the Madge chipset needed for
  283. * full working order.
  284. */
  285. static int abyss_chipset_init(struct net_device *dev)
  286. {
  287. unsigned char reset_reg;
  288. unsigned long ioaddr;
  289. ioaddr = dev->base_addr;
  290. reset_reg = inb(ioaddr + PCIBM2_RESET_REG);
  291. reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
  292. outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
  293. reset_reg &= ~(PCIBM2_RESET_REG_CHIP_NRES |
  294. PCIBM2_RESET_REG_FIFO_NRES |
  295. PCIBM2_RESET_REG_SIF_NRES);
  296. outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
  297. tms380tr_wait(100);
  298. reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
  299. outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
  300. reset_reg |= PCIBM2_RESET_REG_SIF_NRES;
  301. outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
  302. reset_reg |= PCIBM2_RESET_REG_FIFO_NRES;
  303. outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
  304. outb(PCIBM2_INT_CONTROL_REG_SINTEN |
  305. PCIBM2_INT_CONTROL_REG_PCI_ERR_ENABLE,
  306. ioaddr + PCIBM2_INT_CONTROL_REG);
  307. outb(30, ioaddr + PCIBM2_FIFO_THRESHOLD);
  308. return 0;
  309. }
  310. static inline void abyss_chipset_close(struct net_device *dev)
  311. {
  312. unsigned long ioaddr;
  313. ioaddr = dev->base_addr;
  314. outb(0, ioaddr + PCIBM2_RESET_REG);
  315. }
  316. /*
  317. * Read configuration data from the AT24 SEEPROM on Madge cards.
  318. *
  319. */
  320. static void abyss_read_eeprom(struct net_device *dev)
  321. {
  322. struct net_local *tp;
  323. unsigned long ioaddr;
  324. unsigned short val;
  325. int i;
  326. tp = netdev_priv(dev);
  327. ioaddr = dev->base_addr;
  328. /* Must enable glue chip first */
  329. abyss_enable(dev);
  330. val = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
  331. PCIBM2_SEEPROM_RING_SPEED);
  332. tp->DataRate = val?SPEED_4:SPEED_16; /* set open speed */
  333. printk("%s: SEEPROM: ring speed: %dMb/sec\n", dev->name, tp->DataRate);
  334. val = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
  335. PCIBM2_SEEPROM_RAM_SIZE) * 128;
  336. printk("%s: SEEPROM: adapter RAM: %dkb\n", dev->name, val);
  337. dev->addr_len = 6;
  338. for (i = 0; i < 6; i++)
  339. dev->dev_addr[i] = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
  340. PCIBM2_SEEPROM_BIA+i);
  341. }
  342. static int abyss_open(struct net_device *dev)
  343. {
  344. abyss_chipset_init(dev);
  345. tms380tr_open(dev);
  346. return 0;
  347. }
  348. static int abyss_close(struct net_device *dev)
  349. {
  350. tms380tr_close(dev);
  351. abyss_chipset_close(dev);
  352. return 0;
  353. }
  354. static void __devexit abyss_detach (struct pci_dev *pdev)
  355. {
  356. struct net_device *dev = pci_get_drvdata(pdev);
  357. BUG_ON(!dev);
  358. unregister_netdev(dev);
  359. release_region(dev->base_addr-0x10, ABYSS_IO_EXTENT);
  360. free_irq(dev->irq, dev);
  361. tmsdev_term(dev);
  362. free_netdev(dev);
  363. pci_set_drvdata(pdev, NULL);
  364. }
  365. static struct pci_driver abyss_driver = {
  366. .name = "abyss",
  367. .id_table = abyss_pci_tbl,
  368. .probe = abyss_attach,
  369. .remove = __devexit_p(abyss_detach),
  370. };
  371. static int __init abyss_init (void)
  372. {
  373. return pci_register_driver(&abyss_driver);
  374. }
  375. static void __exit abyss_rmmod (void)
  376. {
  377. pci_unregister_driver (&abyss_driver);
  378. }
  379. module_init(abyss_init);
  380. module_exit(abyss_rmmod);