3c359.c 58 KB

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  1. /*
  2. * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
  3. *
  4. * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC
  5. *
  6. * Base Driver Olympic:
  7. * Written 1999 Peter De Schrijver & Mike Phillips
  8. *
  9. * This software may be used and distributed according to the terms
  10. * of the GNU General Public License, incorporated herein by reference.
  11. *
  12. * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world.
  13. *
  14. * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel.
  15. * 3/05/01 - Last clean up stuff before submission.
  16. * 2/15/01 - Finally, update to new pci api.
  17. *
  18. * To Do:
  19. */
  20. /*
  21. * Technical Card Details
  22. *
  23. * All access to data is done with 16/8 bit transfers. The transfer
  24. * method really sucks. You can only read or write one location at a time.
  25. *
  26. * Also, the microcode for the card must be uploaded if the card does not have
  27. * the flashrom on board. This is a 28K bloat in the driver when compiled
  28. * as a module.
  29. *
  30. * Rx is very simple, status into a ring of descriptors, dma data transfer,
  31. * interrupts to tell us when a packet is received.
  32. *
  33. * Tx is a little more interesting. Similar scenario, descriptor and dma data
  34. * transfers, but we don't have to interrupt the card to tell it another packet
  35. * is ready for transmission, we are just doing simple memory writes, not io or mmio
  36. * writes. The card can be set up to simply poll on the next
  37. * descriptor pointer and when this value is non-zero will automatically download
  38. * the next packet. The card then interrupts us when the packet is done.
  39. *
  40. */
  41. #define XL_DEBUG 0
  42. #include <linux/module.h>
  43. #include <linux/kernel.h>
  44. #include <linux/errno.h>
  45. #include <linux/timer.h>
  46. #include <linux/in.h>
  47. #include <linux/ioport.h>
  48. #include <linux/string.h>
  49. #include <linux/proc_fs.h>
  50. #include <linux/ptrace.h>
  51. #include <linux/skbuff.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/delay.h>
  54. #include <linux/netdevice.h>
  55. #include <linux/trdevice.h>
  56. #include <linux/stddef.h>
  57. #include <linux/init.h>
  58. #include <linux/pci.h>
  59. #include <linux/spinlock.h>
  60. #include <linux/bitops.h>
  61. #include <net/checksum.h>
  62. #include <asm/io.h>
  63. #include <asm/system.h>
  64. #include "3c359.h"
  65. static char version[] __devinitdata =
  66. "3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ;
  67. MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
  68. MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver \n") ;
  69. /* Module paramters */
  70. /* Ring Speed 0,4,16
  71. * 0 = Autosense
  72. * 4,16 = Selected speed only, no autosense
  73. * This allows the card to be the first on the ring
  74. * and become the active monitor.
  75. *
  76. * WARNING: Some hubs will allow you to insert
  77. * at the wrong speed.
  78. *
  79. * The adapter will _not_ fail to open if there are no
  80. * active monitors on the ring, it will simply open up in
  81. * its last known ringspeed if no ringspeed is specified.
  82. */
  83. static int ringspeed[XL_MAX_ADAPTERS] = {0,} ;
  84. module_param_array(ringspeed, int, NULL, 0);
  85. MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ;
  86. /* Packet buffer size */
  87. static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ;
  88. module_param_array(pkt_buf_sz, int, NULL, 0) ;
  89. MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ;
  90. /* Message Level */
  91. static int message_level[XL_MAX_ADAPTERS] = {0,} ;
  92. module_param_array(message_level, int, NULL, 0) ;
  93. MODULE_PARM_DESC(message_level, "3c359: Level of reported messages \n") ;
  94. /*
  95. * This is a real nasty way of doing this, but otherwise you
  96. * will be stuck with 1555 lines of hex #'s in the code.
  97. */
  98. #include "3c359_microcode.h"
  99. static struct pci_device_id xl_pci_tbl[] =
  100. {
  101. {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, },
  102. { } /* terminate list */
  103. };
  104. MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ;
  105. static int xl_init(struct net_device *dev);
  106. static int xl_open(struct net_device *dev);
  107. static int xl_open_hw(struct net_device *dev) ;
  108. static int xl_hw_reset(struct net_device *dev);
  109. static int xl_xmit(struct sk_buff *skb, struct net_device *dev);
  110. static void xl_dn_comp(struct net_device *dev);
  111. static int xl_close(struct net_device *dev);
  112. static void xl_set_rx_mode(struct net_device *dev);
  113. static irqreturn_t xl_interrupt(int irq, void *dev_id);
  114. static struct net_device_stats * xl_get_stats(struct net_device *dev);
  115. static int xl_set_mac_address(struct net_device *dev, void *addr) ;
  116. static void xl_arb_cmd(struct net_device *dev);
  117. static void xl_asb_cmd(struct net_device *dev) ;
  118. static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ;
  119. static void xl_wait_misr_flags(struct net_device *dev) ;
  120. static int xl_change_mtu(struct net_device *dev, int mtu);
  121. static void xl_srb_bh(struct net_device *dev) ;
  122. static void xl_asb_bh(struct net_device *dev) ;
  123. static void xl_reset(struct net_device *dev) ;
  124. static void xl_freemem(struct net_device *dev) ;
  125. /* EEProm Access Functions */
  126. static u16 xl_ee_read(struct net_device *dev, int ee_addr) ;
  127. static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ;
  128. /* Debugging functions */
  129. #if XL_DEBUG
  130. static void print_tx_state(struct net_device *dev) ;
  131. static void print_rx_state(struct net_device *dev) ;
  132. static void print_tx_state(struct net_device *dev)
  133. {
  134. struct xl_private *xl_priv = netdev_priv(dev);
  135. struct xl_tx_desc *txd ;
  136. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  137. int i ;
  138. printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d \n",xl_priv->tx_ring_head,
  139. xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ;
  140. printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len \n");
  141. for (i = 0; i < 16; i++) {
  142. txd = &(xl_priv->xl_tx_ring[i]) ;
  143. printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(txd),
  144. txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ;
  145. }
  146. printk("DNLISTPTR = %04x \n", readl(xl_mmio + MMIO_DNLISTPTR) );
  147. printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
  148. printk("Queue status = %0x \n",netif_running(dev) ) ;
  149. }
  150. static void print_rx_state(struct net_device *dev)
  151. {
  152. struct xl_private *xl_priv = netdev_priv(dev);
  153. struct xl_rx_desc *rxd ;
  154. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  155. int i ;
  156. printk("rx_ring_tail: %d \n", xl_priv->rx_ring_tail) ;
  157. printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len \n");
  158. for (i = 0; i < 16; i++) {
  159. /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */
  160. rxd = &(xl_priv->xl_rx_ring[i]) ;
  161. printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(rxd),
  162. rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ;
  163. }
  164. printk("UPLISTPTR = %04x \n", readl(xl_mmio + MMIO_UPLISTPTR) );
  165. printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
  166. printk("Queue status = %0x \n",netif_running(dev) ) ;
  167. }
  168. #endif
  169. /*
  170. * Read values from the on-board EEProm. This looks very strange
  171. * but you have to wait for the EEProm to get/set the value before
  172. * passing/getting the next value from the nic. As with all requests
  173. * on this nic it has to be done in two stages, a) tell the nic which
  174. * memory address you want to access and b) pass/get the value from the nic.
  175. * With the EEProm, you have to wait before and inbetween access a) and b).
  176. * As this is only read at initialization time and the wait period is very
  177. * small we shouldn't have to worry about scheduling issues.
  178. */
  179. static u16 xl_ee_read(struct net_device *dev, int ee_addr)
  180. {
  181. struct xl_private *xl_priv = netdev_priv(dev);
  182. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  183. /* Wait for EEProm to not be busy */
  184. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  185. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  186. /* Tell EEProm what we want to do and where */
  187. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  188. writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
  189. /* Wait for EEProm to not be busy */
  190. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  191. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  192. /* Tell EEProm what we want to do and where */
  193. writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  194. writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
  195. /* Finally read the value from the EEProm */
  196. writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  197. return readw(xl_mmio + MMIO_MACDATA) ;
  198. }
  199. /*
  200. * Write values to the onboard eeprom. As with eeprom read you need to
  201. * set which location to write, wait, value to write, wait, with the
  202. * added twist of having to enable eeprom writes as well.
  203. */
  204. static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value)
  205. {
  206. struct xl_private *xl_priv = netdev_priv(dev);
  207. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  208. /* Wait for EEProm to not be busy */
  209. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  210. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  211. /* Enable write/erase */
  212. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  213. writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ;
  214. /* Wait for EEProm to not be busy */
  215. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  216. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  217. /* Put the value we want to write into EEDATA */
  218. writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  219. writew(ee_value, xl_mmio + MMIO_MACDATA) ;
  220. /* Tell EEProm to write eevalue into ee_addr */
  221. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  222. writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ;
  223. /* Wait for EEProm to not be busy, to ensure write gets done */
  224. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  225. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  226. return ;
  227. }
  228. static int __devinit xl_probe(struct pci_dev *pdev,
  229. const struct pci_device_id *ent)
  230. {
  231. struct net_device *dev ;
  232. struct xl_private *xl_priv ;
  233. static int card_no = -1 ;
  234. int i ;
  235. card_no++ ;
  236. if (pci_enable_device(pdev)) {
  237. return -ENODEV ;
  238. }
  239. pci_set_master(pdev);
  240. if ((i = pci_request_regions(pdev,"3c359"))) {
  241. return i ;
  242. } ;
  243. /*
  244. * Allowing init_trdev to allocate the dev->priv structure will align xl_private
  245. * on a 32 bytes boundary which we need for the rx/tx descriptors
  246. */
  247. dev = alloc_trdev(sizeof(struct xl_private)) ;
  248. if (!dev) {
  249. pci_release_regions(pdev) ;
  250. return -ENOMEM ;
  251. }
  252. xl_priv = netdev_priv(dev);
  253. #if XL_DEBUG
  254. printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n",
  255. pdev, dev, netdev_priv(dev), (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start);
  256. #endif
  257. dev->irq=pdev->irq;
  258. dev->base_addr=pci_resource_start(pdev,0) ;
  259. xl_priv->xl_card_name = pci_name(pdev);
  260. xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE);
  261. xl_priv->pdev = pdev ;
  262. if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
  263. xl_priv->pkt_buf_sz = PKT_BUF_SZ ;
  264. else
  265. xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
  266. dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ;
  267. xl_priv->xl_ring_speed = ringspeed[card_no] ;
  268. xl_priv->xl_message_level = message_level[card_no] ;
  269. xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ;
  270. xl_priv->xl_copy_all_options = 0 ;
  271. if((i = xl_init(dev))) {
  272. iounmap(xl_priv->xl_mmio) ;
  273. free_netdev(dev) ;
  274. pci_release_regions(pdev) ;
  275. return i ;
  276. }
  277. dev->open=&xl_open;
  278. dev->hard_start_xmit=&xl_xmit;
  279. dev->change_mtu=&xl_change_mtu;
  280. dev->stop=&xl_close;
  281. dev->do_ioctl=NULL;
  282. dev->set_multicast_list=&xl_set_rx_mode;
  283. dev->get_stats=&xl_get_stats ;
  284. dev->set_mac_address=&xl_set_mac_address ;
  285. SET_NETDEV_DEV(dev, &pdev->dev);
  286. pci_set_drvdata(pdev,dev) ;
  287. if ((i = register_netdev(dev))) {
  288. printk(KERN_ERR "3C359, register netdev failed\n") ;
  289. pci_set_drvdata(pdev,NULL) ;
  290. iounmap(xl_priv->xl_mmio) ;
  291. free_netdev(dev) ;
  292. pci_release_regions(pdev) ;
  293. return i ;
  294. }
  295. printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ;
  296. return 0;
  297. }
  298. static int __devinit xl_init(struct net_device *dev)
  299. {
  300. struct xl_private *xl_priv = netdev_priv(dev);
  301. printk(KERN_INFO "%s \n", version);
  302. printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n",
  303. xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq);
  304. spin_lock_init(&xl_priv->xl_lock) ;
  305. return xl_hw_reset(dev) ;
  306. }
  307. /*
  308. * Hardware reset. This needs to be a separate entity as we need to reset the card
  309. * when we change the EEProm settings.
  310. */
  311. static int xl_hw_reset(struct net_device *dev)
  312. {
  313. struct xl_private *xl_priv = netdev_priv(dev);
  314. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  315. unsigned long t ;
  316. u16 i ;
  317. u16 result_16 ;
  318. u8 result_8 ;
  319. u16 start ;
  320. int j ;
  321. /*
  322. * Reset the card. If the card has got the microcode on board, we have
  323. * missed the initialization interrupt, so we must always do this.
  324. */
  325. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  326. /*
  327. * Must wait for cmdInProgress bit (12) to clear before continuing with
  328. * card configuration.
  329. */
  330. t=jiffies;
  331. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  332. schedule();
  333. if(jiffies-t > 40*HZ) {
  334. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name);
  335. return -ENODEV;
  336. }
  337. }
  338. /*
  339. * Enable pmbar by setting bit in CPAttention
  340. */
  341. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  342. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  343. result_8 = result_8 | CPA_PMBARVIS ;
  344. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  345. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  346. /*
  347. * Read cpHold bit in pmbar, if cleared we have got Flashrom on board.
  348. * If not, we need to upload the microcode to the card
  349. */
  350. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  351. #if XL_DEBUG
  352. printk(KERN_INFO "Read from PMBAR = %04x \n", readw(xl_mmio + MMIO_MACDATA)) ;
  353. #endif
  354. if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
  355. /* Set PmBar, privateMemoryBase bits (8:2) to 0 */
  356. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  357. result_16 = readw(xl_mmio + MMIO_MACDATA) ;
  358. result_16 = result_16 & ~((0x7F) << 2) ;
  359. writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  360. writew(result_16,xl_mmio + MMIO_MACDATA) ;
  361. /* Set CPAttention, memWrEn bit */
  362. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  363. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  364. result_8 = result_8 | CPA_MEMWREN ;
  365. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  366. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  367. /*
  368. * Now to write the microcode into the shared ram
  369. * The microcode must finish at position 0xFFFF, so we must subtract
  370. * to get the start position for the code
  371. */
  372. start = (0xFFFF - (mc_size) + 1 ) ; /* Looks strange but ensures compiler only uses 16 bit unsigned int for this */
  373. printk(KERN_INFO "3C359: Uploading Microcode: ");
  374. for (i = start, j = 0; j < mc_size; i++, j++) {
  375. writel(MEM_BYTE_WRITE | 0XD0000 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  376. writeb(microcode[j],xl_mmio + MMIO_MACDATA) ;
  377. if (j % 1024 == 0)
  378. printk(".");
  379. }
  380. printk("\n") ;
  381. for (i=0;i < 16; i++) {
  382. writel( (MEM_BYTE_WRITE | 0xDFFF0) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  383. writeb(microcode[mc_size - 16 + i], xl_mmio + MMIO_MACDATA) ;
  384. }
  385. /*
  386. * Have to write the start address of the upload to FFF4, but
  387. * the address must be >> 4. You do not want to know how long
  388. * it took me to discover this.
  389. */
  390. writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  391. writew(start >> 4, xl_mmio + MMIO_MACDATA);
  392. /* Clear the CPAttention, memWrEn Bit */
  393. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  394. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  395. result_8 = result_8 & ~CPA_MEMWREN ;
  396. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  397. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  398. /* Clear the cpHold bit in pmbar */
  399. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  400. result_16 = readw(xl_mmio + MMIO_MACDATA) ;
  401. result_16 = result_16 & ~PMB_CPHOLD ;
  402. writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  403. writew(result_16,xl_mmio + MMIO_MACDATA) ;
  404. } /* If microcode upload required */
  405. /*
  406. * The card should now go though a self test procedure and get itself ready
  407. * to be opened, we must wait for an srb response with the initialization
  408. * information.
  409. */
  410. #if XL_DEBUG
  411. printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name);
  412. #endif
  413. writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ;
  414. t=jiffies;
  415. while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) {
  416. schedule();
  417. if(jiffies-t > 15*HZ) {
  418. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  419. return -ENODEV;
  420. }
  421. }
  422. /*
  423. * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh,
  424. * DnPriReqThresh, read the tech docs if you want to know what
  425. * values they need to be.
  426. */
  427. writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  428. writew(0xD000, xl_mmio + MMIO_MACDATA) ;
  429. writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  430. writew(0X0020, xl_mmio + MMIO_MACDATA) ;
  431. writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ;
  432. writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ;
  433. writeb(0x04, xl_mmio + DNPRIREQTHRESH) ;
  434. /*
  435. * Read WRBR to provide the location of the srb block, have to use byte reads not word reads.
  436. * Tech docs have this wrong !!!!
  437. */
  438. writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  439. xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ;
  440. writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  441. xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ;
  442. #if XL_DEBUG
  443. writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  444. if ( readw(xl_mmio + MMIO_MACDATA) & 2) {
  445. printk(KERN_INFO "Default ring speed 4 mbps \n") ;
  446. } else {
  447. printk(KERN_INFO "Default ring speed 16 mbps \n") ;
  448. }
  449. printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb);
  450. #endif
  451. return 0;
  452. }
  453. static int xl_open(struct net_device *dev)
  454. {
  455. struct xl_private *xl_priv=netdev_priv(dev);
  456. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  457. u8 i ;
  458. u16 hwaddr[3] ; /* Should be u8[6] but we get word return values */
  459. int open_err ;
  460. u16 switchsettings, switchsettings_eeprom ;
  461. if(request_irq(dev->irq, &xl_interrupt, IRQF_SHARED , "3c359", dev)) {
  462. return -EAGAIN;
  463. }
  464. /*
  465. * Read the information from the EEPROM that we need. I know we
  466. * should use ntohs, but the word gets stored reversed in the 16
  467. * bit field anyway and it all works its self out when we memcpy
  468. * it into dev->dev_addr.
  469. */
  470. hwaddr[0] = xl_ee_read(dev,0x10) ;
  471. hwaddr[1] = xl_ee_read(dev,0x11) ;
  472. hwaddr[2] = xl_ee_read(dev,0x12) ;
  473. /* Ring speed */
  474. switchsettings_eeprom = xl_ee_read(dev,0x08) ;
  475. switchsettings = switchsettings_eeprom ;
  476. if (xl_priv->xl_ring_speed != 0) {
  477. if (xl_priv->xl_ring_speed == 4)
  478. switchsettings = switchsettings | 0x02 ;
  479. else
  480. switchsettings = switchsettings & ~0x02 ;
  481. }
  482. /* Only write EEProm if there has been a change */
  483. if (switchsettings != switchsettings_eeprom) {
  484. xl_ee_write(dev,0x08,switchsettings) ;
  485. /* Hardware reset after changing EEProm */
  486. xl_hw_reset(dev) ;
  487. }
  488. memcpy(dev->dev_addr,hwaddr,dev->addr_len) ;
  489. open_err = xl_open_hw(dev) ;
  490. /*
  491. * This really needs to be cleaned up with better error reporting.
  492. */
  493. if (open_err != 0) { /* Something went wrong with the open command */
  494. if (open_err & 0x07) { /* Wrong speed, retry at different speed */
  495. printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed \n", dev->name) ;
  496. switchsettings = switchsettings ^ 2 ;
  497. xl_ee_write(dev,0x08,switchsettings) ;
  498. xl_hw_reset(dev) ;
  499. open_err = xl_open_hw(dev) ;
  500. if (open_err != 0) {
  501. printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name);
  502. free_irq(dev->irq,dev) ;
  503. return -ENODEV ;
  504. }
  505. } else {
  506. printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ;
  507. free_irq(dev->irq,dev) ;
  508. return -ENODEV ;
  509. }
  510. }
  511. /*
  512. * Now to set up the Rx and Tx buffer structures
  513. */
  514. /* These MUST be on 8 byte boundaries */
  515. xl_priv->xl_tx_ring = kzalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL);
  516. if (xl_priv->xl_tx_ring == NULL) {
  517. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
  518. dev->name);
  519. free_irq(dev->irq,dev);
  520. return -ENOMEM;
  521. }
  522. xl_priv->xl_rx_ring = kzalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL);
  523. if (xl_priv->xl_tx_ring == NULL) {
  524. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
  525. dev->name);
  526. free_irq(dev->irq,dev);
  527. kfree(xl_priv->xl_tx_ring);
  528. return -ENOMEM;
  529. }
  530. /* Setup Rx Ring */
  531. for (i=0 ; i < XL_RX_RING_SIZE ; i++) {
  532. struct sk_buff *skb ;
  533. skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
  534. if (skb==NULL)
  535. break ;
  536. skb->dev = dev ;
  537. xl_priv->xl_rx_ring[i].upfragaddr = pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
  538. xl_priv->xl_rx_ring[i].upfraglen = xl_priv->pkt_buf_sz | RXUPLASTFRAG;
  539. xl_priv->rx_ring_skb[i] = skb ;
  540. }
  541. if (i==0) {
  542. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled \n",dev->name) ;
  543. free_irq(dev->irq,dev) ;
  544. return -EIO ;
  545. }
  546. xl_priv->rx_ring_no = i ;
  547. xl_priv->rx_ring_tail = 0 ;
  548. xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ;
  549. for (i=0;i<(xl_priv->rx_ring_no-1);i++) {
  550. xl_priv->xl_rx_ring[i].upnextptr = xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1)) ;
  551. }
  552. xl_priv->xl_rx_ring[i].upnextptr = 0 ;
  553. writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ;
  554. /* Setup Tx Ring */
  555. xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
  556. xl_priv->tx_ring_head = 1 ;
  557. xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */
  558. xl_priv->free_ring_entries = XL_TX_RING_SIZE ;
  559. /*
  560. * Setup the first dummy DPD entry for polling to start working.
  561. */
  562. xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY ;
  563. xl_priv->xl_tx_ring[0].buffer = 0 ;
  564. xl_priv->xl_tx_ring[0].buffer_length = 0 ;
  565. xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
  566. writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ;
  567. writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ;
  568. writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ;
  569. writel(DNENABLE, xl_mmio + MMIO_COMMAND) ;
  570. writeb(0x40, xl_mmio + MMIO_DNPOLL) ;
  571. /*
  572. * Enable interrupts on the card
  573. */
  574. writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  575. writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  576. netif_start_queue(dev) ;
  577. return 0;
  578. }
  579. static int xl_open_hw(struct net_device *dev)
  580. {
  581. struct xl_private *xl_priv=netdev_priv(dev);
  582. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  583. u16 vsoff ;
  584. char ver_str[33];
  585. int open_err ;
  586. int i ;
  587. unsigned long t ;
  588. /*
  589. * Okay, let's build up the Open.NIC srb command
  590. *
  591. */
  592. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  593. writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ;
  594. /*
  595. * Use this as a test byte, if it comes back with the same value, the command didn't work
  596. */
  597. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  598. writeb(0xff,xl_mmio + MMIO_MACDATA) ;
  599. /* Open options */
  600. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  601. writeb(0x00, xl_mmio + MMIO_MACDATA) ;
  602. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  603. writeb(0x00, xl_mmio + MMIO_MACDATA) ;
  604. /*
  605. * Node address, be careful here, the docs say you can just put zeros here and it will use
  606. * the hardware address, it doesn't, you must include the node address in the open command.
  607. */
  608. if (xl_priv->xl_laa[0]) { /* If using a LAA address */
  609. for (i=10;i<16;i++) {
  610. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  611. writeb(xl_priv->xl_laa[i-10],xl_mmio + MMIO_MACDATA) ;
  612. }
  613. memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ;
  614. } else { /* Regular hardware address */
  615. for (i=10;i<16;i++) {
  616. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  617. writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ;
  618. }
  619. }
  620. /* Default everything else to 0 */
  621. for (i = 16; i < 34; i++) {
  622. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  623. writeb(0x00,xl_mmio + MMIO_MACDATA) ;
  624. }
  625. /*
  626. * Set the csrb bit in the MISR register
  627. */
  628. xl_wait_misr_flags(dev) ;
  629. writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  630. writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
  631. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  632. writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ;
  633. /*
  634. * Now wait for the command to run
  635. */
  636. t=jiffies;
  637. while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
  638. schedule();
  639. if(jiffies-t > 40*HZ) {
  640. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  641. break ;
  642. }
  643. }
  644. /*
  645. * Let's interpret the open response
  646. */
  647. writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  648. if (readb(xl_mmio + MMIO_MACDATA)!=0) {
  649. open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ;
  650. writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  651. open_err |= readb(xl_mmio + MMIO_MACDATA) ;
  652. return open_err ;
  653. } else {
  654. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  655. xl_priv->asb = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
  656. printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ;
  657. printk("ASB: %04x",xl_priv->asb ) ;
  658. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  659. printk(", SRB: %04x",ntohs(readw(xl_mmio + MMIO_MACDATA)) ) ;
  660. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  661. xl_priv->arb = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
  662. printk(", ARB: %04x \n",xl_priv->arb ) ;
  663. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  664. vsoff = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
  665. /*
  666. * Interesting, sending the individual characters directly to printk was causing klogd to use
  667. * use 100% of processor time, so we build up the string and print that instead.
  668. */
  669. for (i=0;i<0x20;i++) {
  670. writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  671. ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ;
  672. }
  673. ver_str[i] = '\0' ;
  674. printk(KERN_INFO "%s: Microcode version String: %s \n",dev->name,ver_str);
  675. }
  676. /*
  677. * Issue the AckInterrupt
  678. */
  679. writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  680. return 0 ;
  681. }
  682. /*
  683. * There are two ways of implementing rx on the 359 NIC, either
  684. * interrupt driven or polling. We are going to uses interrupts,
  685. * it is the easier way of doing things.
  686. *
  687. * The Rx works with a ring of Rx descriptors. At initialise time the ring
  688. * entries point to the next entry except for the last entry in the ring
  689. * which points to 0. The card is programmed with the location of the first
  690. * available descriptor and keeps reading the next_ptr until next_ptr is set
  691. * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr
  692. * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers
  693. * and then point the end of the ring to our current position and point our current
  694. * position to 0, therefore making the current position the last position on the ring.
  695. * The last position on the ring therefore loops continually loops around the rx ring.
  696. *
  697. * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head
  698. * expands as the card adds new packets and we go around eating the tail processing the
  699. * packets.)
  700. *
  701. * Undoubtably it could be streamlined and improved upon, but at the moment it works
  702. * and the fast path through the routine is fine.
  703. *
  704. * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times
  705. * in xl_rx so would increase the size of the function significantly.
  706. */
  707. static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */
  708. {
  709. struct xl_private *xl_priv=netdev_priv(dev);
  710. int prev_ring_loc ;
  711. prev_ring_loc = (xl_priv->rx_ring_tail + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1);
  712. xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * xl_priv->rx_ring_tail) ;
  713. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus = 0 ;
  714. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upnextptr = 0 ;
  715. xl_priv->rx_ring_tail++ ;
  716. xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1) ;
  717. return ;
  718. }
  719. static void xl_rx(struct net_device *dev)
  720. {
  721. struct xl_private *xl_priv=netdev_priv(dev);
  722. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  723. struct sk_buff *skb, *skb2 ;
  724. int frame_length = 0, copy_len = 0 ;
  725. int temp_ring_loc ;
  726. /*
  727. * Receive the next frame, loop around the ring until all frames
  728. * have been received.
  729. */
  730. while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */
  731. if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */
  732. /*
  733. * This is a pain, you need to go through all the descriptors until the last one
  734. * for this frame to find the framelength
  735. */
  736. temp_ring_loc = xl_priv->rx_ring_tail ;
  737. while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) {
  738. temp_ring_loc++ ;
  739. temp_ring_loc &= (XL_RX_RING_SIZE-1) ;
  740. }
  741. frame_length = xl_priv->xl_rx_ring[temp_ring_loc].framestatus & 0x7FFF ;
  742. skb = dev_alloc_skb(frame_length) ;
  743. if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */
  744. printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ;
  745. while (xl_priv->rx_ring_tail != temp_ring_loc)
  746. adv_rx_ring(dev) ;
  747. adv_rx_ring(dev) ; /* One more time just for luck :) */
  748. xl_priv->xl_stats.rx_dropped++ ;
  749. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  750. return ;
  751. }
  752. while (xl_priv->rx_ring_tail != temp_ring_loc) {
  753. copy_len = xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen & 0x7FFF ;
  754. frame_length -= copy_len ;
  755. pci_dma_sync_single_for_cpu(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  756. skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
  757. skb_put(skb, copy_len),
  758. copy_len);
  759. pci_dma_sync_single_for_device(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  760. adv_rx_ring(dev) ;
  761. }
  762. /* Now we have found the last fragment */
  763. pci_dma_sync_single_for_cpu(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  764. skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
  765. skb_put(skb,copy_len), frame_length);
  766. /* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */
  767. pci_dma_sync_single_for_device(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  768. adv_rx_ring(dev) ;
  769. skb->protocol = tr_type_trans(skb,dev) ;
  770. netif_rx(skb) ;
  771. } else { /* Single Descriptor Used, simply swap buffers over, fast path */
  772. frame_length = xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & 0x7FFF ;
  773. skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
  774. if (skb==NULL) { /* Still need to fix the rx ring */
  775. printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ;
  776. adv_rx_ring(dev) ;
  777. xl_priv->xl_stats.rx_dropped++ ;
  778. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  779. return ;
  780. }
  781. skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ;
  782. pci_unmap_single(xl_priv->pdev, xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr, xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  783. skb_put(skb2, frame_length) ;
  784. skb2->protocol = tr_type_trans(skb2,dev) ;
  785. xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ;
  786. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
  787. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = xl_priv->pkt_buf_sz | RXUPLASTFRAG ;
  788. adv_rx_ring(dev) ;
  789. xl_priv->xl_stats.rx_packets++ ;
  790. xl_priv->xl_stats.rx_bytes += frame_length ;
  791. netif_rx(skb2) ;
  792. } /* if multiple buffers */
  793. dev->last_rx = jiffies ;
  794. } /* while packet to do */
  795. /* Clear the updComplete interrupt */
  796. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  797. return ;
  798. }
  799. /*
  800. * This is ruthless, it doesn't care what state the card is in it will
  801. * completely reset the adapter.
  802. */
  803. static void xl_reset(struct net_device *dev)
  804. {
  805. struct xl_private *xl_priv=netdev_priv(dev);
  806. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  807. unsigned long t;
  808. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  809. /*
  810. * Must wait for cmdInProgress bit (12) to clear before continuing with
  811. * card configuration.
  812. */
  813. t=jiffies;
  814. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  815. if(jiffies-t > 40*HZ) {
  816. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  817. break ;
  818. }
  819. }
  820. }
  821. static void xl_freemem(struct net_device *dev)
  822. {
  823. struct xl_private *xl_priv=netdev_priv(dev);
  824. int i ;
  825. for (i=0;i<XL_RX_RING_SIZE;i++) {
  826. dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ;
  827. pci_unmap_single(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
  828. xl_priv->rx_ring_tail++ ;
  829. xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1;
  830. }
  831. /* unmap ring */
  832. pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ;
  833. pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ;
  834. kfree(xl_priv->xl_rx_ring) ;
  835. kfree(xl_priv->xl_tx_ring) ;
  836. return ;
  837. }
  838. static irqreturn_t xl_interrupt(int irq, void *dev_id)
  839. {
  840. struct net_device *dev = (struct net_device *)dev_id;
  841. struct xl_private *xl_priv =netdev_priv(dev);
  842. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  843. u16 intstatus, macstatus ;
  844. intstatus = readw(xl_mmio + MMIO_INTSTATUS) ;
  845. if (!(intstatus & 1)) /* We didn't generate the interrupt */
  846. return IRQ_NONE;
  847. spin_lock(&xl_priv->xl_lock) ;
  848. /*
  849. * Process the interrupt
  850. */
  851. /*
  852. * Something fishy going on here, we shouldn't get 0001 ints, not fatal though.
  853. */
  854. if (intstatus == 0x0001) {
  855. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  856. printk(KERN_INFO "%s: 00001 int received \n",dev->name) ;
  857. } else {
  858. if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) {
  859. /*
  860. * Host Error.
  861. * It may be possible to recover from this, but usually it means something
  862. * is seriously fubar, so we just close the adapter.
  863. */
  864. if (intstatus & HOSTERRINT) {
  865. printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x \n",dev->name,intstatus) ;
  866. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  867. printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
  868. netif_stop_queue(dev) ;
  869. xl_freemem(dev) ;
  870. free_irq(dev->irq,dev);
  871. xl_reset(dev) ;
  872. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  873. spin_unlock(&xl_priv->xl_lock) ;
  874. return IRQ_HANDLED;
  875. } /* Host Error */
  876. if (intstatus & SRBRINT ) { /* Srbc interrupt */
  877. writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  878. if (xl_priv->srb_queued)
  879. xl_srb_bh(dev) ;
  880. } /* SRBR Interrupt */
  881. if (intstatus & TXUNDERRUN) { /* Issue DnReset command */
  882. writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  883. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */
  884. /* !!! FIX-ME !!!!
  885. Must put a timeout check here ! */
  886. /* Empty Loop */
  887. }
  888. printk(KERN_WARNING "%s: TX Underrun received \n",dev->name) ;
  889. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  890. } /* TxUnderRun */
  891. if (intstatus & ARBCINT ) { /* Arbc interrupt */
  892. xl_arb_cmd(dev) ;
  893. } /* Arbc */
  894. if (intstatus & ASBFINT) {
  895. if (xl_priv->asb_queued == 1) {
  896. xl_asb_cmd(dev) ;
  897. } else if (xl_priv->asb_queued == 2) {
  898. xl_asb_bh(dev) ;
  899. } else {
  900. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  901. }
  902. } /* Asbf */
  903. if (intstatus & UPCOMPINT ) /* UpComplete */
  904. xl_rx(dev) ;
  905. if (intstatus & DNCOMPINT ) /* DnComplete */
  906. xl_dn_comp(dev) ;
  907. if (intstatus & HARDERRINT ) { /* Hardware error */
  908. writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  909. macstatus = readw(xl_mmio + MMIO_MACDATA) ;
  910. printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name);
  911. if (macstatus & (1<<14))
  912. printk(KERN_WARNING "tchk error: Unrecoverable error \n") ;
  913. if (macstatus & (1<<3))
  914. printk(KERN_WARNING "eint error: Internal watchdog timer expired \n") ;
  915. if (macstatus & (1<<2))
  916. printk(KERN_WARNING "aint error: Host tried to perform invalid operation \n") ;
  917. printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ;
  918. printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
  919. netif_stop_queue(dev) ;
  920. xl_freemem(dev) ;
  921. free_irq(dev->irq,dev);
  922. unregister_netdev(dev) ;
  923. free_netdev(dev) ;
  924. xl_reset(dev) ;
  925. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  926. spin_unlock(&xl_priv->xl_lock) ;
  927. return IRQ_HANDLED;
  928. }
  929. } else {
  930. printk(KERN_WARNING "%s: Received Unknown interrupt : %04x \n", dev->name, intstatus) ;
  931. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  932. }
  933. }
  934. /* Turn interrupts back on */
  935. writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  936. writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  937. spin_unlock(&xl_priv->xl_lock) ;
  938. return IRQ_HANDLED;
  939. }
  940. /*
  941. * Tx - Polling configuration
  942. */
  943. static int xl_xmit(struct sk_buff *skb, struct net_device *dev)
  944. {
  945. struct xl_private *xl_priv=netdev_priv(dev);
  946. struct xl_tx_desc *txd ;
  947. int tx_head, tx_tail, tx_prev ;
  948. unsigned long flags ;
  949. spin_lock_irqsave(&xl_priv->xl_lock,flags) ;
  950. netif_stop_queue(dev) ;
  951. if (xl_priv->free_ring_entries > 1 ) {
  952. /*
  953. * Set up the descriptor for the packet
  954. */
  955. tx_head = xl_priv->tx_ring_head ;
  956. tx_tail = xl_priv->tx_ring_tail ;
  957. txd = &(xl_priv->xl_tx_ring[tx_head]) ;
  958. txd->dnnextptr = 0 ;
  959. txd->framestartheader = skb->len | TXDNINDICATE ;
  960. txd->buffer = pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE) ;
  961. txd->buffer_length = skb->len | TXDNFRAGLAST ;
  962. xl_priv->tx_ring_skb[tx_head] = skb ;
  963. xl_priv->xl_stats.tx_packets++ ;
  964. xl_priv->xl_stats.tx_bytes += skb->len ;
  965. /*
  966. * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1
  967. * to ensure no negative numbers in unsigned locations.
  968. */
  969. tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ;
  970. xl_priv->tx_ring_head++ ;
  971. xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ;
  972. xl_priv->free_ring_entries-- ;
  973. xl_priv->xl_tx_ring[tx_prev].dnnextptr = xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head) ;
  974. /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */
  975. /* readl(xl_mmio + MMIO_DNLISTPTR) ; */
  976. netif_wake_queue(dev) ;
  977. spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
  978. return 0;
  979. } else {
  980. spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
  981. return 1;
  982. }
  983. }
  984. /*
  985. * The NIC has told us that a packet has been downloaded onto the card, we must
  986. * find out which packet it has done, clear the skb and information for the packet
  987. * then advance around the ring for all tranmitted packets
  988. */
  989. static void xl_dn_comp(struct net_device *dev)
  990. {
  991. struct xl_private *xl_priv=netdev_priv(dev);
  992. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  993. struct xl_tx_desc *txd ;
  994. if (xl_priv->tx_ring_tail == 255) {/* First time */
  995. xl_priv->xl_tx_ring[0].framestartheader = 0 ;
  996. xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
  997. xl_priv->tx_ring_tail = 1 ;
  998. }
  999. while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) {
  1000. txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ;
  1001. pci_unmap_single(xl_priv->pdev,txd->buffer, xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE) ;
  1002. txd->framestartheader = 0 ;
  1003. txd->buffer = 0xdeadbeef ;
  1004. txd->buffer_length = 0 ;
  1005. dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ;
  1006. xl_priv->tx_ring_tail++ ;
  1007. xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ;
  1008. xl_priv->free_ring_entries++ ;
  1009. }
  1010. netif_wake_queue(dev) ;
  1011. writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  1012. }
  1013. /*
  1014. * Close the adapter properly.
  1015. * This srb reply cannot be handled from interrupt context as we have
  1016. * to free the interrupt from the driver.
  1017. */
  1018. static int xl_close(struct net_device *dev)
  1019. {
  1020. struct xl_private *xl_priv = netdev_priv(dev);
  1021. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1022. unsigned long t ;
  1023. netif_stop_queue(dev) ;
  1024. /*
  1025. * Close the adapter, need to stall the rx and tx queues.
  1026. */
  1027. writew(DNSTALL, xl_mmio + MMIO_COMMAND) ;
  1028. t=jiffies;
  1029. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1030. schedule();
  1031. if(jiffies-t > 10*HZ) {
  1032. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name);
  1033. break ;
  1034. }
  1035. }
  1036. writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ;
  1037. t=jiffies;
  1038. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1039. schedule();
  1040. if(jiffies-t > 10*HZ) {
  1041. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name);
  1042. break ;
  1043. }
  1044. }
  1045. writew(UPSTALL, xl_mmio + MMIO_COMMAND) ;
  1046. t=jiffies;
  1047. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1048. schedule();
  1049. if(jiffies-t > 10*HZ) {
  1050. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name);
  1051. break ;
  1052. }
  1053. }
  1054. /* Turn off interrupts, we will still get the indication though
  1055. * so we can trap it
  1056. */
  1057. writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ;
  1058. xl_srb_cmd(dev,CLOSE_NIC) ;
  1059. t=jiffies;
  1060. while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
  1061. schedule();
  1062. if(jiffies-t > 10*HZ) {
  1063. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name);
  1064. break ;
  1065. }
  1066. }
  1067. /* Read the srb response from the adapter */
  1068. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1069. if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) {
  1070. printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response \n",dev->name) ;
  1071. } else {
  1072. writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1073. if (readb(xl_mmio + MMIO_MACDATA)==0) {
  1074. printk(KERN_INFO "%s: Adapter has been closed \n",dev->name) ;
  1075. writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1076. xl_freemem(dev) ;
  1077. free_irq(dev->irq,dev) ;
  1078. } else {
  1079. printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ;
  1080. }
  1081. }
  1082. /* Reset the upload and download logic */
  1083. writew(UPRESET, xl_mmio + MMIO_COMMAND) ;
  1084. t=jiffies;
  1085. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1086. schedule();
  1087. if(jiffies-t > 10*HZ) {
  1088. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name);
  1089. break ;
  1090. }
  1091. }
  1092. writew(DNRESET, xl_mmio + MMIO_COMMAND) ;
  1093. t=jiffies;
  1094. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1095. schedule();
  1096. if(jiffies-t > 10*HZ) {
  1097. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name);
  1098. break ;
  1099. }
  1100. }
  1101. xl_hw_reset(dev) ;
  1102. return 0 ;
  1103. }
  1104. static void xl_set_rx_mode(struct net_device *dev)
  1105. {
  1106. struct xl_private *xl_priv = netdev_priv(dev);
  1107. struct dev_mc_list *dmi ;
  1108. unsigned char dev_mc_address[4] ;
  1109. u16 options ;
  1110. int i ;
  1111. if (dev->flags & IFF_PROMISC)
  1112. options = 0x0004 ;
  1113. else
  1114. options = 0x0000 ;
  1115. if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */
  1116. xl_priv->xl_copy_all_options = options ;
  1117. xl_srb_cmd(dev, SET_RECEIVE_MODE) ;
  1118. return ;
  1119. }
  1120. dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
  1121. for (i=0,dmi=dev->mc_list;i < dev->mc_count; i++,dmi = dmi->next) {
  1122. dev_mc_address[0] |= dmi->dmi_addr[2] ;
  1123. dev_mc_address[1] |= dmi->dmi_addr[3] ;
  1124. dev_mc_address[2] |= dmi->dmi_addr[4] ;
  1125. dev_mc_address[3] |= dmi->dmi_addr[5] ;
  1126. }
  1127. if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */
  1128. memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ;
  1129. xl_srb_cmd(dev, SET_FUNC_ADDRESS) ;
  1130. }
  1131. return ;
  1132. }
  1133. /*
  1134. * We issued an srb command and now we must read
  1135. * the response from the completed command.
  1136. */
  1137. static void xl_srb_bh(struct net_device *dev)
  1138. {
  1139. struct xl_private *xl_priv = netdev_priv(dev);
  1140. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1141. u8 srb_cmd, ret_code ;
  1142. int i ;
  1143. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1144. srb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
  1145. writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1146. ret_code = readb(xl_mmio + MMIO_MACDATA) ;
  1147. /* Ret_code is standard across all commands */
  1148. switch (ret_code) {
  1149. case 1:
  1150. printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ;
  1151. break ;
  1152. case 4:
  1153. printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command \n",dev->name,srb_cmd) ;
  1154. break ;
  1155. case 6:
  1156. printk(KERN_INFO "%s: Command: %d - Options Invalid for command \n",dev->name,srb_cmd) ;
  1157. break ;
  1158. case 0: /* Successful command execution */
  1159. switch (srb_cmd) {
  1160. case READ_LOG: /* Returns 14 bytes of data from the NIC */
  1161. if(xl_priv->xl_message_level)
  1162. printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ;
  1163. /*
  1164. * We still have to read the log even if message_level = 0 and we don't want
  1165. * to see it
  1166. */
  1167. for (i=0;i<14;i++) {
  1168. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1169. if(xl_priv->xl_message_level)
  1170. printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ;
  1171. }
  1172. printk("\n") ;
  1173. break ;
  1174. case SET_FUNC_ADDRESS:
  1175. if(xl_priv->xl_message_level)
  1176. printk(KERN_INFO "%s: Functional Address Set \n",dev->name) ;
  1177. break ;
  1178. case CLOSE_NIC:
  1179. if(xl_priv->xl_message_level)
  1180. printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler \n",dev->name) ;
  1181. break ;
  1182. case SET_MULTICAST_MODE:
  1183. if(xl_priv->xl_message_level)
  1184. printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ;
  1185. break ;
  1186. case SET_RECEIVE_MODE:
  1187. if(xl_priv->xl_message_level) {
  1188. if (xl_priv->xl_copy_all_options == 0x0004)
  1189. printk(KERN_INFO "%s: Entering promiscuous mode \n", dev->name) ;
  1190. else
  1191. printk(KERN_INFO "%s: Entering normal receive mode \n",dev->name) ;
  1192. }
  1193. break ;
  1194. } /* switch */
  1195. break ;
  1196. } /* switch */
  1197. return ;
  1198. }
  1199. static struct net_device_stats * xl_get_stats(struct net_device *dev)
  1200. {
  1201. struct xl_private *xl_priv = netdev_priv(dev);
  1202. return (struct net_device_stats *) &xl_priv->xl_stats;
  1203. }
  1204. static int xl_set_mac_address (struct net_device *dev, void *addr)
  1205. {
  1206. struct sockaddr *saddr = addr ;
  1207. struct xl_private *xl_priv = netdev_priv(dev);
  1208. if (netif_running(dev)) {
  1209. printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
  1210. return -EIO ;
  1211. }
  1212. memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ;
  1213. if (xl_priv->xl_message_level) {
  1214. printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0],
  1215. xl_priv->xl_laa[1], xl_priv->xl_laa[2],
  1216. xl_priv->xl_laa[3], xl_priv->xl_laa[4],
  1217. xl_priv->xl_laa[5]);
  1218. }
  1219. return 0 ;
  1220. }
  1221. static void xl_arb_cmd(struct net_device *dev)
  1222. {
  1223. struct xl_private *xl_priv = netdev_priv(dev);
  1224. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1225. u8 arb_cmd ;
  1226. u16 lan_status, lan_status_diff ;
  1227. writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1228. arb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
  1229. if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */
  1230. writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1231. printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, ntohs(readw(xl_mmio + MMIO_MACDATA) )) ;
  1232. lan_status = ntohs(readw(xl_mmio + MMIO_MACDATA));
  1233. /* Acknowledge interrupt, this tells nic we are done with the arb */
  1234. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1235. lan_status_diff = xl_priv->xl_lan_status ^ lan_status ;
  1236. if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
  1237. if (lan_status_diff & LSC_LWF)
  1238. printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
  1239. if (lan_status_diff & LSC_ARW)
  1240. printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
  1241. if (lan_status_diff & LSC_FPE)
  1242. printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
  1243. if (lan_status_diff & LSC_RR)
  1244. printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
  1245. /* Adapter has been closed by the hardware */
  1246. netif_stop_queue(dev);
  1247. xl_freemem(dev) ;
  1248. free_irq(dev->irq,dev);
  1249. printk(KERN_WARNING "%s: Adapter has been closed \n", dev->name) ;
  1250. } /* If serious error */
  1251. if (xl_priv->xl_message_level) {
  1252. if (lan_status_diff & LSC_SIG_LOSS)
  1253. printk(KERN_WARNING "%s: No receive signal detected \n", dev->name) ;
  1254. if (lan_status_diff & LSC_HARD_ERR)
  1255. printk(KERN_INFO "%s: Beaconing \n",dev->name);
  1256. if (lan_status_diff & LSC_SOFT_ERR)
  1257. printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n",dev->name);
  1258. if (lan_status_diff & LSC_TRAN_BCN)
  1259. printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name);
  1260. if (lan_status_diff & LSC_SS)
  1261. printk(KERN_INFO "%s: Single Station on the ring \n", dev->name);
  1262. if (lan_status_diff & LSC_RING_REC)
  1263. printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
  1264. if (lan_status_diff & LSC_FDX_MODE)
  1265. printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
  1266. }
  1267. if (lan_status_diff & LSC_CO) {
  1268. if (xl_priv->xl_message_level)
  1269. printk(KERN_INFO "%s: Counter Overflow \n", dev->name);
  1270. /* Issue READ.LOG command */
  1271. xl_srb_cmd(dev, READ_LOG) ;
  1272. }
  1273. /* There is no command in the tech docs to issue the read_sr_counters */
  1274. if (lan_status_diff & LSC_SR_CO) {
  1275. if (xl_priv->xl_message_level)
  1276. printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
  1277. }
  1278. xl_priv->xl_lan_status = lan_status ;
  1279. } /* Lan.change.status */
  1280. else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */
  1281. #if XL_DEBUG
  1282. printk(KERN_INFO "Received.Data \n") ;
  1283. #endif
  1284. writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1285. xl_priv->mac_buffer = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
  1286. /* Now we are going to be really basic here and not do anything
  1287. * with the data at all. The tech docs do not give me enough
  1288. * information to calculate the buffers properly so we're
  1289. * just going to tell the nic that we've dealt with the frame
  1290. * anyway.
  1291. */
  1292. dev->last_rx = jiffies ;
  1293. /* Acknowledge interrupt, this tells nic we are done with the arb */
  1294. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1295. /* Is the ASB free ? */
  1296. xl_priv->asb_queued = 0 ;
  1297. writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1298. if (readb(xl_mmio + MMIO_MACDATA) != 0xff) {
  1299. xl_priv->asb_queued = 1 ;
  1300. xl_wait_misr_flags(dev) ;
  1301. writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1302. writeb(0xff, xl_mmio + MMIO_MACDATA) ;
  1303. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1304. writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ;
  1305. return ;
  1306. /* Drop out and wait for the bottom half to be run */
  1307. }
  1308. xl_asb_cmd(dev) ;
  1309. } else {
  1310. printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x \n",dev->name,arb_cmd) ;
  1311. }
  1312. /* Acknowledge the arb interrupt */
  1313. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  1314. return ;
  1315. }
  1316. /*
  1317. * There is only one asb command, but we can get called from different
  1318. * places.
  1319. */
  1320. static void xl_asb_cmd(struct net_device *dev)
  1321. {
  1322. struct xl_private *xl_priv = netdev_priv(dev);
  1323. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1324. if (xl_priv->asb_queued == 1)
  1325. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  1326. writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1327. writeb(0x81, xl_mmio + MMIO_MACDATA) ;
  1328. writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1329. writew(ntohs(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ;
  1330. xl_wait_misr_flags(dev) ;
  1331. writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1332. writeb(0xff, xl_mmio + MMIO_MACDATA) ;
  1333. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1334. writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ;
  1335. xl_priv->asb_queued = 2 ;
  1336. return ;
  1337. }
  1338. /*
  1339. * This will only get called if there was an error
  1340. * from the asb cmd.
  1341. */
  1342. static void xl_asb_bh(struct net_device *dev)
  1343. {
  1344. struct xl_private *xl_priv = netdev_priv(dev);
  1345. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1346. u8 ret_code ;
  1347. writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1348. ret_code = readb(xl_mmio + MMIO_MACDATA) ;
  1349. switch (ret_code) {
  1350. case 0x01:
  1351. printk(KERN_INFO "%s: ASB Command, unrecognized command code \n",dev->name) ;
  1352. break ;
  1353. case 0x26:
  1354. printk(KERN_INFO "%s: ASB Command, unexpected receive buffer \n", dev->name) ;
  1355. break ;
  1356. case 0x40:
  1357. printk(KERN_INFO "%s: ASB Command, Invalid Station ID \n", dev->name) ;
  1358. break ;
  1359. }
  1360. xl_priv->asb_queued = 0 ;
  1361. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  1362. return ;
  1363. }
  1364. /*
  1365. * Issue srb commands to the nic
  1366. */
  1367. static void xl_srb_cmd(struct net_device *dev, int srb_cmd)
  1368. {
  1369. struct xl_private *xl_priv = netdev_priv(dev);
  1370. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1371. switch (srb_cmd) {
  1372. case READ_LOG:
  1373. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1374. writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ;
  1375. break;
  1376. case CLOSE_NIC:
  1377. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1378. writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ;
  1379. break ;
  1380. case SET_RECEIVE_MODE:
  1381. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1382. writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ;
  1383. writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1384. writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ;
  1385. break ;
  1386. case SET_FUNC_ADDRESS:
  1387. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1388. writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ;
  1389. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1390. writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ;
  1391. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1392. writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ;
  1393. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1394. writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ;
  1395. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1396. writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ;
  1397. break ;
  1398. } /* switch */
  1399. xl_wait_misr_flags(dev) ;
  1400. /* Write 0xff to the CSRB flag */
  1401. writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1402. writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
  1403. /* Set csrb bit in MISR register to process command */
  1404. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1405. writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ;
  1406. xl_priv->srb_queued = 1 ;
  1407. return ;
  1408. }
  1409. /*
  1410. * This is nasty, to use the MISR command you have to wait for 6 memory locations
  1411. * to be zero. This is the way the driver does on other OS'es so we should be ok with
  1412. * the empty loop.
  1413. */
  1414. static void xl_wait_misr_flags(struct net_device *dev)
  1415. {
  1416. struct xl_private *xl_priv = netdev_priv(dev);
  1417. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1418. int i ;
  1419. writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1420. if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */
  1421. for (i=0; i<6; i++) {
  1422. writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1423. while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */
  1424. }
  1425. }
  1426. writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1427. writeb(0x80, xl_mmio + MMIO_MACDATA) ;
  1428. return ;
  1429. }
  1430. /*
  1431. * Change mtu size, this should work the same as olympic
  1432. */
  1433. static int xl_change_mtu(struct net_device *dev, int mtu)
  1434. {
  1435. struct xl_private *xl_priv = netdev_priv(dev);
  1436. u16 max_mtu ;
  1437. if (xl_priv->xl_ring_speed == 4)
  1438. max_mtu = 4500 ;
  1439. else
  1440. max_mtu = 18000 ;
  1441. if (mtu > max_mtu)
  1442. return -EINVAL ;
  1443. if (mtu < 100)
  1444. return -EINVAL ;
  1445. dev->mtu = mtu ;
  1446. xl_priv->pkt_buf_sz = mtu + TR_HLEN ;
  1447. return 0 ;
  1448. }
  1449. static void __devexit xl_remove_one (struct pci_dev *pdev)
  1450. {
  1451. struct net_device *dev = pci_get_drvdata(pdev);
  1452. struct xl_private *xl_priv=netdev_priv(dev);
  1453. unregister_netdev(dev);
  1454. iounmap(xl_priv->xl_mmio) ;
  1455. pci_release_regions(pdev) ;
  1456. pci_set_drvdata(pdev,NULL) ;
  1457. free_netdev(dev);
  1458. return ;
  1459. }
  1460. static struct pci_driver xl_3c359_driver = {
  1461. .name = "3c359",
  1462. .id_table = xl_pci_tbl,
  1463. .probe = xl_probe,
  1464. .remove = __devexit_p(xl_remove_one),
  1465. };
  1466. static int __init xl_pci_init (void)
  1467. {
  1468. return pci_register_driver(&xl_3c359_driver);
  1469. }
  1470. static void __exit xl_pci_cleanup (void)
  1471. {
  1472. pci_unregister_driver (&xl_3c359_driver);
  1473. }
  1474. module_init(xl_pci_init);
  1475. module_exit(xl_pci_cleanup);
  1476. MODULE_LICENSE("GPL") ;