via-ircc.c 42 KB

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  1. /********************************************************************
  2. Filename: via-ircc.c
  3. Version: 1.0
  4. Description: Driver for the VIA VT8231/VT8233 IrDA chipsets
  5. Author: VIA Technologies,inc
  6. Date : 08/06/2003
  7. Copyright (c) 1998-2003 VIA Technologies, Inc.
  8. This program is free software; you can redistribute it and/or modify it under
  9. the terms of the GNU General Public License as published by the Free Software
  10. Foundation; either version 2, or (at your option) any later version.
  11. This program is distributed in the hope that it will be useful, but WITHOUT
  12. ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  14. See the GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License along with
  16. this program; if not, write to the Free Software Foundation, Inc.,
  17. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. F01 Oct/02/02: Modify code for V0.11(move out back to back transfer)
  19. F02 Oct/28/02: Add SB device ID for 3147 and 3177.
  20. Comment :
  21. jul/09/2002 : only implement two kind of dongle currently.
  22. Oct/02/2002 : work on VT8231 and VT8233 .
  23. Aug/06/2003 : change driver format to pci driver .
  24. 2004-02-16: <sda@bdit.de>
  25. - Removed unneeded 'legacy' pci stuff.
  26. - Make sure SIR mode is set (hw_init()) before calling mode-dependant stuff.
  27. - On speed change from core, don't send SIR frame with new speed.
  28. Use current speed and change speeds later.
  29. - Make module-param dongle_id actually work.
  30. - New dongle_id 17 (0x11): TDFS4500. Single-ended SIR only.
  31. Tested with home-grown PCB on EPIA boards.
  32. - Code cleanup.
  33. ********************************************************************/
  34. #include <linux/module.h>
  35. #include <linux/kernel.h>
  36. #include <linux/types.h>
  37. #include <linux/skbuff.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/ioport.h>
  40. #include <linux/delay.h>
  41. #include <linux/slab.h>
  42. #include <linux/init.h>
  43. #include <linux/rtnetlink.h>
  44. #include <linux/pci.h>
  45. #include <linux/dma-mapping.h>
  46. #include <asm/io.h>
  47. #include <asm/dma.h>
  48. #include <asm/byteorder.h>
  49. #include <linux/pm.h>
  50. #include <net/irda/wrapper.h>
  51. #include <net/irda/irda.h>
  52. #include <net/irda/irda_device.h>
  53. #include "via-ircc.h"
  54. #define VIA_MODULE_NAME "via-ircc"
  55. #define CHIP_IO_EXTENT 0x40
  56. static char *driver_name = VIA_MODULE_NAME;
  57. /* Module parameters */
  58. static int qos_mtt_bits = 0x07; /* 1 ms or more */
  59. static int dongle_id = 0; /* default: probe */
  60. /* We can't guess the type of connected dongle, user *must* supply it. */
  61. module_param(dongle_id, int, 0);
  62. /* FIXME : we should not need this, because instances should be automatically
  63. * managed by the PCI layer. Especially that we seem to only be using the
  64. * first entry. Jean II */
  65. /* Max 4 instances for now */
  66. static struct via_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL };
  67. /* Some prototypes */
  68. static int via_ircc_open(int i, chipio_t * info, unsigned int id);
  69. static int via_ircc_close(struct via_ircc_cb *self);
  70. static int via_ircc_dma_receive(struct via_ircc_cb *self);
  71. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  72. int iobase);
  73. static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  74. struct net_device *dev);
  75. static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  76. struct net_device *dev);
  77. static void via_hw_init(struct via_ircc_cb *self);
  78. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 baud);
  79. static irqreturn_t via_ircc_interrupt(int irq, void *dev_id);
  80. static int via_ircc_is_receiving(struct via_ircc_cb *self);
  81. static int via_ircc_read_dongle_id(int iobase);
  82. static int via_ircc_net_open(struct net_device *dev);
  83. static int via_ircc_net_close(struct net_device *dev);
  84. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  85. int cmd);
  86. static struct net_device_stats *via_ircc_net_get_stats(struct net_device
  87. *dev);
  88. static void via_ircc_change_dongle_speed(int iobase, int speed,
  89. int dongle_id);
  90. static int RxTimerHandler(struct via_ircc_cb *self, int iobase);
  91. static void hwreset(struct via_ircc_cb *self);
  92. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase);
  93. static int upload_rxdata(struct via_ircc_cb *self, int iobase);
  94. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id);
  95. static void __devexit via_remove_one (struct pci_dev *pdev);
  96. /* FIXME : Should use udelay() instead, even if we are x86 only - Jean II */
  97. static void iodelay(int udelay)
  98. {
  99. u8 data;
  100. int i;
  101. for (i = 0; i < udelay; i++) {
  102. data = inb(0x80);
  103. }
  104. }
  105. static struct pci_device_id via_pci_tbl[] = {
  106. { PCI_VENDOR_ID_VIA, 0x8231, PCI_ANY_ID, PCI_ANY_ID,0,0,0 },
  107. { PCI_VENDOR_ID_VIA, 0x3109, PCI_ANY_ID, PCI_ANY_ID,0,0,1 },
  108. { PCI_VENDOR_ID_VIA, 0x3074, PCI_ANY_ID, PCI_ANY_ID,0,0,2 },
  109. { PCI_VENDOR_ID_VIA, 0x3147, PCI_ANY_ID, PCI_ANY_ID,0,0,3 },
  110. { PCI_VENDOR_ID_VIA, 0x3177, PCI_ANY_ID, PCI_ANY_ID,0,0,4 },
  111. { 0, }
  112. };
  113. MODULE_DEVICE_TABLE(pci,via_pci_tbl);
  114. static struct pci_driver via_driver = {
  115. .name = VIA_MODULE_NAME,
  116. .id_table = via_pci_tbl,
  117. .probe = via_init_one,
  118. .remove = __devexit_p(via_remove_one),
  119. };
  120. /*
  121. * Function via_ircc_init ()
  122. *
  123. * Initialize chip. Just find out chip type and resource.
  124. */
  125. static int __init via_ircc_init(void)
  126. {
  127. int rc;
  128. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  129. rc = pci_register_driver(&via_driver);
  130. if (rc < 0) {
  131. IRDA_DEBUG(0, "%s(): error rc = %d, returning -ENODEV...\n",
  132. __FUNCTION__, rc);
  133. return -ENODEV;
  134. }
  135. return 0;
  136. }
  137. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id)
  138. {
  139. int rc;
  140. u8 temp,oldPCI_40,oldPCI_44,bTmp,bTmp1;
  141. u16 Chipset,FirDRQ1,FirDRQ0,FirIRQ,FirIOBase;
  142. chipio_t info;
  143. IRDA_DEBUG(2, "%s(): Device ID=(0X%X)\n", __FUNCTION__, id->device);
  144. rc = pci_enable_device (pcidev);
  145. if (rc) {
  146. IRDA_DEBUG(0, "%s(): error rc = %d\n", __FUNCTION__, rc);
  147. return -ENODEV;
  148. }
  149. // South Bridge exist
  150. if ( ReadLPCReg(0x20) != 0x3C )
  151. Chipset=0x3096;
  152. else
  153. Chipset=0x3076;
  154. if (Chipset==0x3076) {
  155. IRDA_DEBUG(2, "%s(): Chipset = 3076\n", __FUNCTION__);
  156. WriteLPCReg(7,0x0c );
  157. temp=ReadLPCReg(0x30);//check if BIOS Enable Fir
  158. if((temp&0x01)==1) { // BIOS close or no FIR
  159. WriteLPCReg(0x1d, 0x82 );
  160. WriteLPCReg(0x23,0x18);
  161. temp=ReadLPCReg(0xF0);
  162. if((temp&0x01)==0) {
  163. temp=(ReadLPCReg(0x74)&0x03); //DMA
  164. FirDRQ0=temp + 4;
  165. temp=(ReadLPCReg(0x74)&0x0C) >> 2;
  166. FirDRQ1=temp + 4;
  167. } else {
  168. temp=(ReadLPCReg(0x74)&0x0C) >> 2; //DMA
  169. FirDRQ0=temp + 4;
  170. FirDRQ1=FirDRQ0;
  171. }
  172. FirIRQ=(ReadLPCReg(0x70)&0x0f); //IRQ
  173. FirIOBase=ReadLPCReg(0x60 ) << 8; //IO Space :high byte
  174. FirIOBase=FirIOBase| ReadLPCReg(0x61) ; //low byte
  175. FirIOBase=FirIOBase ;
  176. info.fir_base=FirIOBase;
  177. info.irq=FirIRQ;
  178. info.dma=FirDRQ1;
  179. info.dma2=FirDRQ0;
  180. pci_read_config_byte(pcidev,0x40,&bTmp);
  181. pci_write_config_byte(pcidev,0x40,((bTmp | 0x08) & 0xfe));
  182. pci_read_config_byte(pcidev,0x42,&bTmp);
  183. pci_write_config_byte(pcidev,0x42,(bTmp | 0xf0));
  184. pci_write_config_byte(pcidev,0x5a,0xc0);
  185. WriteLPCReg(0x28, 0x70 );
  186. if (via_ircc_open(0, &info,0x3076) == 0)
  187. rc=0;
  188. } else
  189. rc = -ENODEV; //IR not turn on
  190. } else { //Not VT1211
  191. IRDA_DEBUG(2, "%s(): Chipset = 3096\n", __FUNCTION__);
  192. pci_read_config_byte(pcidev,0x67,&bTmp);//check if BIOS Enable Fir
  193. if((bTmp&0x01)==1) { // BIOS enable FIR
  194. //Enable Double DMA clock
  195. pci_read_config_byte(pcidev,0x42,&oldPCI_40);
  196. pci_write_config_byte(pcidev,0x42,oldPCI_40 | 0x80);
  197. pci_read_config_byte(pcidev,0x40,&oldPCI_40);
  198. pci_write_config_byte(pcidev,0x40,oldPCI_40 & 0xf7);
  199. pci_read_config_byte(pcidev,0x44,&oldPCI_44);
  200. pci_write_config_byte(pcidev,0x44,0x4e);
  201. //---------- read configuration from Function0 of south bridge
  202. if((bTmp&0x02)==0) {
  203. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  204. FirDRQ0 = (bTmp1 & 0x30) >> 4;
  205. pci_read_config_byte(pcidev,0x44,&bTmp1);
  206. FirDRQ1 = (bTmp1 & 0xc0) >> 6;
  207. } else {
  208. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  209. FirDRQ0 = (bTmp1 & 0x30) >> 4 ;
  210. FirDRQ1=0;
  211. }
  212. pci_read_config_byte(pcidev,0x47,&bTmp1); //IRQ
  213. FirIRQ = bTmp1 & 0x0f;
  214. pci_read_config_byte(pcidev,0x69,&bTmp);
  215. FirIOBase = bTmp << 8;//hight byte
  216. pci_read_config_byte(pcidev,0x68,&bTmp);
  217. FirIOBase = (FirIOBase | bTmp ) & 0xfff0;
  218. //-------------------------
  219. info.fir_base=FirIOBase;
  220. info.irq=FirIRQ;
  221. info.dma=FirDRQ1;
  222. info.dma2=FirDRQ0;
  223. if (via_ircc_open(0, &info,0x3096) == 0)
  224. rc=0;
  225. } else
  226. rc = -ENODEV; //IR not turn on !!!!!
  227. }//Not VT1211
  228. IRDA_DEBUG(2, "%s(): End - rc = %d\n", __FUNCTION__, rc);
  229. return rc;
  230. }
  231. /*
  232. * Function via_ircc_clean ()
  233. *
  234. * Close all configured chips
  235. *
  236. */
  237. static void via_ircc_clean(void)
  238. {
  239. int i;
  240. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  241. for (i=0; i < ARRAY_SIZE(dev_self); i++) {
  242. if (dev_self[i])
  243. via_ircc_close(dev_self[i]);
  244. }
  245. }
  246. static void __devexit via_remove_one (struct pci_dev *pdev)
  247. {
  248. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  249. /* FIXME : This is ugly. We should use pci_get_drvdata(pdev);
  250. * to get our driver instance and call directly via_ircc_close().
  251. * See vlsi_ir for details...
  252. * Jean II */
  253. via_ircc_clean();
  254. /* FIXME : This should be in via_ircc_close(), because here we may
  255. * theoritically disable still configured devices :-( - Jean II */
  256. pci_disable_device(pdev);
  257. }
  258. static void __exit via_ircc_cleanup(void)
  259. {
  260. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  261. /* FIXME : This should be redundant, as pci_unregister_driver()
  262. * should call via_remove_one() on each device.
  263. * Jean II */
  264. via_ircc_clean();
  265. /* Cleanup all instances of the driver */
  266. pci_unregister_driver (&via_driver);
  267. }
  268. /*
  269. * Function via_ircc_open (iobase, irq)
  270. *
  271. * Open driver instance
  272. *
  273. */
  274. static __devinit int via_ircc_open(int i, chipio_t * info, unsigned int id)
  275. {
  276. struct net_device *dev;
  277. struct via_ircc_cb *self;
  278. int err;
  279. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  280. if (i >= ARRAY_SIZE(dev_self))
  281. return -ENOMEM;
  282. /* Allocate new instance of the driver */
  283. dev = alloc_irdadev(sizeof(struct via_ircc_cb));
  284. if (dev == NULL)
  285. return -ENOMEM;
  286. self = dev->priv;
  287. self->netdev = dev;
  288. spin_lock_init(&self->lock);
  289. /* FIXME : We should store our driver instance in the PCI layer,
  290. * using pci_set_drvdata(), not in this array.
  291. * See vlsi_ir for details... - Jean II */
  292. /* FIXME : 'i' is always 0 (see via_init_one()) :-( - Jean II */
  293. /* Need to store self somewhere */
  294. dev_self[i] = self;
  295. self->index = i;
  296. /* Initialize Resource */
  297. self->io.cfg_base = info->cfg_base;
  298. self->io.fir_base = info->fir_base;
  299. self->io.irq = info->irq;
  300. self->io.fir_ext = CHIP_IO_EXTENT;
  301. self->io.dma = info->dma;
  302. self->io.dma2 = info->dma2;
  303. self->io.fifo_size = 32;
  304. self->chip_id = id;
  305. self->st_fifo.len = 0;
  306. self->RxDataReady = 0;
  307. /* Reserve the ioports that we need */
  308. if (!request_region(self->io.fir_base, self->io.fir_ext, driver_name)) {
  309. IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
  310. __FUNCTION__, self->io.fir_base);
  311. err = -ENODEV;
  312. goto err_out1;
  313. }
  314. /* Initialize QoS for this device */
  315. irda_init_max_qos_capabilies(&self->qos);
  316. /* Check if user has supplied the dongle id or not */
  317. if (!dongle_id)
  318. dongle_id = via_ircc_read_dongle_id(self->io.fir_base);
  319. self->io.dongle_id = dongle_id;
  320. /* The only value we must override it the baudrate */
  321. /* Maximum speeds and capabilities are dongle-dependant. */
  322. switch( self->io.dongle_id ){
  323. case 0x0d:
  324. self->qos.baud_rate.bits =
  325. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200 |
  326. IR_576000 | IR_1152000 | (IR_4000000 << 8);
  327. break;
  328. default:
  329. self->qos.baud_rate.bits =
  330. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200;
  331. break;
  332. }
  333. /* Following was used for testing:
  334. *
  335. * self->qos.baud_rate.bits = IR_9600;
  336. *
  337. * Is is no good, as it prohibits (error-prone) speed-changes.
  338. */
  339. self->qos.min_turn_time.bits = qos_mtt_bits;
  340. irda_qos_bits_to_value(&self->qos);
  341. /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
  342. self->rx_buff.truesize = 14384 + 2048;
  343. self->tx_buff.truesize = 14384 + 2048;
  344. /* Allocate memory if needed */
  345. self->rx_buff.head =
  346. dma_alloc_coherent(NULL, self->rx_buff.truesize,
  347. &self->rx_buff_dma, GFP_KERNEL);
  348. if (self->rx_buff.head == NULL) {
  349. err = -ENOMEM;
  350. goto err_out2;
  351. }
  352. memset(self->rx_buff.head, 0, self->rx_buff.truesize);
  353. self->tx_buff.head =
  354. dma_alloc_coherent(NULL, self->tx_buff.truesize,
  355. &self->tx_buff_dma, GFP_KERNEL);
  356. if (self->tx_buff.head == NULL) {
  357. err = -ENOMEM;
  358. goto err_out3;
  359. }
  360. memset(self->tx_buff.head, 0, self->tx_buff.truesize);
  361. self->rx_buff.in_frame = FALSE;
  362. self->rx_buff.state = OUTSIDE_FRAME;
  363. self->tx_buff.data = self->tx_buff.head;
  364. self->rx_buff.data = self->rx_buff.head;
  365. /* Reset Tx queue info */
  366. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  367. self->tx_fifo.tail = self->tx_buff.head;
  368. /* Override the network functions we need to use */
  369. dev->hard_start_xmit = via_ircc_hard_xmit_sir;
  370. dev->open = via_ircc_net_open;
  371. dev->stop = via_ircc_net_close;
  372. dev->do_ioctl = via_ircc_net_ioctl;
  373. dev->get_stats = via_ircc_net_get_stats;
  374. err = register_netdev(dev);
  375. if (err)
  376. goto err_out4;
  377. IRDA_MESSAGE("IrDA: Registered device %s (via-ircc)\n", dev->name);
  378. /* Initialise the hardware..
  379. */
  380. self->io.speed = 9600;
  381. via_hw_init(self);
  382. return 0;
  383. err_out4:
  384. dma_free_coherent(NULL, self->tx_buff.truesize,
  385. self->tx_buff.head, self->tx_buff_dma);
  386. err_out3:
  387. dma_free_coherent(NULL, self->rx_buff.truesize,
  388. self->rx_buff.head, self->rx_buff_dma);
  389. err_out2:
  390. release_region(self->io.fir_base, self->io.fir_ext);
  391. err_out1:
  392. free_netdev(dev);
  393. dev_self[i] = NULL;
  394. return err;
  395. }
  396. /*
  397. * Function via_ircc_close (self)
  398. *
  399. * Close driver instance
  400. *
  401. */
  402. static int via_ircc_close(struct via_ircc_cb *self)
  403. {
  404. int iobase;
  405. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  406. IRDA_ASSERT(self != NULL, return -1;);
  407. iobase = self->io.fir_base;
  408. ResetChip(iobase, 5); //hardware reset.
  409. /* Remove netdevice */
  410. unregister_netdev(self->netdev);
  411. /* Release the PORT that this driver is using */
  412. IRDA_DEBUG(2, "%s(), Releasing Region %03x\n",
  413. __FUNCTION__, self->io.fir_base);
  414. release_region(self->io.fir_base, self->io.fir_ext);
  415. if (self->tx_buff.head)
  416. dma_free_coherent(NULL, self->tx_buff.truesize,
  417. self->tx_buff.head, self->tx_buff_dma);
  418. if (self->rx_buff.head)
  419. dma_free_coherent(NULL, self->rx_buff.truesize,
  420. self->rx_buff.head, self->rx_buff_dma);
  421. dev_self[self->index] = NULL;
  422. free_netdev(self->netdev);
  423. return 0;
  424. }
  425. /*
  426. * Function via_hw_init(self)
  427. *
  428. * Returns non-negative on success.
  429. *
  430. * Formerly via_ircc_setup
  431. */
  432. static void via_hw_init(struct via_ircc_cb *self)
  433. {
  434. int iobase = self->io.fir_base;
  435. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  436. SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095
  437. // FIFO Init
  438. EnRXFIFOReadyInt(iobase, OFF);
  439. EnRXFIFOHalfLevelInt(iobase, OFF);
  440. EnTXFIFOHalfLevelInt(iobase, OFF);
  441. EnTXFIFOUnderrunEOMInt(iobase, ON);
  442. EnTXFIFOReadyInt(iobase, OFF);
  443. InvertTX(iobase, OFF);
  444. InvertRX(iobase, OFF);
  445. if (ReadLPCReg(0x20) == 0x3c)
  446. WriteLPCReg(0xF0, 0); // for VT1211
  447. /* Int Init */
  448. EnRXSpecInt(iobase, ON);
  449. /* The following is basically hwreset */
  450. /* If this is the case, why not just call hwreset() ? Jean II */
  451. ResetChip(iobase, 5);
  452. EnableDMA(iobase, OFF);
  453. EnableTX(iobase, OFF);
  454. EnableRX(iobase, OFF);
  455. EnRXDMA(iobase, OFF);
  456. EnTXDMA(iobase, OFF);
  457. RXStart(iobase, OFF);
  458. TXStart(iobase, OFF);
  459. InitCard(iobase);
  460. CommonInit(iobase);
  461. SIRFilter(iobase, ON);
  462. SetSIR(iobase, ON);
  463. CRC16(iobase, ON);
  464. EnTXCRC(iobase, 0);
  465. WriteReg(iobase, I_ST_CT_0, 0x00);
  466. SetBaudRate(iobase, 9600);
  467. SetPulseWidth(iobase, 12);
  468. SetSendPreambleCount(iobase, 0);
  469. self->io.speed = 9600;
  470. self->st_fifo.len = 0;
  471. via_ircc_change_dongle_speed(iobase, self->io.speed,
  472. self->io.dongle_id);
  473. WriteReg(iobase, I_ST_CT_0, 0x80);
  474. }
  475. /*
  476. * Function via_ircc_read_dongle_id (void)
  477. *
  478. */
  479. static int via_ircc_read_dongle_id(int iobase)
  480. {
  481. int dongle_id = 9; /* Default to IBM */
  482. IRDA_ERROR("via-ircc: dongle probing not supported, please specify dongle_id module parameter.\n");
  483. return dongle_id;
  484. }
  485. /*
  486. * Function via_ircc_change_dongle_speed (iobase, speed, dongle_id)
  487. * Change speed of the attach dongle
  488. * only implement two type of dongle currently.
  489. */
  490. static void via_ircc_change_dongle_speed(int iobase, int speed,
  491. int dongle_id)
  492. {
  493. u8 mode = 0;
  494. /* speed is unused, as we use IsSIROn()/IsMIROn() */
  495. speed = speed;
  496. IRDA_DEBUG(1, "%s(): change_dongle_speed to %d for 0x%x, %d\n",
  497. __FUNCTION__, speed, iobase, dongle_id);
  498. switch (dongle_id) {
  499. /* Note: The dongle_id's listed here are derived from
  500. * nsc-ircc.c */
  501. case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
  502. UseOneRX(iobase, ON); // use one RX pin RX1,RX2
  503. InvertTX(iobase, OFF);
  504. InvertRX(iobase, OFF);
  505. EnRX2(iobase, ON); //sir to rx2
  506. EnGPIOtoRX2(iobase, OFF);
  507. if (IsSIROn(iobase)) { //sir
  508. // Mode select Off
  509. SlowIRRXLowActive(iobase, ON);
  510. udelay(1000);
  511. SlowIRRXLowActive(iobase, OFF);
  512. } else {
  513. if (IsMIROn(iobase)) { //mir
  514. // Mode select On
  515. SlowIRRXLowActive(iobase, OFF);
  516. udelay(20);
  517. } else { // fir
  518. if (IsFIROn(iobase)) { //fir
  519. // Mode select On
  520. SlowIRRXLowActive(iobase, OFF);
  521. udelay(20);
  522. }
  523. }
  524. }
  525. break;
  526. case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
  527. UseOneRX(iobase, ON); //use ONE RX....RX1
  528. InvertTX(iobase, OFF);
  529. InvertRX(iobase, OFF); // invert RX pin
  530. EnRX2(iobase, ON);
  531. EnGPIOtoRX2(iobase, OFF);
  532. if (IsSIROn(iobase)) { //sir
  533. // Mode select On
  534. SlowIRRXLowActive(iobase, ON);
  535. udelay(20);
  536. // Mode select Off
  537. SlowIRRXLowActive(iobase, OFF);
  538. }
  539. if (IsMIROn(iobase)) { //mir
  540. // Mode select On
  541. SlowIRRXLowActive(iobase, OFF);
  542. udelay(20);
  543. // Mode select Off
  544. SlowIRRXLowActive(iobase, ON);
  545. } else { // fir
  546. if (IsFIROn(iobase)) { //fir
  547. // Mode select On
  548. SlowIRRXLowActive(iobase, OFF);
  549. // TX On
  550. WriteTX(iobase, ON);
  551. udelay(20);
  552. // Mode select OFF
  553. SlowIRRXLowActive(iobase, ON);
  554. udelay(20);
  555. // TX Off
  556. WriteTX(iobase, OFF);
  557. }
  558. }
  559. break;
  560. case 0x0d:
  561. UseOneRX(iobase, OFF); // use two RX pin RX1,RX2
  562. InvertTX(iobase, OFF);
  563. InvertRX(iobase, OFF);
  564. SlowIRRXLowActive(iobase, OFF);
  565. if (IsSIROn(iobase)) { //sir
  566. EnGPIOtoRX2(iobase, OFF);
  567. WriteGIO(iobase, OFF);
  568. EnRX2(iobase, OFF); //sir to rx2
  569. } else { // fir mir
  570. EnGPIOtoRX2(iobase, OFF);
  571. WriteGIO(iobase, OFF);
  572. EnRX2(iobase, OFF); //fir to rx
  573. }
  574. break;
  575. case 0x11: /* Temic TFDS4500 */
  576. IRDA_DEBUG(2, "%s: Temic TFDS4500: One RX pin, TX normal, RX inverted.\n", __FUNCTION__);
  577. UseOneRX(iobase, ON); //use ONE RX....RX1
  578. InvertTX(iobase, OFF);
  579. InvertRX(iobase, ON); // invert RX pin
  580. EnRX2(iobase, ON); //sir to rx2
  581. EnGPIOtoRX2(iobase, OFF);
  582. if( IsSIROn(iobase) ){ //sir
  583. // Mode select On
  584. SlowIRRXLowActive(iobase, ON);
  585. udelay(20);
  586. // Mode select Off
  587. SlowIRRXLowActive(iobase, OFF);
  588. } else{
  589. IRDA_DEBUG(0, "%s: Warning: TFDS4500 not running in SIR mode !\n", __FUNCTION__);
  590. }
  591. break;
  592. case 0x0ff: /* Vishay */
  593. if (IsSIROn(iobase))
  594. mode = 0;
  595. else if (IsMIROn(iobase))
  596. mode = 1;
  597. else if (IsFIROn(iobase))
  598. mode = 2;
  599. else if (IsVFIROn(iobase))
  600. mode = 5; //VFIR-16
  601. SI_SetMode(iobase, mode);
  602. break;
  603. default:
  604. IRDA_ERROR("%s: Error: dongle_id %d unsupported !\n",
  605. __FUNCTION__, dongle_id);
  606. }
  607. }
  608. /*
  609. * Function via_ircc_change_speed (self, baud)
  610. *
  611. * Change the speed of the device
  612. *
  613. */
  614. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 speed)
  615. {
  616. struct net_device *dev = self->netdev;
  617. u16 iobase;
  618. u8 value = 0, bTmp;
  619. iobase = self->io.fir_base;
  620. /* Update accounting for new speed */
  621. self->io.speed = speed;
  622. IRDA_DEBUG(1, "%s: change_speed to %d bps.\n", __FUNCTION__, speed);
  623. WriteReg(iobase, I_ST_CT_0, 0x0);
  624. /* Controller mode sellection */
  625. switch (speed) {
  626. case 2400:
  627. case 9600:
  628. case 19200:
  629. case 38400:
  630. case 57600:
  631. case 115200:
  632. value = (115200/speed)-1;
  633. SetSIR(iobase, ON);
  634. CRC16(iobase, ON);
  635. break;
  636. case 576000:
  637. /* FIXME: this can't be right, as it's the same as 115200,
  638. * and 576000 is MIR, not SIR. */
  639. value = 0;
  640. SetSIR(iobase, ON);
  641. CRC16(iobase, ON);
  642. break;
  643. case 1152000:
  644. value = 0;
  645. SetMIR(iobase, ON);
  646. /* FIXME: CRC ??? */
  647. break;
  648. case 4000000:
  649. value = 0;
  650. SetFIR(iobase, ON);
  651. SetPulseWidth(iobase, 0);
  652. SetSendPreambleCount(iobase, 14);
  653. CRC16(iobase, OFF);
  654. EnTXCRC(iobase, ON);
  655. break;
  656. case 16000000:
  657. value = 0;
  658. SetVFIR(iobase, ON);
  659. /* FIXME: CRC ??? */
  660. break;
  661. default:
  662. value = 0;
  663. break;
  664. }
  665. /* Set baudrate to 0x19[2..7] */
  666. bTmp = (ReadReg(iobase, I_CF_H_1) & 0x03);
  667. bTmp |= value << 2;
  668. WriteReg(iobase, I_CF_H_1, bTmp);
  669. /* Some dongles may need to be informed about speed changes. */
  670. via_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
  671. /* Set FIFO size to 64 */
  672. SetFIFO(iobase, 64);
  673. /* Enable IR */
  674. WriteReg(iobase, I_ST_CT_0, 0x80);
  675. // EnTXFIFOHalfLevelInt(iobase,ON);
  676. /* Enable some interrupts so we can receive frames */
  677. //EnAllInt(iobase,ON);
  678. if (IsSIROn(iobase)) {
  679. SIRFilter(iobase, ON);
  680. SIRRecvAny(iobase, ON);
  681. } else {
  682. SIRFilter(iobase, OFF);
  683. SIRRecvAny(iobase, OFF);
  684. }
  685. if (speed > 115200) {
  686. /* Install FIR xmit handler */
  687. dev->hard_start_xmit = via_ircc_hard_xmit_fir;
  688. via_ircc_dma_receive(self);
  689. } else {
  690. /* Install SIR xmit handler */
  691. dev->hard_start_xmit = via_ircc_hard_xmit_sir;
  692. }
  693. netif_wake_queue(dev);
  694. }
  695. /*
  696. * Function via_ircc_hard_xmit (skb, dev)
  697. *
  698. * Transmit the frame!
  699. *
  700. */
  701. static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  702. struct net_device *dev)
  703. {
  704. struct via_ircc_cb *self;
  705. unsigned long flags;
  706. u16 iobase;
  707. __u32 speed;
  708. self = (struct via_ircc_cb *) dev->priv;
  709. IRDA_ASSERT(self != NULL, return 0;);
  710. iobase = self->io.fir_base;
  711. netif_stop_queue(dev);
  712. /* Check if we need to change the speed */
  713. speed = irda_get_next_speed(skb);
  714. if ((speed != self->io.speed) && (speed != -1)) {
  715. /* Check for empty frame */
  716. if (!skb->len) {
  717. via_ircc_change_speed(self, speed);
  718. dev->trans_start = jiffies;
  719. dev_kfree_skb(skb);
  720. return 0;
  721. } else
  722. self->new_speed = speed;
  723. }
  724. InitCard(iobase);
  725. CommonInit(iobase);
  726. SIRFilter(iobase, ON);
  727. SetSIR(iobase, ON);
  728. CRC16(iobase, ON);
  729. EnTXCRC(iobase, 0);
  730. WriteReg(iobase, I_ST_CT_0, 0x00);
  731. spin_lock_irqsave(&self->lock, flags);
  732. self->tx_buff.data = self->tx_buff.head;
  733. self->tx_buff.len =
  734. async_wrap_skb(skb, self->tx_buff.data,
  735. self->tx_buff.truesize);
  736. self->stats.tx_bytes += self->tx_buff.len;
  737. /* Send this frame with old speed */
  738. SetBaudRate(iobase, self->io.speed);
  739. SetPulseWidth(iobase, 12);
  740. SetSendPreambleCount(iobase, 0);
  741. WriteReg(iobase, I_ST_CT_0, 0x80);
  742. EnableTX(iobase, ON);
  743. EnableRX(iobase, OFF);
  744. ResetChip(iobase, 0);
  745. ResetChip(iobase, 1);
  746. ResetChip(iobase, 2);
  747. ResetChip(iobase, 3);
  748. ResetChip(iobase, 4);
  749. EnAllInt(iobase, ON);
  750. EnTXDMA(iobase, ON);
  751. EnRXDMA(iobase, OFF);
  752. irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
  753. DMA_TX_MODE);
  754. SetSendByte(iobase, self->tx_buff.len);
  755. RXStart(iobase, OFF);
  756. TXStart(iobase, ON);
  757. dev->trans_start = jiffies;
  758. spin_unlock_irqrestore(&self->lock, flags);
  759. dev_kfree_skb(skb);
  760. return 0;
  761. }
  762. static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  763. struct net_device *dev)
  764. {
  765. struct via_ircc_cb *self;
  766. u16 iobase;
  767. __u32 speed;
  768. unsigned long flags;
  769. self = (struct via_ircc_cb *) dev->priv;
  770. iobase = self->io.fir_base;
  771. if (self->st_fifo.len)
  772. return 0;
  773. if (self->chip_id == 0x3076)
  774. iodelay(1500);
  775. else
  776. udelay(1500);
  777. netif_stop_queue(dev);
  778. speed = irda_get_next_speed(skb);
  779. if ((speed != self->io.speed) && (speed != -1)) {
  780. if (!skb->len) {
  781. via_ircc_change_speed(self, speed);
  782. dev->trans_start = jiffies;
  783. dev_kfree_skb(skb);
  784. return 0;
  785. } else
  786. self->new_speed = speed;
  787. }
  788. spin_lock_irqsave(&self->lock, flags);
  789. self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
  790. self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
  791. self->tx_fifo.tail += skb->len;
  792. self->stats.tx_bytes += skb->len;
  793. skb_copy_from_linear_data(skb,
  794. self->tx_fifo.queue[self->tx_fifo.free].start, skb->len);
  795. self->tx_fifo.len++;
  796. self->tx_fifo.free++;
  797. //F01 if (self->tx_fifo.len == 1) {
  798. via_ircc_dma_xmit(self, iobase);
  799. //F01 }
  800. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) netif_wake_queue(self->netdev);
  801. dev->trans_start = jiffies;
  802. dev_kfree_skb(skb);
  803. spin_unlock_irqrestore(&self->lock, flags);
  804. return 0;
  805. }
  806. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase)
  807. {
  808. EnTXDMA(iobase, OFF);
  809. self->io.direction = IO_XMIT;
  810. EnPhys(iobase, ON);
  811. EnableTX(iobase, ON);
  812. EnableRX(iobase, OFF);
  813. ResetChip(iobase, 0);
  814. ResetChip(iobase, 1);
  815. ResetChip(iobase, 2);
  816. ResetChip(iobase, 3);
  817. ResetChip(iobase, 4);
  818. EnAllInt(iobase, ON);
  819. EnTXDMA(iobase, ON);
  820. EnRXDMA(iobase, OFF);
  821. irda_setup_dma(self->io.dma,
  822. ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
  823. self->tx_buff.head) + self->tx_buff_dma,
  824. self->tx_fifo.queue[self->tx_fifo.ptr].len, DMA_TX_MODE);
  825. IRDA_DEBUG(1, "%s: tx_fifo.ptr=%x,len=%x,tx_fifo.len=%x..\n",
  826. __FUNCTION__, self->tx_fifo.ptr,
  827. self->tx_fifo.queue[self->tx_fifo.ptr].len,
  828. self->tx_fifo.len);
  829. SetSendByte(iobase, self->tx_fifo.queue[self->tx_fifo.ptr].len);
  830. RXStart(iobase, OFF);
  831. TXStart(iobase, ON);
  832. return 0;
  833. }
  834. /*
  835. * Function via_ircc_dma_xmit_complete (self)
  836. *
  837. * The transfer of a frame in finished. This function will only be called
  838. * by the interrupt handler
  839. *
  840. */
  841. static int via_ircc_dma_xmit_complete(struct via_ircc_cb *self)
  842. {
  843. int iobase;
  844. int ret = TRUE;
  845. u8 Tx_status;
  846. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  847. iobase = self->io.fir_base;
  848. /* Disable DMA */
  849. // DisableDmaChannel(self->io.dma);
  850. /* Check for underrrun! */
  851. /* Clear bit, by writing 1 into it */
  852. Tx_status = GetTXStatus(iobase);
  853. if (Tx_status & 0x08) {
  854. self->stats.tx_errors++;
  855. self->stats.tx_fifo_errors++;
  856. hwreset(self);
  857. // how to clear underrrun ?
  858. } else {
  859. self->stats.tx_packets++;
  860. ResetChip(iobase, 3);
  861. ResetChip(iobase, 4);
  862. }
  863. /* Check if we need to change the speed */
  864. if (self->new_speed) {
  865. via_ircc_change_speed(self, self->new_speed);
  866. self->new_speed = 0;
  867. }
  868. /* Finished with this frame, so prepare for next */
  869. if (IsFIROn(iobase)) {
  870. if (self->tx_fifo.len) {
  871. self->tx_fifo.len--;
  872. self->tx_fifo.ptr++;
  873. }
  874. }
  875. IRDA_DEBUG(1,
  876. "%s: tx_fifo.len=%x ,tx_fifo.ptr=%x,tx_fifo.free=%x...\n",
  877. __FUNCTION__,
  878. self->tx_fifo.len, self->tx_fifo.ptr, self->tx_fifo.free);
  879. /* F01_S
  880. // Any frames to be sent back-to-back?
  881. if (self->tx_fifo.len) {
  882. // Not finished yet!
  883. via_ircc_dma_xmit(self, iobase);
  884. ret = FALSE;
  885. } else {
  886. F01_E*/
  887. // Reset Tx FIFO info
  888. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  889. self->tx_fifo.tail = self->tx_buff.head;
  890. //F01 }
  891. // Make sure we have room for more frames
  892. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) {
  893. // Not busy transmitting anymore
  894. // Tell the network layer, that we can accept more frames
  895. netif_wake_queue(self->netdev);
  896. //F01 }
  897. return ret;
  898. }
  899. /*
  900. * Function via_ircc_dma_receive (self)
  901. *
  902. * Set configuration for receive a frame.
  903. *
  904. */
  905. static int via_ircc_dma_receive(struct via_ircc_cb *self)
  906. {
  907. int iobase;
  908. iobase = self->io.fir_base;
  909. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  910. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  911. self->tx_fifo.tail = self->tx_buff.head;
  912. self->RxDataReady = 0;
  913. self->io.direction = IO_RECV;
  914. self->rx_buff.data = self->rx_buff.head;
  915. self->st_fifo.len = self->st_fifo.pending_bytes = 0;
  916. self->st_fifo.tail = self->st_fifo.head = 0;
  917. EnPhys(iobase, ON);
  918. EnableTX(iobase, OFF);
  919. EnableRX(iobase, ON);
  920. ResetChip(iobase, 0);
  921. ResetChip(iobase, 1);
  922. ResetChip(iobase, 2);
  923. ResetChip(iobase, 3);
  924. ResetChip(iobase, 4);
  925. EnAllInt(iobase, ON);
  926. EnTXDMA(iobase, OFF);
  927. EnRXDMA(iobase, ON);
  928. irda_setup_dma(self->io.dma2, self->rx_buff_dma,
  929. self->rx_buff.truesize, DMA_RX_MODE);
  930. TXStart(iobase, OFF);
  931. RXStart(iobase, ON);
  932. return 0;
  933. }
  934. /*
  935. * Function via_ircc_dma_receive_complete (self)
  936. *
  937. * Controller Finished with receiving frames,
  938. * and this routine is call by ISR
  939. *
  940. */
  941. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  942. int iobase)
  943. {
  944. struct st_fifo *st_fifo;
  945. struct sk_buff *skb;
  946. int len, i;
  947. u8 status = 0;
  948. iobase = self->io.fir_base;
  949. st_fifo = &self->st_fifo;
  950. if (self->io.speed < 4000000) { //Speed below FIR
  951. len = GetRecvByte(iobase, self);
  952. skb = dev_alloc_skb(len + 1);
  953. if (skb == NULL)
  954. return FALSE;
  955. // Make sure IP header gets aligned
  956. skb_reserve(skb, 1);
  957. skb_put(skb, len - 2);
  958. if (self->chip_id == 0x3076) {
  959. for (i = 0; i < len - 2; i++)
  960. skb->data[i] = self->rx_buff.data[i * 2];
  961. } else {
  962. if (self->chip_id == 0x3096) {
  963. for (i = 0; i < len - 2; i++)
  964. skb->data[i] =
  965. self->rx_buff.data[i];
  966. }
  967. }
  968. // Move to next frame
  969. self->rx_buff.data += len;
  970. self->stats.rx_bytes += len;
  971. self->stats.rx_packets++;
  972. skb->dev = self->netdev;
  973. skb_reset_mac_header(skb);
  974. skb->protocol = htons(ETH_P_IRDA);
  975. netif_rx(skb);
  976. return TRUE;
  977. }
  978. else { //FIR mode
  979. len = GetRecvByte(iobase, self);
  980. if (len == 0)
  981. return TRUE; //interrupt only, data maybe move by RxT
  982. if (((len - 4) < 2) || ((len - 4) > 2048)) {
  983. IRDA_DEBUG(1, "%s(): Trouble:len=%x,CurCount=%x,LastCount=%x..\n",
  984. __FUNCTION__, len, RxCurCount(iobase, self),
  985. self->RxLastCount);
  986. hwreset(self);
  987. return FALSE;
  988. }
  989. IRDA_DEBUG(2, "%s(): fifo.len=%x,len=%x,CurCount=%x..\n",
  990. __FUNCTION__,
  991. st_fifo->len, len - 4, RxCurCount(iobase, self));
  992. st_fifo->entries[st_fifo->tail].status = status;
  993. st_fifo->entries[st_fifo->tail].len = len;
  994. st_fifo->pending_bytes += len;
  995. st_fifo->tail++;
  996. st_fifo->len++;
  997. if (st_fifo->tail > MAX_RX_WINDOW)
  998. st_fifo->tail = 0;
  999. self->RxDataReady = 0;
  1000. // It maybe have MAX_RX_WINDOW package receive by
  1001. // receive_complete before Timer IRQ
  1002. /* F01_S
  1003. if (st_fifo->len < (MAX_RX_WINDOW+2 )) {
  1004. RXStart(iobase,ON);
  1005. SetTimer(iobase,4);
  1006. }
  1007. else {
  1008. F01_E */
  1009. EnableRX(iobase, OFF);
  1010. EnRXDMA(iobase, OFF);
  1011. RXStart(iobase, OFF);
  1012. //F01_S
  1013. // Put this entry back in fifo
  1014. if (st_fifo->head > MAX_RX_WINDOW)
  1015. st_fifo->head = 0;
  1016. status = st_fifo->entries[st_fifo->head].status;
  1017. len = st_fifo->entries[st_fifo->head].len;
  1018. st_fifo->head++;
  1019. st_fifo->len--;
  1020. skb = dev_alloc_skb(len + 1 - 4);
  1021. /*
  1022. * if frame size,data ptr,or skb ptr are wrong ,the get next
  1023. * entry.
  1024. */
  1025. if ((skb == NULL) || (skb->data == NULL)
  1026. || (self->rx_buff.data == NULL) || (len < 6)) {
  1027. self->stats.rx_dropped++;
  1028. return TRUE;
  1029. }
  1030. skb_reserve(skb, 1);
  1031. skb_put(skb, len - 4);
  1032. skb_copy_to_linear_data(skb, self->rx_buff.data, len - 4);
  1033. IRDA_DEBUG(2, "%s(): len=%x.rx_buff=%p\n", __FUNCTION__,
  1034. len - 4, self->rx_buff.data);
  1035. // Move to next frame
  1036. self->rx_buff.data += len;
  1037. self->stats.rx_bytes += len;
  1038. self->stats.rx_packets++;
  1039. skb->dev = self->netdev;
  1040. skb_reset_mac_header(skb);
  1041. skb->protocol = htons(ETH_P_IRDA);
  1042. netif_rx(skb);
  1043. //F01_E
  1044. } //FIR
  1045. return TRUE;
  1046. }
  1047. /*
  1048. * if frame is received , but no INT ,then use this routine to upload frame.
  1049. */
  1050. static int upload_rxdata(struct via_ircc_cb *self, int iobase)
  1051. {
  1052. struct sk_buff *skb;
  1053. int len;
  1054. struct st_fifo *st_fifo;
  1055. st_fifo = &self->st_fifo;
  1056. len = GetRecvByte(iobase, self);
  1057. IRDA_DEBUG(2, "%s(): len=%x\n", __FUNCTION__, len);
  1058. if ((len - 4) < 2) {
  1059. self->stats.rx_dropped++;
  1060. return FALSE;
  1061. }
  1062. skb = dev_alloc_skb(len + 1);
  1063. if (skb == NULL) {
  1064. self->stats.rx_dropped++;
  1065. return FALSE;
  1066. }
  1067. skb_reserve(skb, 1);
  1068. skb_put(skb, len - 4 + 1);
  1069. skb_copy_to_linear_data(skb, self->rx_buff.data, len - 4 + 1);
  1070. st_fifo->tail++;
  1071. st_fifo->len++;
  1072. if (st_fifo->tail > MAX_RX_WINDOW)
  1073. st_fifo->tail = 0;
  1074. // Move to next frame
  1075. self->rx_buff.data += len;
  1076. self->stats.rx_bytes += len;
  1077. self->stats.rx_packets++;
  1078. skb->dev = self->netdev;
  1079. skb_reset_mac_header(skb);
  1080. skb->protocol = htons(ETH_P_IRDA);
  1081. netif_rx(skb);
  1082. if (st_fifo->len < (MAX_RX_WINDOW + 2)) {
  1083. RXStart(iobase, ON);
  1084. } else {
  1085. EnableRX(iobase, OFF);
  1086. EnRXDMA(iobase, OFF);
  1087. RXStart(iobase, OFF);
  1088. }
  1089. return TRUE;
  1090. }
  1091. /*
  1092. * Implement back to back receive , use this routine to upload data.
  1093. */
  1094. static int RxTimerHandler(struct via_ircc_cb *self, int iobase)
  1095. {
  1096. struct st_fifo *st_fifo;
  1097. struct sk_buff *skb;
  1098. int len;
  1099. u8 status;
  1100. st_fifo = &self->st_fifo;
  1101. if (CkRxRecv(iobase, self)) {
  1102. // if still receiving ,then return ,don't upload frame
  1103. self->RetryCount = 0;
  1104. SetTimer(iobase, 20);
  1105. self->RxDataReady++;
  1106. return FALSE;
  1107. } else
  1108. self->RetryCount++;
  1109. if ((self->RetryCount >= 1) ||
  1110. ((st_fifo->pending_bytes + 2048) > self->rx_buff.truesize)
  1111. || (st_fifo->len >= (MAX_RX_WINDOW))) {
  1112. while (st_fifo->len > 0) { //upload frame
  1113. // Put this entry back in fifo
  1114. if (st_fifo->head > MAX_RX_WINDOW)
  1115. st_fifo->head = 0;
  1116. status = st_fifo->entries[st_fifo->head].status;
  1117. len = st_fifo->entries[st_fifo->head].len;
  1118. st_fifo->head++;
  1119. st_fifo->len--;
  1120. skb = dev_alloc_skb(len + 1 - 4);
  1121. /*
  1122. * if frame size, data ptr, or skb ptr are wrong,
  1123. * then get next entry.
  1124. */
  1125. if ((skb == NULL) || (skb->data == NULL)
  1126. || (self->rx_buff.data == NULL) || (len < 6)) {
  1127. self->stats.rx_dropped++;
  1128. continue;
  1129. }
  1130. skb_reserve(skb, 1);
  1131. skb_put(skb, len - 4);
  1132. skb_copy_to_linear_data(skb, self->rx_buff.data, len - 4);
  1133. IRDA_DEBUG(2, "%s(): len=%x.head=%x\n", __FUNCTION__,
  1134. len - 4, st_fifo->head);
  1135. // Move to next frame
  1136. self->rx_buff.data += len;
  1137. self->stats.rx_bytes += len;
  1138. self->stats.rx_packets++;
  1139. skb->dev = self->netdev;
  1140. skb_reset_mac_header(skb);
  1141. skb->protocol = htons(ETH_P_IRDA);
  1142. netif_rx(skb);
  1143. } //while
  1144. self->RetryCount = 0;
  1145. IRDA_DEBUG(2,
  1146. "%s(): End of upload HostStatus=%x,RxStatus=%x\n",
  1147. __FUNCTION__,
  1148. GetHostStatus(iobase), GetRXStatus(iobase));
  1149. /*
  1150. * if frame is receive complete at this routine ,then upload
  1151. * frame.
  1152. */
  1153. if ((GetRXStatus(iobase) & 0x10)
  1154. && (RxCurCount(iobase, self) != self->RxLastCount)) {
  1155. upload_rxdata(self, iobase);
  1156. if (irda_device_txqueue_empty(self->netdev))
  1157. via_ircc_dma_receive(self);
  1158. }
  1159. } // timer detect complete
  1160. else
  1161. SetTimer(iobase, 4);
  1162. return TRUE;
  1163. }
  1164. /*
  1165. * Function via_ircc_interrupt (irq, dev_id)
  1166. *
  1167. * An interrupt from the chip has arrived. Time to do some work
  1168. *
  1169. */
  1170. static irqreturn_t via_ircc_interrupt(int irq, void *dev_id)
  1171. {
  1172. struct net_device *dev = (struct net_device *) dev_id;
  1173. struct via_ircc_cb *self;
  1174. int iobase;
  1175. u8 iHostIntType, iRxIntType, iTxIntType;
  1176. if (!dev) {
  1177. IRDA_WARNING("%s: irq %d for unknown device.\n", driver_name,
  1178. irq);
  1179. return IRQ_NONE;
  1180. }
  1181. self = (struct via_ircc_cb *) dev->priv;
  1182. iobase = self->io.fir_base;
  1183. spin_lock(&self->lock);
  1184. iHostIntType = GetHostStatus(iobase);
  1185. IRDA_DEBUG(4, "%s(): iHostIntType %02x: %s %s %s %02x\n",
  1186. __FUNCTION__, iHostIntType,
  1187. (iHostIntType & 0x40) ? "Timer" : "",
  1188. (iHostIntType & 0x20) ? "Tx" : "",
  1189. (iHostIntType & 0x10) ? "Rx" : "",
  1190. (iHostIntType & 0x0e) >> 1);
  1191. if ((iHostIntType & 0x40) != 0) { //Timer Event
  1192. self->EventFlag.TimeOut++;
  1193. ClearTimerInt(iobase, 1);
  1194. if (self->io.direction == IO_XMIT) {
  1195. via_ircc_dma_xmit(self, iobase);
  1196. }
  1197. if (self->io.direction == IO_RECV) {
  1198. /*
  1199. * frame ready hold too long, must reset.
  1200. */
  1201. if (self->RxDataReady > 30) {
  1202. hwreset(self);
  1203. if (irda_device_txqueue_empty(self->netdev)) {
  1204. via_ircc_dma_receive(self);
  1205. }
  1206. } else { // call this to upload frame.
  1207. RxTimerHandler(self, iobase);
  1208. }
  1209. } //RECV
  1210. } //Timer Event
  1211. if ((iHostIntType & 0x20) != 0) { //Tx Event
  1212. iTxIntType = GetTXStatus(iobase);
  1213. IRDA_DEBUG(4, "%s(): iTxIntType %02x: %s %s %s %s\n",
  1214. __FUNCTION__, iTxIntType,
  1215. (iTxIntType & 0x08) ? "FIFO underr." : "",
  1216. (iTxIntType & 0x04) ? "EOM" : "",
  1217. (iTxIntType & 0x02) ? "FIFO ready" : "",
  1218. (iTxIntType & 0x01) ? "Early EOM" : "");
  1219. if (iTxIntType & 0x4) {
  1220. self->EventFlag.EOMessage++; // read and will auto clean
  1221. if (via_ircc_dma_xmit_complete(self)) {
  1222. if (irda_device_txqueue_empty
  1223. (self->netdev)) {
  1224. via_ircc_dma_receive(self);
  1225. }
  1226. } else {
  1227. self->EventFlag.Unknown++;
  1228. }
  1229. } //EOP
  1230. } //Tx Event
  1231. //----------------------------------------
  1232. if ((iHostIntType & 0x10) != 0) { //Rx Event
  1233. /* Check if DMA has finished */
  1234. iRxIntType = GetRXStatus(iobase);
  1235. IRDA_DEBUG(4, "%s(): iRxIntType %02x: %s %s %s %s %s %s %s\n",
  1236. __FUNCTION__, iRxIntType,
  1237. (iRxIntType & 0x80) ? "PHY err." : "",
  1238. (iRxIntType & 0x40) ? "CRC err" : "",
  1239. (iRxIntType & 0x20) ? "FIFO overr." : "",
  1240. (iRxIntType & 0x10) ? "EOF" : "",
  1241. (iRxIntType & 0x08) ? "RxData" : "",
  1242. (iRxIntType & 0x02) ? "RxMaxLen" : "",
  1243. (iRxIntType & 0x01) ? "SIR bad" : "");
  1244. if (!iRxIntType)
  1245. IRDA_DEBUG(3, "%s(): RxIRQ =0\n", __FUNCTION__);
  1246. if (iRxIntType & 0x10) {
  1247. if (via_ircc_dma_receive_complete(self, iobase)) {
  1248. //F01 if(!(IsFIROn(iobase))) via_ircc_dma_receive(self);
  1249. via_ircc_dma_receive(self);
  1250. }
  1251. } // No ERR
  1252. else { //ERR
  1253. IRDA_DEBUG(4, "%s(): RxIRQ ERR:iRxIntType=%x,HostIntType=%x,CurCount=%x,RxLastCount=%x_____\n",
  1254. __FUNCTION__, iRxIntType, iHostIntType,
  1255. RxCurCount(iobase, self),
  1256. self->RxLastCount);
  1257. if (iRxIntType & 0x20) { //FIFO OverRun ERR
  1258. ResetChip(iobase, 0);
  1259. ResetChip(iobase, 1);
  1260. } else { //PHY,CRC ERR
  1261. if (iRxIntType != 0x08)
  1262. hwreset(self); //F01
  1263. }
  1264. via_ircc_dma_receive(self);
  1265. } //ERR
  1266. } //Rx Event
  1267. spin_unlock(&self->lock);
  1268. return IRQ_RETVAL(iHostIntType);
  1269. }
  1270. static void hwreset(struct via_ircc_cb *self)
  1271. {
  1272. int iobase;
  1273. iobase = self->io.fir_base;
  1274. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1275. ResetChip(iobase, 5);
  1276. EnableDMA(iobase, OFF);
  1277. EnableTX(iobase, OFF);
  1278. EnableRX(iobase, OFF);
  1279. EnRXDMA(iobase, OFF);
  1280. EnTXDMA(iobase, OFF);
  1281. RXStart(iobase, OFF);
  1282. TXStart(iobase, OFF);
  1283. InitCard(iobase);
  1284. CommonInit(iobase);
  1285. SIRFilter(iobase, ON);
  1286. SetSIR(iobase, ON);
  1287. CRC16(iobase, ON);
  1288. EnTXCRC(iobase, 0);
  1289. WriteReg(iobase, I_ST_CT_0, 0x00);
  1290. SetBaudRate(iobase, 9600);
  1291. SetPulseWidth(iobase, 12);
  1292. SetSendPreambleCount(iobase, 0);
  1293. WriteReg(iobase, I_ST_CT_0, 0x80);
  1294. /* Restore speed. */
  1295. via_ircc_change_speed(self, self->io.speed);
  1296. self->st_fifo.len = 0;
  1297. }
  1298. /*
  1299. * Function via_ircc_is_receiving (self)
  1300. *
  1301. * Return TRUE is we are currently receiving a frame
  1302. *
  1303. */
  1304. static int via_ircc_is_receiving(struct via_ircc_cb *self)
  1305. {
  1306. int status = FALSE;
  1307. int iobase;
  1308. IRDA_ASSERT(self != NULL, return FALSE;);
  1309. iobase = self->io.fir_base;
  1310. if (CkRxRecv(iobase, self))
  1311. status = TRUE;
  1312. IRDA_DEBUG(2, "%s(): status=%x....\n", __FUNCTION__, status);
  1313. return status;
  1314. }
  1315. /*
  1316. * Function via_ircc_net_open (dev)
  1317. *
  1318. * Start the device
  1319. *
  1320. */
  1321. static int via_ircc_net_open(struct net_device *dev)
  1322. {
  1323. struct via_ircc_cb *self;
  1324. int iobase;
  1325. char hwname[32];
  1326. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1327. IRDA_ASSERT(dev != NULL, return -1;);
  1328. self = (struct via_ircc_cb *) dev->priv;
  1329. self->stats.rx_packets = 0;
  1330. IRDA_ASSERT(self != NULL, return 0;);
  1331. iobase = self->io.fir_base;
  1332. if (request_irq(self->io.irq, via_ircc_interrupt, 0, dev->name, dev)) {
  1333. IRDA_WARNING("%s, unable to allocate irq=%d\n", driver_name,
  1334. self->io.irq);
  1335. return -EAGAIN;
  1336. }
  1337. /*
  1338. * Always allocate the DMA channel after the IRQ, and clean up on
  1339. * failure.
  1340. */
  1341. if (request_dma(self->io.dma, dev->name)) {
  1342. IRDA_WARNING("%s, unable to allocate dma=%d\n", driver_name,
  1343. self->io.dma);
  1344. free_irq(self->io.irq, self);
  1345. return -EAGAIN;
  1346. }
  1347. if (self->io.dma2 != self->io.dma) {
  1348. if (request_dma(self->io.dma2, dev->name)) {
  1349. IRDA_WARNING("%s, unable to allocate dma2=%d\n",
  1350. driver_name, self->io.dma2);
  1351. free_irq(self->io.irq, self);
  1352. return -EAGAIN;
  1353. }
  1354. }
  1355. /* turn on interrupts */
  1356. EnAllInt(iobase, ON);
  1357. EnInternalLoop(iobase, OFF);
  1358. EnExternalLoop(iobase, OFF);
  1359. /* */
  1360. via_ircc_dma_receive(self);
  1361. /* Ready to play! */
  1362. netif_start_queue(dev);
  1363. /*
  1364. * Open new IrLAP layer instance, now that everything should be
  1365. * initialized properly
  1366. */
  1367. sprintf(hwname, "VIA @ 0x%x", iobase);
  1368. self->irlap = irlap_open(dev, &self->qos, hwname);
  1369. self->RxLastCount = 0;
  1370. return 0;
  1371. }
  1372. /*
  1373. * Function via_ircc_net_close (dev)
  1374. *
  1375. * Stop the device
  1376. *
  1377. */
  1378. static int via_ircc_net_close(struct net_device *dev)
  1379. {
  1380. struct via_ircc_cb *self;
  1381. int iobase;
  1382. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1383. IRDA_ASSERT(dev != NULL, return -1;);
  1384. self = (struct via_ircc_cb *) dev->priv;
  1385. IRDA_ASSERT(self != NULL, return 0;);
  1386. /* Stop device */
  1387. netif_stop_queue(dev);
  1388. /* Stop and remove instance of IrLAP */
  1389. if (self->irlap)
  1390. irlap_close(self->irlap);
  1391. self->irlap = NULL;
  1392. iobase = self->io.fir_base;
  1393. EnTXDMA(iobase, OFF);
  1394. EnRXDMA(iobase, OFF);
  1395. DisableDmaChannel(self->io.dma);
  1396. /* Disable interrupts */
  1397. EnAllInt(iobase, OFF);
  1398. free_irq(self->io.irq, dev);
  1399. free_dma(self->io.dma);
  1400. return 0;
  1401. }
  1402. /*
  1403. * Function via_ircc_net_ioctl (dev, rq, cmd)
  1404. *
  1405. * Process IOCTL commands for this device
  1406. *
  1407. */
  1408. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  1409. int cmd)
  1410. {
  1411. struct if_irda_req *irq = (struct if_irda_req *) rq;
  1412. struct via_ircc_cb *self;
  1413. unsigned long flags;
  1414. int ret = 0;
  1415. IRDA_ASSERT(dev != NULL, return -1;);
  1416. self = dev->priv;
  1417. IRDA_ASSERT(self != NULL, return -1;);
  1418. IRDA_DEBUG(1, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name,
  1419. cmd);
  1420. /* Disable interrupts & save flags */
  1421. spin_lock_irqsave(&self->lock, flags);
  1422. switch (cmd) {
  1423. case SIOCSBANDWIDTH: /* Set bandwidth */
  1424. if (!capable(CAP_NET_ADMIN)) {
  1425. ret = -EPERM;
  1426. goto out;
  1427. }
  1428. via_ircc_change_speed(self, irq->ifr_baudrate);
  1429. break;
  1430. case SIOCSMEDIABUSY: /* Set media busy */
  1431. if (!capable(CAP_NET_ADMIN)) {
  1432. ret = -EPERM;
  1433. goto out;
  1434. }
  1435. irda_device_set_media_busy(self->netdev, TRUE);
  1436. break;
  1437. case SIOCGRECEIVING: /* Check if we are receiving right now */
  1438. irq->ifr_receiving = via_ircc_is_receiving(self);
  1439. break;
  1440. default:
  1441. ret = -EOPNOTSUPP;
  1442. }
  1443. out:
  1444. spin_unlock_irqrestore(&self->lock, flags);
  1445. return ret;
  1446. }
  1447. static struct net_device_stats *via_ircc_net_get_stats(struct net_device
  1448. *dev)
  1449. {
  1450. struct via_ircc_cb *self = (struct via_ircc_cb *) dev->priv;
  1451. return &self->stats;
  1452. }
  1453. MODULE_AUTHOR("VIA Technologies,inc");
  1454. MODULE_DESCRIPTION("VIA IrDA Device Driver");
  1455. MODULE_LICENSE("GPL");
  1456. module_init(via_ircc_init);
  1457. module_exit(via_ircc_cleanup);