debug.c 6.6 KB

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  1. /*
  2. * drivers/net/ibm_newemac/debug.c
  3. *
  4. * Driver for PowerPC 4xx on-chip ethernet controller, debug print routines.
  5. *
  6. * Copyright (c) 2004, 2005 Zultys Technologies
  7. * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. *
  14. */
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/sysrq.h>
  20. #include <asm/io.h>
  21. #include "core.h"
  22. static spinlock_t emac_dbg_lock = SPIN_LOCK_UNLOCKED;
  23. static void emac_desc_dump(struct emac_instance *p)
  24. {
  25. int i;
  26. printk("** EMAC %s TX BDs **\n"
  27. " tx_cnt = %d tx_slot = %d ack_slot = %d\n",
  28. p->ofdev->node->full_name,
  29. p->tx_cnt, p->tx_slot, p->ack_slot);
  30. for (i = 0; i < NUM_TX_BUFF / 2; ++i)
  31. printk
  32. ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
  33. i, p->tx_desc[i].data_ptr, p->tx_skb[i] ? 'V' : ' ',
  34. p->tx_desc[i].ctrl, p->tx_desc[i].data_len,
  35. NUM_TX_BUFF / 2 + i,
  36. p->tx_desc[NUM_TX_BUFF / 2 + i].data_ptr,
  37. p->tx_skb[NUM_TX_BUFF / 2 + i] ? 'V' : ' ',
  38. p->tx_desc[NUM_TX_BUFF / 2 + i].ctrl,
  39. p->tx_desc[NUM_TX_BUFF / 2 + i].data_len);
  40. printk("** EMAC %s RX BDs **\n"
  41. " rx_slot = %d flags = 0x%lx rx_skb_size = %d rx_sync_size = %d\n"
  42. " rx_sg_skb = 0x%p\n",
  43. p->ofdev->node->full_name,
  44. p->rx_slot, p->commac.flags, p->rx_skb_size,
  45. p->rx_sync_size, p->rx_sg_skb);
  46. for (i = 0; i < NUM_RX_BUFF / 2; ++i)
  47. printk
  48. ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
  49. i, p->rx_desc[i].data_ptr, p->rx_skb[i] ? 'V' : ' ',
  50. p->rx_desc[i].ctrl, p->rx_desc[i].data_len,
  51. NUM_RX_BUFF / 2 + i,
  52. p->rx_desc[NUM_RX_BUFF / 2 + i].data_ptr,
  53. p->rx_skb[NUM_RX_BUFF / 2 + i] ? 'V' : ' ',
  54. p->rx_desc[NUM_RX_BUFF / 2 + i].ctrl,
  55. p->rx_desc[NUM_RX_BUFF / 2 + i].data_len);
  56. }
  57. static void emac_mac_dump(struct emac_instance *dev)
  58. {
  59. struct emac_regs __iomem *p = dev->emacp;
  60. printk("** EMAC %s registers **\n"
  61. "MR0 = 0x%08x MR1 = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x\n"
  62. "RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x\n"
  63. "IAR = %04x%08x VTPID = 0x%04x VTCI = 0x%04x\n"
  64. "IAHT: 0x%04x 0x%04x 0x%04x 0x%04x "
  65. "GAHT: 0x%04x 0x%04x 0x%04x 0x%04x\n"
  66. "LSA = %04x%08x IPGVR = 0x%04x\n"
  67. "STACR = 0x%08x TRTR = 0x%08x RWMR = 0x%08x\n"
  68. "OCTX = 0x%08x OCRX = 0x%08x IPCR = 0x%08x\n",
  69. dev->ofdev->node->full_name, in_be32(&p->mr0), in_be32(&p->mr1),
  70. in_be32(&p->tmr0), in_be32(&p->tmr1),
  71. in_be32(&p->rmr), in_be32(&p->isr), in_be32(&p->iser),
  72. in_be32(&p->iahr), in_be32(&p->ialr), in_be32(&p->vtpid),
  73. in_be32(&p->vtci),
  74. in_be32(&p->iaht1), in_be32(&p->iaht2), in_be32(&p->iaht3),
  75. in_be32(&p->iaht4),
  76. in_be32(&p->gaht1), in_be32(&p->gaht2), in_be32(&p->gaht3),
  77. in_be32(&p->gaht4),
  78. in_be32(&p->lsah), in_be32(&p->lsal), in_be32(&p->ipgvr),
  79. in_be32(&p->stacr), in_be32(&p->trtr), in_be32(&p->rwmr),
  80. in_be32(&p->octx), in_be32(&p->ocrx), in_be32(&p->ipcr)
  81. );
  82. emac_desc_dump(dev);
  83. }
  84. static void emac_mal_dump(struct mal_instance *mal)
  85. {
  86. int i;
  87. printk("** MAL %s Registers **\n"
  88. "CFG = 0x%08x ESR = 0x%08x IER = 0x%08x\n"
  89. "TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n"
  90. "RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n",
  91. mal->ofdev->node->full_name,
  92. get_mal_dcrn(mal, MAL_CFG), get_mal_dcrn(mal, MAL_ESR),
  93. get_mal_dcrn(mal, MAL_IER),
  94. get_mal_dcrn(mal, MAL_TXCASR), get_mal_dcrn(mal, MAL_TXCARR),
  95. get_mal_dcrn(mal, MAL_TXEOBISR), get_mal_dcrn(mal, MAL_TXDEIR),
  96. get_mal_dcrn(mal, MAL_RXCASR), get_mal_dcrn(mal, MAL_RXCARR),
  97. get_mal_dcrn(mal, MAL_RXEOBISR), get_mal_dcrn(mal, MAL_RXDEIR)
  98. );
  99. printk("TX|");
  100. for (i = 0; i < mal->num_tx_chans; ++i) {
  101. if (i && !(i % 4))
  102. printk("\n ");
  103. printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_TXCTPR(i)));
  104. }
  105. printk("\nRX|");
  106. for (i = 0; i < mal->num_rx_chans; ++i) {
  107. if (i && !(i % 4))
  108. printk("\n ");
  109. printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_RXCTPR(i)));
  110. }
  111. printk("\n ");
  112. for (i = 0; i < mal->num_rx_chans; ++i) {
  113. u32 r = get_mal_dcrn(mal, MAL_RCBS(i));
  114. if (i && !(i % 3))
  115. printk("\n ");
  116. printk("RCBS%d = 0x%08x (%d) ", i, r, r * 16);
  117. }
  118. printk("\n");
  119. }
  120. static struct emac_instance *__emacs[4];
  121. static struct mal_instance *__mals[1];
  122. void emac_dbg_register(struct emac_instance *dev)
  123. {
  124. unsigned long flags;
  125. int i;
  126. spin_lock_irqsave(&emac_dbg_lock, flags);
  127. for (i = 0; i < ARRAY_SIZE(__emacs); i++)
  128. if (__emacs[i] == NULL) {
  129. __emacs[i] = dev;
  130. break;
  131. }
  132. spin_unlock_irqrestore(&emac_dbg_lock, flags);
  133. }
  134. void emac_dbg_unregister(struct emac_instance *dev)
  135. {
  136. unsigned long flags;
  137. int i;
  138. spin_lock_irqsave(&emac_dbg_lock, flags);
  139. for (i = 0; i < ARRAY_SIZE(__emacs); i++)
  140. if (__emacs[i] == dev) {
  141. __emacs[i] = NULL;
  142. break;
  143. }
  144. spin_unlock_irqrestore(&emac_dbg_lock, flags);
  145. }
  146. void mal_dbg_register(struct mal_instance *mal)
  147. {
  148. unsigned long flags;
  149. int i;
  150. spin_lock_irqsave(&emac_dbg_lock, flags);
  151. for (i = 0; i < ARRAY_SIZE(__mals); i++)
  152. if (__mals[i] == NULL) {
  153. __mals[i] = mal;
  154. break;
  155. }
  156. spin_unlock_irqrestore(&emac_dbg_lock, flags);
  157. }
  158. void mal_dbg_unregister(struct mal_instance *mal)
  159. {
  160. unsigned long flags;
  161. int i;
  162. spin_lock_irqsave(&emac_dbg_lock, flags);
  163. for (i = 0; i < ARRAY_SIZE(__mals); i++)
  164. if (__mals[i] == mal) {
  165. __mals[i] = NULL;
  166. break;
  167. }
  168. spin_unlock_irqrestore(&emac_dbg_lock, flags);
  169. }
  170. void emac_dbg_dump_all(void)
  171. {
  172. unsigned int i;
  173. unsigned long flags;
  174. spin_lock_irqsave(&emac_dbg_lock, flags);
  175. for (i = 0; i < ARRAY_SIZE(__mals); ++i)
  176. if (__mals[i])
  177. emac_mal_dump(__mals[i]);
  178. for (i = 0; i < ARRAY_SIZE(__emacs); ++i)
  179. if (__emacs[i])
  180. emac_mac_dump(__emacs[i]);
  181. spin_unlock_irqrestore(&emac_dbg_lock, flags);
  182. }
  183. #if defined(CONFIG_MAGIC_SYSRQ)
  184. static void emac_sysrq_handler(int key, struct tty_struct *tty)
  185. {
  186. emac_dbg_dump_all();
  187. }
  188. static struct sysrq_key_op emac_sysrq_op = {
  189. .handler = emac_sysrq_handler,
  190. .help_msg = "emaC",
  191. .action_msg = "Show EMAC(s) status",
  192. };
  193. int __init emac_init_debug(void)
  194. {
  195. return register_sysrq_key('c', &emac_sysrq_op);
  196. }
  197. void __exit emac_fini_debug(void)
  198. {
  199. unregister_sysrq_key('c', &emac_sysrq_op);
  200. }
  201. #else
  202. int __init emac_init_debug(void)
  203. {
  204. return 0;
  205. }
  206. void __exit emac_fini_debug(void)
  207. {
  208. }
  209. #endif /* CONFIG_MAGIC_SYSRQ */