ucb1400_ts.c 15 KB

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  1. /*
  2. * Philips UCB1400 touchscreen driver
  3. *
  4. * Author: Nicolas Pitre
  5. * Created: September 25, 2006
  6. * Copyright: MontaVista Software, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This code is heavily based on ucb1x00-*.c copyrighted by Russell King
  13. * covering the UCB1100, UCB1200 and UCB1300.. Support for the UCB1400 has
  14. * been made separate from ucb1x00-core/ucb1x00-ts on Russell's request.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/init.h>
  19. #include <linux/completion.h>
  20. #include <linux/delay.h>
  21. #include <linux/input.h>
  22. #include <linux/device.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/suspend.h>
  25. #include <linux/slab.h>
  26. #include <linux/kthread.h>
  27. #include <linux/freezer.h>
  28. #include <sound/driver.h>
  29. #include <sound/core.h>
  30. #include <sound/ac97_codec.h>
  31. /*
  32. * Interesting UCB1400 AC-link registers
  33. */
  34. #define UCB_IE_RIS 0x5e
  35. #define UCB_IE_FAL 0x60
  36. #define UCB_IE_STATUS 0x62
  37. #define UCB_IE_CLEAR 0x62
  38. #define UCB_IE_ADC (1 << 11)
  39. #define UCB_IE_TSPX (1 << 12)
  40. #define UCB_TS_CR 0x64
  41. #define UCB_TS_CR_TSMX_POW (1 << 0)
  42. #define UCB_TS_CR_TSPX_POW (1 << 1)
  43. #define UCB_TS_CR_TSMY_POW (1 << 2)
  44. #define UCB_TS_CR_TSPY_POW (1 << 3)
  45. #define UCB_TS_CR_TSMX_GND (1 << 4)
  46. #define UCB_TS_CR_TSPX_GND (1 << 5)
  47. #define UCB_TS_CR_TSMY_GND (1 << 6)
  48. #define UCB_TS_CR_TSPY_GND (1 << 7)
  49. #define UCB_TS_CR_MODE_INT (0 << 8)
  50. #define UCB_TS_CR_MODE_PRES (1 << 8)
  51. #define UCB_TS_CR_MODE_POS (2 << 8)
  52. #define UCB_TS_CR_BIAS_ENA (1 << 11)
  53. #define UCB_TS_CR_TSPX_LOW (1 << 12)
  54. #define UCB_TS_CR_TSMX_LOW (1 << 13)
  55. #define UCB_ADC_CR 0x66
  56. #define UCB_ADC_SYNC_ENA (1 << 0)
  57. #define UCB_ADC_VREFBYP_CON (1 << 1)
  58. #define UCB_ADC_INP_TSPX (0 << 2)
  59. #define UCB_ADC_INP_TSMX (1 << 2)
  60. #define UCB_ADC_INP_TSPY (2 << 2)
  61. #define UCB_ADC_INP_TSMY (3 << 2)
  62. #define UCB_ADC_INP_AD0 (4 << 2)
  63. #define UCB_ADC_INP_AD1 (5 << 2)
  64. #define UCB_ADC_INP_AD2 (6 << 2)
  65. #define UCB_ADC_INP_AD3 (7 << 2)
  66. #define UCB_ADC_EXT_REF (1 << 5)
  67. #define UCB_ADC_START (1 << 7)
  68. #define UCB_ADC_ENA (1 << 15)
  69. #define UCB_ADC_DATA 0x68
  70. #define UCB_ADC_DAT_VALID (1 << 15)
  71. #define UCB_ADC_DAT_VALUE(x) ((x) & 0x3ff)
  72. #define UCB_ID 0x7e
  73. #define UCB_ID_1400 0x4304
  74. struct ucb1400 {
  75. struct snd_ac97 *ac97;
  76. struct input_dev *ts_idev;
  77. int irq;
  78. wait_queue_head_t ts_wait;
  79. struct task_struct *ts_task;
  80. unsigned int irq_pending; /* not bit field shared */
  81. unsigned int ts_restart:1;
  82. unsigned int adcsync:1;
  83. };
  84. static int adcsync;
  85. static int ts_delay = 55; /* us */
  86. static int ts_delay_pressure; /* us */
  87. static inline u16 ucb1400_reg_read(struct ucb1400 *ucb, u16 reg)
  88. {
  89. return ucb->ac97->bus->ops->read(ucb->ac97, reg);
  90. }
  91. static inline void ucb1400_reg_write(struct ucb1400 *ucb, u16 reg, u16 val)
  92. {
  93. ucb->ac97->bus->ops->write(ucb->ac97, reg, val);
  94. }
  95. static inline void ucb1400_adc_enable(struct ucb1400 *ucb)
  96. {
  97. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  98. }
  99. static unsigned int ucb1400_adc_read(struct ucb1400 *ucb, u16 adc_channel)
  100. {
  101. unsigned int val;
  102. if (ucb->adcsync)
  103. adc_channel |= UCB_ADC_SYNC_ENA;
  104. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel);
  105. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel | UCB_ADC_START);
  106. for (;;) {
  107. val = ucb1400_reg_read(ucb, UCB_ADC_DATA);
  108. if (val & UCB_ADC_DAT_VALID)
  109. break;
  110. /* yield to other processes */
  111. schedule_timeout_uninterruptible(1);
  112. }
  113. return UCB_ADC_DAT_VALUE(val);
  114. }
  115. static inline void ucb1400_adc_disable(struct ucb1400 *ucb)
  116. {
  117. ucb1400_reg_write(ucb, UCB_ADC_CR, 0);
  118. }
  119. /* Switch to interrupt mode. */
  120. static inline void ucb1400_ts_mode_int(struct ucb1400 *ucb)
  121. {
  122. ucb1400_reg_write(ucb, UCB_TS_CR,
  123. UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
  124. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
  125. UCB_TS_CR_MODE_INT);
  126. }
  127. /*
  128. * Switch to pressure mode, and read pressure. We don't need to wait
  129. * here, since both plates are being driven.
  130. */
  131. static inline unsigned int ucb1400_ts_read_pressure(struct ucb1400 *ucb)
  132. {
  133. ucb1400_reg_write(ucb, UCB_TS_CR,
  134. UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
  135. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
  136. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  137. udelay(ts_delay_pressure);
  138. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY);
  139. }
  140. /*
  141. * Switch to X position mode and measure Y plate. We switch the plate
  142. * configuration in pressure mode, then switch to position mode. This
  143. * gives a faster response time. Even so, we need to wait about 55us
  144. * for things to stabilise.
  145. */
  146. static inline unsigned int ucb1400_ts_read_xpos(struct ucb1400 *ucb)
  147. {
  148. ucb1400_reg_write(ucb, UCB_TS_CR,
  149. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  150. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  151. ucb1400_reg_write(ucb, UCB_TS_CR,
  152. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  153. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  154. ucb1400_reg_write(ucb, UCB_TS_CR,
  155. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  156. UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
  157. udelay(ts_delay);
  158. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY);
  159. }
  160. /*
  161. * Switch to Y position mode and measure X plate. We switch the plate
  162. * configuration in pressure mode, then switch to position mode. This
  163. * gives a faster response time. Even so, we need to wait about 55us
  164. * for things to stabilise.
  165. */
  166. static inline unsigned int ucb1400_ts_read_ypos(struct ucb1400 *ucb)
  167. {
  168. ucb1400_reg_write(ucb, UCB_TS_CR,
  169. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  170. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  171. ucb1400_reg_write(ucb, UCB_TS_CR,
  172. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  173. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  174. ucb1400_reg_write(ucb, UCB_TS_CR,
  175. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  176. UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
  177. udelay(ts_delay);
  178. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPX);
  179. }
  180. /*
  181. * Switch to X plate resistance mode. Set MX to ground, PX to
  182. * supply. Measure current.
  183. */
  184. static inline unsigned int ucb1400_ts_read_xres(struct ucb1400 *ucb)
  185. {
  186. ucb1400_reg_write(ucb, UCB_TS_CR,
  187. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  188. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  189. return ucb1400_adc_read(ucb, 0);
  190. }
  191. /*
  192. * Switch to Y plate resistance mode. Set MY to ground, PY to
  193. * supply. Measure current.
  194. */
  195. static inline unsigned int ucb1400_ts_read_yres(struct ucb1400 *ucb)
  196. {
  197. ucb1400_reg_write(ucb, UCB_TS_CR,
  198. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  199. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  200. return ucb1400_adc_read(ucb, 0);
  201. }
  202. static inline int ucb1400_ts_pen_down(struct ucb1400 *ucb)
  203. {
  204. unsigned short val = ucb1400_reg_read(ucb, UCB_TS_CR);
  205. return (val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW));
  206. }
  207. static inline void ucb1400_ts_irq_enable(struct ucb1400 *ucb)
  208. {
  209. ucb1400_reg_write(ucb, UCB_IE_CLEAR, UCB_IE_TSPX);
  210. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  211. ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_TSPX);
  212. }
  213. static inline void ucb1400_ts_irq_disable(struct ucb1400 *ucb)
  214. {
  215. ucb1400_reg_write(ucb, UCB_IE_FAL, 0);
  216. }
  217. static void ucb1400_ts_evt_add(struct input_dev *idev, u16 pressure, u16 x, u16 y)
  218. {
  219. input_report_abs(idev, ABS_X, x);
  220. input_report_abs(idev, ABS_Y, y);
  221. input_report_abs(idev, ABS_PRESSURE, pressure);
  222. input_sync(idev);
  223. }
  224. static void ucb1400_ts_event_release(struct input_dev *idev)
  225. {
  226. input_report_abs(idev, ABS_PRESSURE, 0);
  227. input_sync(idev);
  228. }
  229. static void ucb1400_handle_pending_irq(struct ucb1400 *ucb)
  230. {
  231. unsigned int isr;
  232. isr = ucb1400_reg_read(ucb, UCB_IE_STATUS);
  233. ucb1400_reg_write(ucb, UCB_IE_CLEAR, isr);
  234. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  235. if (isr & UCB_IE_TSPX)
  236. ucb1400_ts_irq_disable(ucb);
  237. else
  238. printk(KERN_ERR "ucb1400: unexpected IE_STATUS = %#x\n", isr);
  239. enable_irq(ucb->irq);
  240. }
  241. static int ucb1400_ts_thread(void *_ucb)
  242. {
  243. struct ucb1400 *ucb = _ucb;
  244. struct task_struct *tsk = current;
  245. int valid = 0;
  246. struct sched_param param = { .sched_priority = 1 };
  247. sched_setscheduler(tsk, SCHED_FIFO, &param);
  248. set_freezable();
  249. while (!kthread_should_stop()) {
  250. unsigned int x, y, p;
  251. long timeout;
  252. ucb->ts_restart = 0;
  253. if (ucb->irq_pending) {
  254. ucb->irq_pending = 0;
  255. ucb1400_handle_pending_irq(ucb);
  256. }
  257. ucb1400_adc_enable(ucb);
  258. x = ucb1400_ts_read_xpos(ucb);
  259. y = ucb1400_ts_read_ypos(ucb);
  260. p = ucb1400_ts_read_pressure(ucb);
  261. ucb1400_adc_disable(ucb);
  262. /* Switch back to interrupt mode. */
  263. ucb1400_ts_mode_int(ucb);
  264. msleep(10);
  265. if (ucb1400_ts_pen_down(ucb)) {
  266. ucb1400_ts_irq_enable(ucb);
  267. /*
  268. * If we spat out a valid sample set last time,
  269. * spit out a "pen off" sample here.
  270. */
  271. if (valid) {
  272. ucb1400_ts_event_release(ucb->ts_idev);
  273. valid = 0;
  274. }
  275. timeout = MAX_SCHEDULE_TIMEOUT;
  276. } else {
  277. valid = 1;
  278. ucb1400_ts_evt_add(ucb->ts_idev, p, x, y);
  279. timeout = msecs_to_jiffies(10);
  280. }
  281. wait_event_freezable_timeout(ucb->ts_wait,
  282. ucb->irq_pending || ucb->ts_restart || kthread_should_stop(),
  283. timeout);
  284. }
  285. /* Send the "pen off" if we are stopping with the pen still active */
  286. if (valid)
  287. ucb1400_ts_event_release(ucb->ts_idev);
  288. ucb->ts_task = NULL;
  289. return 0;
  290. }
  291. /*
  292. * A restriction with interrupts exists when using the ucb1400, as
  293. * the codec read/write routines may sleep while waiting for codec
  294. * access completion and uses semaphores for access control to the
  295. * AC97 bus. A complete codec read cycle could take anywhere from
  296. * 60 to 100uSec so we *definitely* don't want to spin inside the
  297. * interrupt handler waiting for codec access. So, we handle the
  298. * interrupt by scheduling a RT kernel thread to run in process
  299. * context instead of interrupt context.
  300. */
  301. static irqreturn_t ucb1400_hard_irq(int irqnr, void *devid)
  302. {
  303. struct ucb1400 *ucb = devid;
  304. if (irqnr == ucb->irq) {
  305. disable_irq(ucb->irq);
  306. ucb->irq_pending = 1;
  307. wake_up(&ucb->ts_wait);
  308. return IRQ_HANDLED;
  309. }
  310. return IRQ_NONE;
  311. }
  312. static int ucb1400_ts_open(struct input_dev *idev)
  313. {
  314. struct ucb1400 *ucb = input_get_drvdata(idev);
  315. int ret = 0;
  316. BUG_ON(ucb->ts_task);
  317. ucb->ts_task = kthread_run(ucb1400_ts_thread, ucb, "UCB1400_ts");
  318. if (IS_ERR(ucb->ts_task)) {
  319. ret = PTR_ERR(ucb->ts_task);
  320. ucb->ts_task = NULL;
  321. }
  322. return ret;
  323. }
  324. static void ucb1400_ts_close(struct input_dev *idev)
  325. {
  326. struct ucb1400 *ucb = input_get_drvdata(idev);
  327. if (ucb->ts_task)
  328. kthread_stop(ucb->ts_task);
  329. ucb1400_ts_irq_disable(ucb);
  330. ucb1400_reg_write(ucb, UCB_TS_CR, 0);
  331. }
  332. #ifdef CONFIG_PM
  333. static int ucb1400_ts_resume(struct device *dev)
  334. {
  335. struct ucb1400 *ucb = dev_get_drvdata(dev);
  336. if (ucb->ts_task) {
  337. /*
  338. * Restart the TS thread to ensure the
  339. * TS interrupt mode is set up again
  340. * after sleep.
  341. */
  342. ucb->ts_restart = 1;
  343. wake_up(&ucb->ts_wait);
  344. }
  345. return 0;
  346. }
  347. #else
  348. #define ucb1400_ts_resume NULL
  349. #endif
  350. #ifndef NO_IRQ
  351. #define NO_IRQ 0
  352. #endif
  353. /*
  354. * Try to probe our interrupt, rather than relying on lots of
  355. * hard-coded machine dependencies.
  356. */
  357. static int ucb1400_detect_irq(struct ucb1400 *ucb)
  358. {
  359. unsigned long mask, timeout;
  360. mask = probe_irq_on();
  361. if (!mask) {
  362. probe_irq_off(mask);
  363. return -EBUSY;
  364. }
  365. /* Enable the ADC interrupt. */
  366. ucb1400_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
  367. ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
  368. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  369. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  370. /* Cause an ADC interrupt. */
  371. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  372. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
  373. /* Wait for the conversion to complete. */
  374. timeout = jiffies + HZ/2;
  375. while (!(ucb1400_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VALID)) {
  376. cpu_relax();
  377. if (time_after(jiffies, timeout)) {
  378. printk(KERN_ERR "ucb1400: timed out in IRQ probe\n");
  379. probe_irq_off(mask);
  380. return -ENODEV;
  381. }
  382. }
  383. ucb1400_reg_write(ucb, UCB_ADC_CR, 0);
  384. /* Disable and clear interrupt. */
  385. ucb1400_reg_write(ucb, UCB_IE_RIS, 0);
  386. ucb1400_reg_write(ucb, UCB_IE_FAL, 0);
  387. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  388. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  389. /* Read triggered interrupt. */
  390. ucb->irq = probe_irq_off(mask);
  391. if (ucb->irq < 0 || ucb->irq == NO_IRQ)
  392. return -ENODEV;
  393. return 0;
  394. }
  395. static int ucb1400_ts_probe(struct device *dev)
  396. {
  397. struct ucb1400 *ucb;
  398. struct input_dev *idev;
  399. int error, id, x_res, y_res;
  400. ucb = kzalloc(sizeof(struct ucb1400), GFP_KERNEL);
  401. idev = input_allocate_device();
  402. if (!ucb || !idev) {
  403. error = -ENOMEM;
  404. goto err_free_devs;
  405. }
  406. ucb->ts_idev = idev;
  407. ucb->adcsync = adcsync;
  408. ucb->ac97 = to_ac97_t(dev);
  409. init_waitqueue_head(&ucb->ts_wait);
  410. id = ucb1400_reg_read(ucb, UCB_ID);
  411. if (id != UCB_ID_1400) {
  412. error = -ENODEV;
  413. goto err_free_devs;
  414. }
  415. error = ucb1400_detect_irq(ucb);
  416. if (error) {
  417. printk(KERN_ERR "UCB1400: IRQ probe failed\n");
  418. goto err_free_devs;
  419. }
  420. error = request_irq(ucb->irq, ucb1400_hard_irq, IRQF_TRIGGER_RISING,
  421. "UCB1400", ucb);
  422. if (error) {
  423. printk(KERN_ERR "ucb1400: unable to grab irq%d: %d\n",
  424. ucb->irq, error);
  425. goto err_free_devs;
  426. }
  427. printk(KERN_DEBUG "UCB1400: found IRQ %d\n", ucb->irq);
  428. input_set_drvdata(idev, ucb);
  429. idev->dev.parent = dev;
  430. idev->name = "UCB1400 touchscreen interface";
  431. idev->id.vendor = ucb1400_reg_read(ucb, AC97_VENDOR_ID1);
  432. idev->id.product = id;
  433. idev->open = ucb1400_ts_open;
  434. idev->close = ucb1400_ts_close;
  435. idev->evbit[0] = BIT_MASK(EV_ABS);
  436. ucb1400_adc_enable(ucb);
  437. x_res = ucb1400_ts_read_xres(ucb);
  438. y_res = ucb1400_ts_read_yres(ucb);
  439. ucb1400_adc_disable(ucb);
  440. printk(KERN_DEBUG "UCB1400: x/y = %d/%d\n", x_res, y_res);
  441. input_set_abs_params(idev, ABS_X, 0, x_res, 0, 0);
  442. input_set_abs_params(idev, ABS_Y, 0, y_res, 0, 0);
  443. input_set_abs_params(idev, ABS_PRESSURE, 0, 0, 0, 0);
  444. error = input_register_device(idev);
  445. if (error)
  446. goto err_free_irq;
  447. dev_set_drvdata(dev, ucb);
  448. return 0;
  449. err_free_irq:
  450. free_irq(ucb->irq, ucb);
  451. err_free_devs:
  452. input_free_device(idev);
  453. kfree(ucb);
  454. return error;
  455. }
  456. static int ucb1400_ts_remove(struct device *dev)
  457. {
  458. struct ucb1400 *ucb = dev_get_drvdata(dev);
  459. free_irq(ucb->irq, ucb);
  460. input_unregister_device(ucb->ts_idev);
  461. dev_set_drvdata(dev, NULL);
  462. kfree(ucb);
  463. return 0;
  464. }
  465. static struct device_driver ucb1400_ts_driver = {
  466. .name = "ucb1400_ts",
  467. .owner = THIS_MODULE,
  468. .bus = &ac97_bus_type,
  469. .probe = ucb1400_ts_probe,
  470. .remove = ucb1400_ts_remove,
  471. .resume = ucb1400_ts_resume,
  472. };
  473. static int __init ucb1400_ts_init(void)
  474. {
  475. return driver_register(&ucb1400_ts_driver);
  476. }
  477. static void __exit ucb1400_ts_exit(void)
  478. {
  479. driver_unregister(&ucb1400_ts_driver);
  480. }
  481. module_param(adcsync, bool, 0444);
  482. MODULE_PARM_DESC(adcsync, "Synchronize touch readings with ADCSYNC pin.");
  483. module_param(ts_delay, int, 0444);
  484. MODULE_PARM_DESC(ts_delay, "Delay between panel setup and position read. Default = 55us.");
  485. module_param(ts_delay_pressure, int, 0444);
  486. MODULE_PARM_DESC(ts_delay_pressure,
  487. "delay between panel setup and pressure read. Default = 0us.");
  488. module_init(ucb1400_ts_init);
  489. module_exit(ucb1400_ts_exit);
  490. MODULE_DESCRIPTION("Philips UCB1400 touchscreen driver");
  491. MODULE_LICENSE("GPL");