i2c-mpc.c 9.4 KB

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  1. /*
  2. * (C) Copyright 2003-2004
  3. * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
  4. * This is a combined i2c adapter and algorithm driver for the
  5. * MPC107/Tsi107 PowerPC northbridge and processors that include
  6. * the same I2C unit (8240, 8245, 85xx).
  7. *
  8. * Release 0.8
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without any
  12. * warranty of any kind, whether express or implied.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/sched.h>
  17. #include <linux/init.h>
  18. #include <linux/platform_device.h>
  19. #include <asm/io.h>
  20. #include <linux/fsl_devices.h>
  21. #include <linux/i2c.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/delay.h>
  24. #define MPC_I2C_ADDR 0x00
  25. #define MPC_I2C_FDR 0x04
  26. #define MPC_I2C_CR 0x08
  27. #define MPC_I2C_SR 0x0c
  28. #define MPC_I2C_DR 0x10
  29. #define MPC_I2C_DFSRR 0x14
  30. #define MPC_I2C_REGION 0x20
  31. #define CCR_MEN 0x80
  32. #define CCR_MIEN 0x40
  33. #define CCR_MSTA 0x20
  34. #define CCR_MTX 0x10
  35. #define CCR_TXAK 0x08
  36. #define CCR_RSTA 0x04
  37. #define CSR_MCF 0x80
  38. #define CSR_MAAS 0x40
  39. #define CSR_MBB 0x20
  40. #define CSR_MAL 0x10
  41. #define CSR_SRW 0x04
  42. #define CSR_MIF 0x02
  43. #define CSR_RXAK 0x01
  44. struct mpc_i2c {
  45. void __iomem *base;
  46. u32 interrupt;
  47. wait_queue_head_t queue;
  48. struct i2c_adapter adap;
  49. int irq;
  50. u32 flags;
  51. };
  52. static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
  53. {
  54. writeb(x, i2c->base + MPC_I2C_CR);
  55. }
  56. static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
  57. {
  58. struct mpc_i2c *i2c = dev_id;
  59. if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
  60. /* Read again to allow register to stabilise */
  61. i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
  62. writeb(0, i2c->base + MPC_I2C_SR);
  63. wake_up_interruptible(&i2c->queue);
  64. }
  65. return IRQ_HANDLED;
  66. }
  67. /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
  68. * the bus, because it wants to send ACK.
  69. * Following sequence of enabling/disabling and sending start/stop generates
  70. * the pulse, so it's all OK.
  71. */
  72. static void mpc_i2c_fixup(struct mpc_i2c *i2c)
  73. {
  74. writeccr(i2c, 0);
  75. udelay(30);
  76. writeccr(i2c, CCR_MEN);
  77. udelay(30);
  78. writeccr(i2c, CCR_MSTA | CCR_MTX);
  79. udelay(30);
  80. writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
  81. udelay(30);
  82. writeccr(i2c, CCR_MEN);
  83. udelay(30);
  84. }
  85. static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
  86. {
  87. unsigned long orig_jiffies = jiffies;
  88. u32 x;
  89. int result = 0;
  90. if (i2c->irq == 0)
  91. {
  92. while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
  93. schedule();
  94. if (time_after(jiffies, orig_jiffies + timeout)) {
  95. pr_debug("I2C: timeout\n");
  96. writeccr(i2c, 0);
  97. result = -EIO;
  98. break;
  99. }
  100. }
  101. x = readb(i2c->base + MPC_I2C_SR);
  102. writeb(0, i2c->base + MPC_I2C_SR);
  103. } else {
  104. /* Interrupt mode */
  105. result = wait_event_interruptible_timeout(i2c->queue,
  106. (i2c->interrupt & CSR_MIF), timeout * HZ);
  107. if (unlikely(result < 0)) {
  108. pr_debug("I2C: wait interrupted\n");
  109. writeccr(i2c, 0);
  110. } else if (unlikely(!(i2c->interrupt & CSR_MIF))) {
  111. pr_debug("I2C: wait timeout\n");
  112. writeccr(i2c, 0);
  113. result = -ETIMEDOUT;
  114. }
  115. x = i2c->interrupt;
  116. i2c->interrupt = 0;
  117. }
  118. if (result < 0)
  119. return result;
  120. if (!(x & CSR_MCF)) {
  121. pr_debug("I2C: unfinished\n");
  122. return -EIO;
  123. }
  124. if (x & CSR_MAL) {
  125. pr_debug("I2C: MAL\n");
  126. return -EIO;
  127. }
  128. if (writing && (x & CSR_RXAK)) {
  129. pr_debug("I2C: No RXAK\n");
  130. /* generate stop */
  131. writeccr(i2c, CCR_MEN);
  132. return -EIO;
  133. }
  134. return 0;
  135. }
  136. static void mpc_i2c_setclock(struct mpc_i2c *i2c)
  137. {
  138. /* Set clock and filters */
  139. if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
  140. writeb(0x31, i2c->base + MPC_I2C_FDR);
  141. writeb(0x10, i2c->base + MPC_I2C_DFSRR);
  142. } else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
  143. writeb(0x3f, i2c->base + MPC_I2C_FDR);
  144. else
  145. writel(0x1031, i2c->base + MPC_I2C_FDR);
  146. }
  147. static void mpc_i2c_start(struct mpc_i2c *i2c)
  148. {
  149. /* Clear arbitration */
  150. writeb(0, i2c->base + MPC_I2C_SR);
  151. /* Start with MEN */
  152. writeccr(i2c, CCR_MEN);
  153. }
  154. static void mpc_i2c_stop(struct mpc_i2c *i2c)
  155. {
  156. writeccr(i2c, CCR_MEN);
  157. }
  158. static int mpc_write(struct mpc_i2c *i2c, int target,
  159. const u8 * data, int length, int restart)
  160. {
  161. int i;
  162. unsigned timeout = i2c->adap.timeout;
  163. u32 flags = restart ? CCR_RSTA : 0;
  164. /* Start with MEN */
  165. if (!restart)
  166. writeccr(i2c, CCR_MEN);
  167. /* Start as master */
  168. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
  169. /* Write target byte */
  170. writeb((target << 1), i2c->base + MPC_I2C_DR);
  171. if (i2c_wait(i2c, timeout, 1) < 0)
  172. return -1;
  173. for (i = 0; i < length; i++) {
  174. /* Write data byte */
  175. writeb(data[i], i2c->base + MPC_I2C_DR);
  176. if (i2c_wait(i2c, timeout, 1) < 0)
  177. return -1;
  178. }
  179. return 0;
  180. }
  181. static int mpc_read(struct mpc_i2c *i2c, int target,
  182. u8 * data, int length, int restart)
  183. {
  184. unsigned timeout = i2c->adap.timeout;
  185. int i;
  186. u32 flags = restart ? CCR_RSTA : 0;
  187. /* Start with MEN */
  188. if (!restart)
  189. writeccr(i2c, CCR_MEN);
  190. /* Switch to read - restart */
  191. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
  192. /* Write target address byte - this time with the read flag set */
  193. writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
  194. if (i2c_wait(i2c, timeout, 1) < 0)
  195. return -1;
  196. if (length) {
  197. if (length == 1)
  198. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
  199. else
  200. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
  201. /* Dummy read */
  202. readb(i2c->base + MPC_I2C_DR);
  203. }
  204. for (i = 0; i < length; i++) {
  205. if (i2c_wait(i2c, timeout, 0) < 0)
  206. return -1;
  207. /* Generate txack on next to last byte */
  208. if (i == length - 2)
  209. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
  210. /* Generate stop on last byte */
  211. if (i == length - 1)
  212. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
  213. data[i] = readb(i2c->base + MPC_I2C_DR);
  214. }
  215. return length;
  216. }
  217. static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  218. {
  219. struct i2c_msg *pmsg;
  220. int i;
  221. int ret = 0;
  222. unsigned long orig_jiffies = jiffies;
  223. struct mpc_i2c *i2c = i2c_get_adapdata(adap);
  224. mpc_i2c_start(i2c);
  225. /* Allow bus up to 1s to become not busy */
  226. while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
  227. if (signal_pending(current)) {
  228. pr_debug("I2C: Interrupted\n");
  229. writeccr(i2c, 0);
  230. return -EINTR;
  231. }
  232. if (time_after(jiffies, orig_jiffies + HZ)) {
  233. pr_debug("I2C: timeout\n");
  234. if (readb(i2c->base + MPC_I2C_SR) ==
  235. (CSR_MCF | CSR_MBB | CSR_RXAK))
  236. mpc_i2c_fixup(i2c);
  237. return -EIO;
  238. }
  239. schedule();
  240. }
  241. for (i = 0; ret >= 0 && i < num; i++) {
  242. pmsg = &msgs[i];
  243. pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
  244. pmsg->flags & I2C_M_RD ? "read" : "write",
  245. pmsg->len, pmsg->addr, i + 1, num);
  246. if (pmsg->flags & I2C_M_RD)
  247. ret =
  248. mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
  249. else
  250. ret =
  251. mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
  252. }
  253. mpc_i2c_stop(i2c);
  254. return (ret < 0) ? ret : num;
  255. }
  256. static u32 mpc_functionality(struct i2c_adapter *adap)
  257. {
  258. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  259. }
  260. static const struct i2c_algorithm mpc_algo = {
  261. .master_xfer = mpc_xfer,
  262. .functionality = mpc_functionality,
  263. };
  264. static struct i2c_adapter mpc_ops = {
  265. .owner = THIS_MODULE,
  266. .name = "MPC adapter",
  267. .id = I2C_HW_MPC107,
  268. .algo = &mpc_algo,
  269. .class = I2C_CLASS_HWMON,
  270. .timeout = 1,
  271. .retries = 1
  272. };
  273. static int fsl_i2c_probe(struct platform_device *pdev)
  274. {
  275. int result = 0;
  276. struct mpc_i2c *i2c;
  277. struct fsl_i2c_platform_data *pdata;
  278. struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  279. pdata = (struct fsl_i2c_platform_data *) pdev->dev.platform_data;
  280. if (!(i2c = kzalloc(sizeof(*i2c), GFP_KERNEL))) {
  281. return -ENOMEM;
  282. }
  283. i2c->irq = platform_get_irq(pdev, 0);
  284. if (i2c->irq < 0) {
  285. result = -ENXIO;
  286. goto fail_get_irq;
  287. }
  288. i2c->flags = pdata->device_flags;
  289. init_waitqueue_head(&i2c->queue);
  290. i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION);
  291. if (!i2c->base) {
  292. printk(KERN_ERR "i2c-mpc - failed to map controller\n");
  293. result = -ENOMEM;
  294. goto fail_map;
  295. }
  296. if (i2c->irq != 0)
  297. if ((result = request_irq(i2c->irq, mpc_i2c_isr,
  298. IRQF_SHARED, "i2c-mpc", i2c)) < 0) {
  299. printk(KERN_ERR
  300. "i2c-mpc - failed to attach interrupt\n");
  301. goto fail_irq;
  302. }
  303. mpc_i2c_setclock(i2c);
  304. platform_set_drvdata(pdev, i2c);
  305. i2c->adap = mpc_ops;
  306. i2c->adap.nr = pdev->id;
  307. i2c_set_adapdata(&i2c->adap, i2c);
  308. i2c->adap.dev.parent = &pdev->dev;
  309. if ((result = i2c_add_numbered_adapter(&i2c->adap)) < 0) {
  310. printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
  311. goto fail_add;
  312. }
  313. return result;
  314. fail_add:
  315. if (i2c->irq != 0)
  316. free_irq(i2c->irq, i2c);
  317. fail_irq:
  318. iounmap(i2c->base);
  319. fail_map:
  320. fail_get_irq:
  321. kfree(i2c);
  322. return result;
  323. };
  324. static int fsl_i2c_remove(struct platform_device *pdev)
  325. {
  326. struct mpc_i2c *i2c = platform_get_drvdata(pdev);
  327. i2c_del_adapter(&i2c->adap);
  328. platform_set_drvdata(pdev, NULL);
  329. if (i2c->irq != 0)
  330. free_irq(i2c->irq, i2c);
  331. iounmap(i2c->base);
  332. kfree(i2c);
  333. return 0;
  334. };
  335. /* Structure for a device driver */
  336. static struct platform_driver fsl_i2c_driver = {
  337. .probe = fsl_i2c_probe,
  338. .remove = fsl_i2c_remove,
  339. .driver = {
  340. .owner = THIS_MODULE,
  341. .name = "fsl-i2c",
  342. },
  343. };
  344. static int __init fsl_i2c_init(void)
  345. {
  346. return platform_driver_register(&fsl_i2c_driver);
  347. }
  348. static void __exit fsl_i2c_exit(void)
  349. {
  350. platform_driver_unregister(&fsl_i2c_driver);
  351. }
  352. module_init(fsl_i2c_init);
  353. module_exit(fsl_i2c_exit);
  354. MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
  355. MODULE_DESCRIPTION
  356. ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
  357. MODULE_LICENSE("GPL");