head_44x.S 20 KB

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  1. /*
  2. * Kernel execution entry point code.
  3. *
  4. * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
  5. * Initial PowerPC version.
  6. * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
  7. * Rewritten for PReP
  8. * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
  9. * Low-level exception handers, MMU support, and rewrite.
  10. * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  11. * PowerPC 8xx modifications.
  12. * Copyright (c) 1998-1999 TiVo, Inc.
  13. * PowerPC 403GCX modifications.
  14. * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  15. * PowerPC 403GCX/405GP modifications.
  16. * Copyright 2000 MontaVista Software Inc.
  17. * PPC405 modifications
  18. * PowerPC 403GCX/405GP modifications.
  19. * Author: MontaVista Software, Inc.
  20. * frank_rowand@mvista.com or source@mvista.com
  21. * debbie_chu@mvista.com
  22. * Copyright 2002-2005 MontaVista Software, Inc.
  23. * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  24. *
  25. * This program is free software; you can redistribute it and/or modify it
  26. * under the terms of the GNU General Public License as published by the
  27. * Free Software Foundation; either version 2 of the License, or (at your
  28. * option) any later version.
  29. */
  30. #include <asm/processor.h>
  31. #include <asm/page.h>
  32. #include <asm/mmu.h>
  33. #include <asm/pgtable.h>
  34. #include <asm/ibm4xx.h>
  35. #include <asm/ibm44x.h>
  36. #include <asm/cputable.h>
  37. #include <asm/thread_info.h>
  38. #include <asm/ppc_asm.h>
  39. #include <asm/asm-offsets.h>
  40. #include "head_booke.h"
  41. /* As with the other PowerPC ports, it is expected that when code
  42. * execution begins here, the following registers contain valid, yet
  43. * optional, information:
  44. *
  45. * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  46. * r4 - Starting address of the init RAM disk
  47. * r5 - Ending address of the init RAM disk
  48. * r6 - Start of kernel command line string (e.g. "mem=128")
  49. * r7 - End of kernel command line string
  50. *
  51. */
  52. .text
  53. _GLOBAL(_stext)
  54. _GLOBAL(_start)
  55. /*
  56. * Reserve a word at a fixed location to store the address
  57. * of abatron_pteptrs
  58. */
  59. nop
  60. /*
  61. * Save parameters we are passed
  62. */
  63. mr r31,r3
  64. mr r30,r4
  65. mr r29,r5
  66. mr r28,r6
  67. mr r27,r7
  68. li r24,0 /* CPU number */
  69. /*
  70. * Set up the initial MMU state
  71. *
  72. * We are still executing code at the virtual address
  73. * mappings set by the firmware for the base of RAM.
  74. *
  75. * We first invalidate all TLB entries but the one
  76. * we are running from. We then load the KERNELBASE
  77. * mappings so we can begin to use kernel addresses
  78. * natively and so the interrupt vector locations are
  79. * permanently pinned (necessary since Book E
  80. * implementations always have translation enabled).
  81. *
  82. * TODO: Use the known TLB entry we are running from to
  83. * determine which physical region we are located
  84. * in. This can be used to determine where in RAM
  85. * (on a shared CPU system) or PCI memory space
  86. * (on a DRAMless system) we are located.
  87. * For now, we assume a perfect world which means
  88. * we are located at the base of DRAM (physical 0).
  89. */
  90. /*
  91. * Search TLB for entry that we are currently using.
  92. * Invalidate all entries but the one we are using.
  93. */
  94. /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
  95. mfspr r3,SPRN_PID /* Get PID */
  96. mfmsr r4 /* Get MSR */
  97. andi. r4,r4,MSR_IS@l /* TS=1? */
  98. beq wmmucr /* If not, leave STS=0 */
  99. oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */
  100. wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
  101. sync
  102. bl invstr /* Find our address */
  103. invstr: mflr r5 /* Make it accessible */
  104. tlbsx r23,0,r5 /* Find entry we are in */
  105. li r4,0 /* Start at TLB entry 0 */
  106. li r3,0 /* Set PAGEID inval value */
  107. 1: cmpw r23,r4 /* Is this our entry? */
  108. beq skpinv /* If so, skip the inval */
  109. tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
  110. skpinv: addi r4,r4,1 /* Increment */
  111. cmpwi r4,64 /* Are we done? */
  112. bne 1b /* If not, repeat */
  113. isync /* If so, context change */
  114. /*
  115. * Configure and load pinned entry into TLB slot 63.
  116. */
  117. lis r3,KERNELBASE@h /* Load the kernel virtual address */
  118. ori r3,r3,KERNELBASE@l
  119. /* Kernel is at the base of RAM */
  120. li r4, 0 /* Load the kernel physical address */
  121. /* Load the kernel PID = 0 */
  122. li r0,0
  123. mtspr SPRN_PID,r0
  124. sync
  125. /* Initialize MMUCR */
  126. li r5,0
  127. mtspr SPRN_MMUCR,r5
  128. sync
  129. /* pageid fields */
  130. clrrwi r3,r3,10 /* Mask off the effective page number */
  131. ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
  132. /* xlat fields */
  133. clrrwi r4,r4,10 /* Mask off the real page number */
  134. /* ERPN is 0 for first 4GB page */
  135. /* attrib fields */
  136. /* Added guarded bit to protect against speculative loads/stores */
  137. li r5,0
  138. ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
  139. li r0,63 /* TLB slot 63 */
  140. tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
  141. tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
  142. tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
  143. /* Force context change */
  144. mfmsr r0
  145. mtspr SPRN_SRR1, r0
  146. lis r0,3f@h
  147. ori r0,r0,3f@l
  148. mtspr SPRN_SRR0,r0
  149. sync
  150. rfi
  151. /* If necessary, invalidate original entry we used */
  152. 3: cmpwi r23,63
  153. beq 4f
  154. li r6,0
  155. tlbwe r6,r23,PPC44x_TLB_PAGEID
  156. isync
  157. 4:
  158. #ifdef CONFIG_SERIAL_TEXT_DEBUG
  159. /*
  160. * Add temporary UART mapping for early debug.
  161. * We can map UART registers wherever we want as long as they don't
  162. * interfere with other system mappings (e.g. with pinned entries).
  163. * For an example of how we handle this - see ocotea.h. --ebs
  164. */
  165. /* pageid fields */
  166. lis r3,UART0_IO_BASE@h
  167. ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_4K
  168. /* xlat fields */
  169. lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */
  170. #ifdef UART0_PHYS_ERPN
  171. ori r4,r4,UART0_PHYS_ERPN /* Add ERPN if above 4GB */
  172. #endif
  173. /* attrib fields */
  174. li r5,0
  175. ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G)
  176. li r0,0 /* TLB slot 0 */
  177. tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
  178. tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
  179. tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
  180. /* Force context change */
  181. isync
  182. #endif /* CONFIG_SERIAL_TEXT_DEBUG */
  183. /* Establish the interrupt vector offsets */
  184. SET_IVOR(0, CriticalInput);
  185. SET_IVOR(1, MachineCheck);
  186. SET_IVOR(2, DataStorage);
  187. SET_IVOR(3, InstructionStorage);
  188. SET_IVOR(4, ExternalInput);
  189. SET_IVOR(5, Alignment);
  190. SET_IVOR(6, Program);
  191. SET_IVOR(7, FloatingPointUnavailable);
  192. SET_IVOR(8, SystemCall);
  193. SET_IVOR(9, AuxillaryProcessorUnavailable);
  194. SET_IVOR(10, Decrementer);
  195. SET_IVOR(11, FixedIntervalTimer);
  196. SET_IVOR(12, WatchdogTimer);
  197. SET_IVOR(13, DataTLBError);
  198. SET_IVOR(14, InstructionTLBError);
  199. SET_IVOR(15, Debug);
  200. /* Establish the interrupt vector base */
  201. lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
  202. mtspr SPRN_IVPR,r4
  203. /*
  204. * This is where the main kernel code starts.
  205. */
  206. /* ptr to current */
  207. lis r2,init_task@h
  208. ori r2,r2,init_task@l
  209. /* ptr to current thread */
  210. addi r4,r2,THREAD /* init task's THREAD */
  211. mtspr SPRN_SPRG3,r4
  212. /* stack */
  213. lis r1,init_thread_union@h
  214. ori r1,r1,init_thread_union@l
  215. li r0,0
  216. stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
  217. bl early_init
  218. /*
  219. * Decide what sort of machine this is and initialize the MMU.
  220. */
  221. mr r3,r31
  222. mr r4,r30
  223. mr r5,r29
  224. mr r6,r28
  225. mr r7,r27
  226. bl machine_init
  227. bl MMU_init
  228. /* Setup PTE pointers for the Abatron bdiGDB */
  229. lis r6, swapper_pg_dir@h
  230. ori r6, r6, swapper_pg_dir@l
  231. lis r5, abatron_pteptrs@h
  232. ori r5, r5, abatron_pteptrs@l
  233. lis r4, KERNELBASE@h
  234. ori r4, r4, KERNELBASE@l
  235. stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
  236. stw r6, 0(r5)
  237. /* Let's move on */
  238. lis r4,start_kernel@h
  239. ori r4,r4,start_kernel@l
  240. lis r3,MSR_KERNEL@h
  241. ori r3,r3,MSR_KERNEL@l
  242. mtspr SPRN_SRR0,r4
  243. mtspr SPRN_SRR1,r3
  244. rfi /* change context and jump to start_kernel */
  245. /*
  246. * Interrupt vector entry code
  247. *
  248. * The Book E MMUs are always on so we don't need to handle
  249. * interrupts in real mode as with previous PPC processors. In
  250. * this case we handle interrupts in the kernel virtual address
  251. * space.
  252. *
  253. * Interrupt vectors are dynamically placed relative to the
  254. * interrupt prefix as determined by the address of interrupt_base.
  255. * The interrupt vectors offsets are programmed using the labels
  256. * for each interrupt vector entry.
  257. *
  258. * Interrupt vectors must be aligned on a 16 byte boundary.
  259. * We align on a 32 byte cache line boundary for good measure.
  260. */
  261. interrupt_base:
  262. /* Critical Input Interrupt */
  263. CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
  264. /* Machine Check Interrupt */
  265. #ifdef CONFIG_440A
  266. MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
  267. #else
  268. CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
  269. #endif
  270. /* Data Storage Interrupt */
  271. START_EXCEPTION(DataStorage)
  272. mtspr SPRN_SPRG0, r10 /* Save some working registers */
  273. mtspr SPRN_SPRG1, r11
  274. mtspr SPRN_SPRG4W, r12
  275. mtspr SPRN_SPRG5W, r13
  276. mfcr r11
  277. mtspr SPRN_SPRG7W, r11
  278. /*
  279. * Check if it was a store fault, if not then bail
  280. * because a user tried to access a kernel or
  281. * read-protected page. Otherwise, get the
  282. * offending address and handle it.
  283. */
  284. mfspr r10, SPRN_ESR
  285. andis. r10, r10, ESR_ST@h
  286. beq 2f
  287. mfspr r10, SPRN_DEAR /* Get faulting address */
  288. /* If we are faulting a kernel address, we have to use the
  289. * kernel page tables.
  290. */
  291. lis r11, TASK_SIZE@h
  292. cmplw r10, r11
  293. blt+ 3f
  294. lis r11, swapper_pg_dir@h
  295. ori r11, r11, swapper_pg_dir@l
  296. mfspr r12,SPRN_MMUCR
  297. rlwinm r12,r12,0,0,23 /* Clear TID */
  298. b 4f
  299. /* Get the PGD for the current thread */
  300. 3:
  301. mfspr r11,SPRN_SPRG3
  302. lwz r11,PGDIR(r11)
  303. /* Load PID into MMUCR TID */
  304. mfspr r12,SPRN_MMUCR /* Get MMUCR */
  305. mfspr r13,SPRN_PID /* Get PID */
  306. rlwimi r12,r13,0,24,31 /* Set TID */
  307. 4:
  308. mtspr SPRN_MMUCR,r12
  309. rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
  310. lwzx r11, r12, r11 /* Get pgd/pmd entry */
  311. rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
  312. beq 2f /* Bail if no table */
  313. rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
  314. lwz r11, 4(r12) /* Get pte entry */
  315. andi. r13, r11, _PAGE_RW /* Is it writeable? */
  316. beq 2f /* Bail if not */
  317. /* Update 'changed'.
  318. */
  319. ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
  320. stw r11, 4(r12) /* Update Linux page table */
  321. li r13, PPC44x_TLB_SR@l /* Set SR */
  322. rlwimi r13, r11, 29, 29, 29 /* SX = _PAGE_HWEXEC */
  323. rlwimi r13, r11, 0, 30, 30 /* SW = _PAGE_RW */
  324. rlwimi r13, r11, 29, 28, 28 /* UR = _PAGE_USER */
  325. rlwimi r12, r11, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
  326. rlwimi r12, r11, 29, 30, 30 /* (_PAGE_USER>>3)->r12 */
  327. and r12, r12, r11 /* HWEXEC/RW & USER */
  328. rlwimi r13, r12, 0, 26, 26 /* UX = HWEXEC & USER */
  329. rlwimi r13, r12, 3, 27, 27 /* UW = RW & USER */
  330. rlwimi r11,r13,0,26,31 /* Insert static perms */
  331. rlwinm r11,r11,0,20,15 /* Clear U0-U3 */
  332. /* find the TLB index that caused the fault. It has to be here. */
  333. tlbsx r10, 0, r10
  334. tlbwe r11, r10, PPC44x_TLB_ATTRIB /* Write ATTRIB */
  335. /* Done...restore registers and get out of here.
  336. */
  337. mfspr r11, SPRN_SPRG7R
  338. mtcr r11
  339. mfspr r13, SPRN_SPRG5R
  340. mfspr r12, SPRN_SPRG4R
  341. mfspr r11, SPRN_SPRG1
  342. mfspr r10, SPRN_SPRG0
  343. rfi /* Force context change */
  344. 2:
  345. /*
  346. * The bailout. Restore registers to pre-exception conditions
  347. * and call the heavyweights to help us out.
  348. */
  349. mfspr r11, SPRN_SPRG7R
  350. mtcr r11
  351. mfspr r13, SPRN_SPRG5R
  352. mfspr r12, SPRN_SPRG4R
  353. mfspr r11, SPRN_SPRG1
  354. mfspr r10, SPRN_SPRG0
  355. b data_access
  356. /* Instruction Storage Interrupt */
  357. INSTRUCTION_STORAGE_EXCEPTION
  358. /* External Input Interrupt */
  359. EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
  360. /* Alignment Interrupt */
  361. ALIGNMENT_EXCEPTION
  362. /* Program Interrupt */
  363. PROGRAM_EXCEPTION
  364. /* Floating Point Unavailable Interrupt */
  365. #ifdef CONFIG_PPC_FPU
  366. FP_UNAVAILABLE_EXCEPTION
  367. #else
  368. EXCEPTION(0x2010, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
  369. #endif
  370. /* System Call Interrupt */
  371. START_EXCEPTION(SystemCall)
  372. NORMAL_EXCEPTION_PROLOG
  373. EXC_XFER_EE_LITE(0x0c00, DoSyscall)
  374. /* Auxillary Processor Unavailable Interrupt */
  375. EXCEPTION(0x2020, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
  376. /* Decrementer Interrupt */
  377. DECREMENTER_EXCEPTION
  378. /* Fixed Internal Timer Interrupt */
  379. /* TODO: Add FIT support */
  380. EXCEPTION(0x1010, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
  381. /* Watchdog Timer Interrupt */
  382. /* TODO: Add watchdog support */
  383. #ifdef CONFIG_BOOKE_WDT
  384. CRITICAL_EXCEPTION(0x1020, WatchdogTimer, WatchdogException)
  385. #else
  386. CRITICAL_EXCEPTION(0x1020, WatchdogTimer, unknown_exception)
  387. #endif
  388. /* Data TLB Error Interrupt */
  389. START_EXCEPTION(DataTLBError)
  390. mtspr SPRN_SPRG0, r10 /* Save some working registers */
  391. mtspr SPRN_SPRG1, r11
  392. mtspr SPRN_SPRG4W, r12
  393. mtspr SPRN_SPRG5W, r13
  394. mfcr r11
  395. mtspr SPRN_SPRG7W, r11
  396. mfspr r10, SPRN_DEAR /* Get faulting address */
  397. /* If we are faulting a kernel address, we have to use the
  398. * kernel page tables.
  399. */
  400. lis r11, TASK_SIZE@h
  401. cmplw r10, r11
  402. blt+ 3f
  403. lis r11, swapper_pg_dir@h
  404. ori r11, r11, swapper_pg_dir@l
  405. mfspr r12,SPRN_MMUCR
  406. rlwinm r12,r12,0,0,23 /* Clear TID */
  407. b 4f
  408. /* Get the PGD for the current thread */
  409. 3:
  410. mfspr r11,SPRN_SPRG3
  411. lwz r11,PGDIR(r11)
  412. /* Load PID into MMUCR TID */
  413. mfspr r12,SPRN_MMUCR
  414. mfspr r13,SPRN_PID /* Get PID */
  415. rlwimi r12,r13,0,24,31 /* Set TID */
  416. 4:
  417. mtspr SPRN_MMUCR,r12
  418. rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
  419. lwzx r11, r12, r11 /* Get pgd/pmd entry */
  420. rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
  421. beq 2f /* Bail if no table */
  422. rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
  423. lwz r11, 4(r12) /* Get pte entry */
  424. andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
  425. beq 2f /* Bail if not present */
  426. ori r11, r11, _PAGE_ACCESSED
  427. stw r11, 4(r12)
  428. /* Jump to common tlb load */
  429. b finish_tlb_load
  430. 2:
  431. /* The bailout. Restore registers to pre-exception conditions
  432. * and call the heavyweights to help us out.
  433. */
  434. mfspr r11, SPRN_SPRG7R
  435. mtcr r11
  436. mfspr r13, SPRN_SPRG5R
  437. mfspr r12, SPRN_SPRG4R
  438. mfspr r11, SPRN_SPRG1
  439. mfspr r10, SPRN_SPRG0
  440. b data_access
  441. /* Instruction TLB Error Interrupt */
  442. /*
  443. * Nearly the same as above, except we get our
  444. * information from different registers and bailout
  445. * to a different point.
  446. */
  447. START_EXCEPTION(InstructionTLBError)
  448. mtspr SPRN_SPRG0, r10 /* Save some working registers */
  449. mtspr SPRN_SPRG1, r11
  450. mtspr SPRN_SPRG4W, r12
  451. mtspr SPRN_SPRG5W, r13
  452. mfcr r11
  453. mtspr SPRN_SPRG7W, r11
  454. mfspr r10, SPRN_SRR0 /* Get faulting address */
  455. /* If we are faulting a kernel address, we have to use the
  456. * kernel page tables.
  457. */
  458. lis r11, TASK_SIZE@h
  459. cmplw r10, r11
  460. blt+ 3f
  461. lis r11, swapper_pg_dir@h
  462. ori r11, r11, swapper_pg_dir@l
  463. mfspr r12,SPRN_MMUCR
  464. rlwinm r12,r12,0,0,23 /* Clear TID */
  465. b 4f
  466. /* Get the PGD for the current thread */
  467. 3:
  468. mfspr r11,SPRN_SPRG3
  469. lwz r11,PGDIR(r11)
  470. /* Load PID into MMUCR TID */
  471. mfspr r12,SPRN_MMUCR
  472. mfspr r13,SPRN_PID /* Get PID */
  473. rlwimi r12,r13,0,24,31 /* Set TID */
  474. 4:
  475. mtspr SPRN_MMUCR,r12
  476. rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
  477. lwzx r11, r12, r11 /* Get pgd/pmd entry */
  478. rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
  479. beq 2f /* Bail if no table */
  480. rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
  481. lwz r11, 4(r12) /* Get pte entry */
  482. andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
  483. beq 2f /* Bail if not present */
  484. ori r11, r11, _PAGE_ACCESSED
  485. stw r11, 4(r12)
  486. /* Jump to common TLB load point */
  487. b finish_tlb_load
  488. 2:
  489. /* The bailout. Restore registers to pre-exception conditions
  490. * and call the heavyweights to help us out.
  491. */
  492. mfspr r11, SPRN_SPRG7R
  493. mtcr r11
  494. mfspr r13, SPRN_SPRG5R
  495. mfspr r12, SPRN_SPRG4R
  496. mfspr r11, SPRN_SPRG1
  497. mfspr r10, SPRN_SPRG0
  498. b InstructionStorage
  499. /* Debug Interrupt */
  500. DEBUG_EXCEPTION
  501. /*
  502. * Local functions
  503. */
  504. /*
  505. * Data TLB exceptions will bail out to this point
  506. * if they can't resolve the lightweight TLB fault.
  507. */
  508. data_access:
  509. NORMAL_EXCEPTION_PROLOG
  510. mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
  511. stw r5,_ESR(r11)
  512. mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
  513. EXC_XFER_EE_LITE(0x0300, handle_page_fault)
  514. /*
  515. * Both the instruction and data TLB miss get to this
  516. * point to load the TLB.
  517. * r10 - EA of fault
  518. * r11 - available to use
  519. * r12 - Pointer to the 64-bit PTE
  520. * r13 - available to use
  521. * MMUCR - loaded with proper value when we get here
  522. * Upon exit, we reload everything and RFI.
  523. */
  524. finish_tlb_load:
  525. /*
  526. * We set execute, because we don't have the granularity to
  527. * properly set this at the page level (Linux problem).
  528. * If shared is set, we cause a zero PID->TID load.
  529. * Many of these bits are software only. Bits we don't set
  530. * here we (properly should) assume have the appropriate value.
  531. */
  532. /* Load the next available TLB index */
  533. lis r13, tlb_44x_index@ha
  534. lwz r13, tlb_44x_index@l(r13)
  535. /* Load the TLB high watermark */
  536. lis r11, tlb_44x_hwater@ha
  537. lwz r11, tlb_44x_hwater@l(r11)
  538. /* Increment, rollover, and store TLB index */
  539. addi r13, r13, 1
  540. cmpw 0, r13, r11 /* reserve entries */
  541. ble 7f
  542. li r13, 0
  543. 7:
  544. /* Store the next available TLB index */
  545. lis r11, tlb_44x_index@ha
  546. stw r13, tlb_44x_index@l(r11)
  547. lwz r11, 0(r12) /* Get MS word of PTE */
  548. lwz r12, 4(r12) /* Get LS word of PTE */
  549. rlwimi r11, r12, 0, 0 , 19 /* Insert RPN */
  550. tlbwe r11, r13, PPC44x_TLB_XLAT /* Write XLAT */
  551. /*
  552. * Create PAGEID. This is the faulting address,
  553. * page size, and valid flag.
  554. */
  555. li r11, PPC44x_TLB_VALID | PPC44x_TLB_4K
  556. rlwimi r10, r11, 0, 20, 31 /* Insert valid and page size */
  557. tlbwe r10, r13, PPC44x_TLB_PAGEID /* Write PAGEID */
  558. li r10, PPC44x_TLB_SR@l /* Set SR */
  559. rlwimi r10, r12, 0, 30, 30 /* Set SW = _PAGE_RW */
  560. rlwimi r10, r12, 29, 29, 29 /* SX = _PAGE_HWEXEC */
  561. rlwimi r10, r12, 29, 28, 28 /* UR = _PAGE_USER */
  562. rlwimi r11, r12, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
  563. and r11, r12, r11 /* HWEXEC & USER */
  564. rlwimi r10, r11, 0, 26, 26 /* UX = HWEXEC & USER */
  565. rlwimi r12, r10, 0, 26, 31 /* Insert static perms */
  566. rlwinm r12, r12, 0, 20, 15 /* Clear U0-U3 */
  567. tlbwe r12, r13, PPC44x_TLB_ATTRIB /* Write ATTRIB */
  568. /* Done...restore registers and get out of here.
  569. */
  570. mfspr r11, SPRN_SPRG7R
  571. mtcr r11
  572. mfspr r13, SPRN_SPRG5R
  573. mfspr r12, SPRN_SPRG4R
  574. mfspr r11, SPRN_SPRG1
  575. mfspr r10, SPRN_SPRG0
  576. rfi /* Force context change */
  577. /*
  578. * Global functions
  579. */
  580. /*
  581. * extern void giveup_altivec(struct task_struct *prev)
  582. *
  583. * The 44x core does not have an AltiVec unit.
  584. */
  585. _GLOBAL(giveup_altivec)
  586. blr
  587. /*
  588. * extern void giveup_fpu(struct task_struct *prev)
  589. *
  590. * The 44x core does not have an FPU.
  591. */
  592. #ifndef CONFIG_PPC_FPU
  593. _GLOBAL(giveup_fpu)
  594. blr
  595. #endif
  596. /*
  597. * extern void abort(void)
  598. *
  599. * At present, this routine just applies a system reset.
  600. */
  601. _GLOBAL(abort)
  602. mfspr r13,SPRN_DBCR0
  603. oris r13,r13,DBCR0_RST_SYSTEM@h
  604. mtspr SPRN_DBCR0,r13
  605. _GLOBAL(set_context)
  606. #ifdef CONFIG_BDI_SWITCH
  607. /* Context switch the PTE pointer for the Abatron BDI2000.
  608. * The PGDIR is the second parameter.
  609. */
  610. lis r5, abatron_pteptrs@h
  611. ori r5, r5, abatron_pteptrs@l
  612. stw r4, 0x4(r5)
  613. #endif
  614. mtspr SPRN_PID,r3
  615. isync /* Force context change */
  616. blr
  617. /*
  618. * We put a few things here that have to be page-aligned. This stuff
  619. * goes at the beginning of the data segment, which is page-aligned.
  620. */
  621. .data
  622. .align 12
  623. .globl sdata
  624. sdata:
  625. .globl empty_zero_page
  626. empty_zero_page:
  627. .space 4096
  628. /*
  629. * To support >32-bit physical addresses, we use an 8KB pgdir.
  630. */
  631. .globl swapper_pg_dir
  632. swapper_pg_dir:
  633. .space 8192
  634. /* Reserved 4k for the critical exception stack & 4k for the machine
  635. * check stack per CPU for kernel mode exceptions */
  636. .section .bss
  637. .align 12
  638. exception_stack_bottom:
  639. .space BOOKE_EXCEPTION_STACK_SIZE
  640. .globl exception_stack_top
  641. exception_stack_top:
  642. /*
  643. * This space gets a copy of optional info passed to us by the bootstrap
  644. * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
  645. */
  646. .globl cmd_line
  647. cmd_line:
  648. .space 512
  649. /*
  650. * Room for two PTE pointers, usually the kernel and current user pointers
  651. * to their respective root page table.
  652. */
  653. abatron_pteptrs:
  654. .space 8