ins.S 2.0 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879
  1. /*
  2. * File: arch/blackfin/lib/ins.S
  3. * Based on:
  4. * Author: Bas Vermeulen <bas@buyways.nl>
  5. *
  6. * Created: Tue Mar 22 15:27:24 CEST 2005
  7. * Description: Implementation of ins{bwl} for BlackFin processors using zero overhead loops.
  8. *
  9. * Modified:
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
  12. *
  13. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, see the file COPYING, or write
  27. * to the Free Software Foundation, Inc.,
  28. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  29. */
  30. #include <linux/linkage.h>
  31. #include <asm/blackfin.h>
  32. .align 2
  33. ENTRY(_insl)
  34. P0 = R0; /* P0 = port */
  35. cli R3;
  36. P1 = R1; /* P1 = address */
  37. P2 = R2; /* P2 = count */
  38. SSYNC;
  39. LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
  40. .Llong_loop_s: R0 = [P0];
  41. [P1++] = R0;
  42. NOP;
  43. .Llong_loop_e: NOP;
  44. sti R3;
  45. RTS;
  46. ENDPROC(_insl)
  47. ENTRY(_insw)
  48. P0 = R0; /* P0 = port */
  49. cli R3;
  50. P1 = R1; /* P1 = address */
  51. P2 = R2; /* P2 = count */
  52. SSYNC;
  53. LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
  54. .Lword_loop_s: R0 = W[P0];
  55. W[P1++] = R0;
  56. NOP;
  57. .Lword_loop_e: NOP;
  58. sti R3;
  59. RTS;
  60. ENDPROC(_insw)
  61. ENTRY(_insb)
  62. P0 = R0; /* P0 = port */
  63. cli R3;
  64. P1 = R1; /* P1 = address */
  65. P2 = R2; /* P2 = count */
  66. SSYNC;
  67. LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
  68. .Lbyte_loop_s: R0 = B[P0];
  69. B[P1++] = R0;
  70. NOP;
  71. .Lbyte_loop_e: NOP;
  72. sti R3;
  73. RTS;
  74. ENDPROC(_insb)