debug.c 4.9 KB

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  1. /*
  2. * Copyright (c) 2008 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "core.h"
  17. #include "reg.h"
  18. #include "hw.h"
  19. static unsigned int ath9k_debug = DBG_DEFAULT;
  20. module_param_named(debug, ath9k_debug, uint, 0);
  21. void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...)
  22. {
  23. if (!sc)
  24. return;
  25. if (sc->sc_debug.debug_mask & dbg_mask) {
  26. va_list args;
  27. va_start(args, fmt);
  28. printk(KERN_DEBUG "ath9k: ");
  29. vprintk(fmt, args);
  30. va_end(args);
  31. }
  32. }
  33. static int ath9k_debugfs_open(struct inode *inode, struct file *file)
  34. {
  35. file->private_data = inode->i_private;
  36. return 0;
  37. }
  38. static ssize_t read_file_dma(struct file *file, char __user *user_buf,
  39. size_t count, loff_t *ppos)
  40. {
  41. struct ath_softc *sc = file->private_data;
  42. struct ath_hal *ah = sc->sc_ah;
  43. char buf[1024];
  44. unsigned int len = 0;
  45. u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
  46. int i, qcuOffset = 0, dcuOffset = 0;
  47. u32 *qcuBase = &val[0], *dcuBase = &val[4];
  48. REG_WRITE(ah, AR_MACMISC,
  49. ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
  50. (AR_MACMISC_MISC_OBS_BUS_1 <<
  51. AR_MACMISC_MISC_OBS_BUS_MSB_S)));
  52. len += snprintf(buf + len, sizeof(buf) - len,
  53. "Raw DMA Debug values:\n");
  54. for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
  55. if (i % 4 == 0)
  56. len += snprintf(buf + len, sizeof(buf) - len, "\n");
  57. val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32)));
  58. len += snprintf(buf + len, sizeof(buf) - len, "%d: %08x ",
  59. i, val[i]);
  60. }
  61. len += snprintf(buf + len, sizeof(buf) - len, "\n\n");
  62. len += snprintf(buf + len, sizeof(buf) - len,
  63. "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
  64. for (i = 0; i < ATH9K_NUM_QUEUES; i++, qcuOffset += 4, dcuOffset += 5) {
  65. if (i == 8) {
  66. qcuOffset = 0;
  67. qcuBase++;
  68. }
  69. if (i == 6) {
  70. dcuOffset = 0;
  71. dcuBase++;
  72. }
  73. len += snprintf(buf + len, sizeof(buf) - len,
  74. "%2d %2x %1x %2x %2x\n",
  75. i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
  76. (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset + 3),
  77. val[2] & (0x7 << (i * 3)) >> (i * 3),
  78. (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
  79. }
  80. len += snprintf(buf + len, sizeof(buf) - len, "\n");
  81. len += snprintf(buf + len, sizeof(buf) - len,
  82. "qcu_stitch state: %2x qcu_fetch state: %2x\n",
  83. (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
  84. len += snprintf(buf + len, sizeof(buf) - len,
  85. "qcu_complete state: %2x dcu_complete state: %2x\n",
  86. (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
  87. len += snprintf(buf + len, sizeof(buf) - len,
  88. "dcu_arb state: %2x dcu_fp state: %2x\n",
  89. (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
  90. len += snprintf(buf + len, sizeof(buf) - len,
  91. "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
  92. (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
  93. len += snprintf(buf + len, sizeof(buf) - len,
  94. "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
  95. (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
  96. len += snprintf(buf + len, sizeof(buf) - len,
  97. "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
  98. (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
  99. len += snprintf(buf + len, sizeof(buf) - len, "pcu observe: 0x%x \n",
  100. REG_READ(ah, AR_OBS_BUS_1));
  101. len += snprintf(buf + len, sizeof(buf) - len,
  102. "AR_CR: 0x%x \n", REG_READ(ah, AR_CR));
  103. return simple_read_from_buffer(user_buf, count, ppos, buf, len);
  104. }
  105. static const struct file_operations fops_dma = {
  106. .read = read_file_dma,
  107. .open = ath9k_debugfs_open,
  108. .owner = THIS_MODULE
  109. };
  110. int ath9k_init_debug(struct ath_softc *sc)
  111. {
  112. sc->sc_debug.debug_mask = ath9k_debug;
  113. sc->sc_debug.debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
  114. if (!sc->sc_debug.debugfs_root)
  115. goto err;
  116. sc->sc_debug.debugfs_phy = debugfs_create_dir(wiphy_name(sc->hw->wiphy),
  117. sc->sc_debug.debugfs_root);
  118. if (!sc->sc_debug.debugfs_phy)
  119. goto err;
  120. sc->sc_debug.debugfs_dma = debugfs_create_file("dma", S_IRUGO,
  121. sc->sc_debug.debugfs_phy, sc, &fops_dma);
  122. if (!sc->sc_debug.debugfs_dma)
  123. goto err;
  124. return 0;
  125. err:
  126. ath9k_exit_debug(sc);
  127. return -ENOMEM;
  128. }
  129. void ath9k_exit_debug(struct ath_softc *sc)
  130. {
  131. debugfs_remove(sc->sc_debug.debugfs_dma);
  132. debugfs_remove(sc->sc_debug.debugfs_phy);
  133. debugfs_remove(sc->sc_debug.debugfs_root);
  134. }