mpc832x_mds.c 2.9 KB

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  1. /*
  2. * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
  3. *
  4. * Description:
  5. * MPC832xE MDS board specific routines.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. #include <linux/stddef.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/errno.h>
  16. #include <linux/reboot.h>
  17. #include <linux/pci.h>
  18. #include <linux/kdev_t.h>
  19. #include <linux/major.h>
  20. #include <linux/console.h>
  21. #include <linux/delay.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/root_dev.h>
  24. #include <linux/initrd.h>
  25. #include <linux/of_platform.h>
  26. #include <linux/of_device.h>
  27. #include <asm/system.h>
  28. #include <linux/atomic.h>
  29. #include <asm/time.h>
  30. #include <asm/io.h>
  31. #include <asm/machdep.h>
  32. #include <asm/ipic.h>
  33. #include <asm/irq.h>
  34. #include <asm/prom.h>
  35. #include <asm/udbg.h>
  36. #include <sysdev/fsl_soc.h>
  37. #include <sysdev/fsl_pci.h>
  38. #include <asm/qe.h>
  39. #include <asm/qe_ic.h>
  40. #include "mpc83xx.h"
  41. #undef DEBUG
  42. #ifdef DEBUG
  43. #define DBG(fmt...) udbg_printf(fmt)
  44. #else
  45. #define DBG(fmt...)
  46. #endif
  47. /* ************************************************************************
  48. *
  49. * Setup the architecture
  50. *
  51. */
  52. static void __init mpc832x_sys_setup_arch(void)
  53. {
  54. struct device_node *np;
  55. u8 __iomem *bcsr_regs = NULL;
  56. if (ppc_md.progress)
  57. ppc_md.progress("mpc832x_sys_setup_arch()", 0);
  58. /* Map BCSR area */
  59. np = of_find_node_by_name(NULL, "bcsr");
  60. if (np) {
  61. struct resource res;
  62. of_address_to_resource(np, 0, &res);
  63. bcsr_regs = ioremap(res.start, resource_size(&res));
  64. of_node_put(np);
  65. }
  66. mpc83xx_setup_pci();
  67. #ifdef CONFIG_QUICC_ENGINE
  68. qe_reset();
  69. if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  70. par_io_init(np);
  71. of_node_put(np);
  72. for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  73. par_io_of_config(np);
  74. }
  75. if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
  76. != NULL){
  77. /* Reset the Ethernet PHYs */
  78. #define BCSR8_FETH_RST 0x50
  79. clrbits8(&bcsr_regs[8], BCSR8_FETH_RST);
  80. udelay(1000);
  81. setbits8(&bcsr_regs[8], BCSR8_FETH_RST);
  82. iounmap(bcsr_regs);
  83. of_node_put(np);
  84. }
  85. #endif /* CONFIG_QUICC_ENGINE */
  86. }
  87. machine_device_initcall(mpc832x_mds, mpc83xx_declare_of_platform_devices);
  88. /*
  89. * Called very early, MMU is off, device-tree isn't unflattened
  90. */
  91. static int __init mpc832x_sys_probe(void)
  92. {
  93. unsigned long root = of_get_flat_dt_root();
  94. return of_flat_dt_is_compatible(root, "MPC832xMDS");
  95. }
  96. define_machine(mpc832x_mds) {
  97. .name = "MPC832x MDS",
  98. .probe = mpc832x_sys_probe,
  99. .setup_arch = mpc832x_sys_setup_arch,
  100. .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
  101. .get_irq = ipic_get_irq,
  102. .restart = mpc83xx_restart,
  103. .time_init = mpc83xx_time_init,
  104. .calibrate_decr = generic_calibrate_decr,
  105. .progress = udbg_progress,
  106. };