cx23888-ir.c 6.2 KB

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  1. /*
  2. * Driver for the Conexant CX23885/7/8 PCIe bridge
  3. *
  4. * CX23888 Integrated Consumer Infrared Controller
  5. *
  6. * Copyright (C) 2009 Andy Walls <awalls@radix.net>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  21. * 02110-1301, USA.
  22. */
  23. #include <media/v4l2-device.h>
  24. #include <media/v4l2-chip-ident.h>
  25. #include "cx23885.h"
  26. #define CX23888_IR_REG_BASE 0x170000
  27. /*
  28. * These CX23888 register offsets have a straightforward one to one mapping
  29. * to the CX23885 register offsets of 0x200 through 0x218
  30. */
  31. #define CX23888_IR_CNTRL_REG 0x170000
  32. #define CX23888_IR_TXCLK_REG 0x170004
  33. #define CX23888_IR_RXCLK_REG 0x170008
  34. #define CX23888_IR_CDUTY_REG 0x17000C
  35. #define CX23888_IR_STATS_REG 0x170010
  36. #define CX23888_IR_IRQEN_REG 0x170014
  37. #define CX23888_IR_FILTR_REG 0x170018
  38. /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */
  39. #define CX23888_IR_FIFO_REG 0x170040
  40. /* CX23888 unique registers */
  41. #define CX23888_IR_SEEDP_REG 0x17001C
  42. #define CX23888_IR_TIMOL_REG 0x170020
  43. #define CX23888_IR_WAKE0_REG 0x170024
  44. #define CX23888_IR_WAKE1_REG 0x170028
  45. #define CX23888_IR_WAKE2_REG 0x17002C
  46. #define CX23888_IR_MASK0_REG 0x170030
  47. #define CX23888_IR_MASK1_REG 0x170034
  48. #define CX23888_IR_MAKS2_REG 0x170038
  49. #define CX23888_IR_DPIPG_REG 0x17003C
  50. #define CX23888_IR_LEARN_REG 0x170044
  51. struct cx23888_ir_state {
  52. struct v4l2_subdev sd;
  53. struct cx23885_dev *dev;
  54. u32 id;
  55. u32 rev;
  56. };
  57. static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd)
  58. {
  59. return v4l2_get_subdevdata(sd);
  60. }
  61. static int cx23888_ir_write(struct cx23885_dev *dev, u32 addr, u8 value)
  62. {
  63. u32 reg = (addr & ~3);
  64. int shift = (addr & 3) * 8;
  65. u32 x = cx_read(reg);
  66. x = (x & ~(0xff << shift)) | ((u32)value << shift);
  67. cx_write(reg, x);
  68. return 0;
  69. }
  70. static
  71. inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value)
  72. {
  73. cx_write(addr, value);
  74. return 0;
  75. }
  76. static u8 cx23888_ir_read(struct cx23885_dev *dev, u32 addr)
  77. {
  78. u32 x = cx_read((addr & ~3));
  79. int shift = (addr & 3) * 8;
  80. return (x >> shift) & 0xff;
  81. }
  82. static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr)
  83. {
  84. return cx_read(addr);
  85. }
  86. static int cx23888_ir_and_or(struct cx23885_dev *dev, u32 addr,
  87. unsigned and_mask, u8 or_value)
  88. {
  89. return cx23888_ir_write(dev, addr,
  90. (cx23888_ir_read(dev, addr) & and_mask) |
  91. or_value);
  92. }
  93. static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
  94. u32 and_mask, u32 or_value)
  95. {
  96. cx_andor(addr, and_mask, or_value);
  97. return 0;
  98. }
  99. static int cx23888_ir_log_status(struct v4l2_subdev *sd)
  100. {
  101. struct cx23888_ir_state *state = to_state(sd);
  102. struct cx23885_dev *dev = state->dev;
  103. u8 cntrl = cx23888_ir_read(dev, CX23888_IR_CNTRL_REG+1);
  104. v4l2_info(sd, "receiver %sabled\n", cntrl & 0x1 ? "en" : "dis");
  105. v4l2_info(sd, "transmitter %sabled\n", cntrl & 0x2 ? "en" : "dis");
  106. return 0;
  107. }
  108. static inline int cx23888_ir_dbg_match(const struct v4l2_dbg_match *match)
  109. {
  110. return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 2;
  111. }
  112. static int cx23888_ir_g_chip_ident(struct v4l2_subdev *sd,
  113. struct v4l2_dbg_chip_ident *chip)
  114. {
  115. struct cx23888_ir_state *state = to_state(sd);
  116. if (cx23888_ir_dbg_match(&chip->match)) {
  117. chip->ident = state->id;
  118. chip->revision = state->rev;
  119. }
  120. return 0;
  121. }
  122. #ifdef CONFIG_VIDEO_ADV_DEBUG
  123. static int cx23888_ir_g_register(struct v4l2_subdev *sd,
  124. struct v4l2_dbg_register *reg)
  125. {
  126. struct cx23888_ir_state *state = to_state(sd);
  127. u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
  128. if (!cx23888_ir_dbg_match(&reg->match))
  129. return -EINVAL;
  130. if ((addr & 0x3) != 0)
  131. return -EINVAL;
  132. if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
  133. return -EINVAL;
  134. if (!capable(CAP_SYS_ADMIN))
  135. return -EPERM;
  136. reg->size = 4;
  137. reg->val = cx23888_ir_read4(state->dev, addr);
  138. return 0;
  139. }
  140. static int cx23888_ir_s_register(struct v4l2_subdev *sd,
  141. struct v4l2_dbg_register *reg)
  142. {
  143. struct cx23888_ir_state *state = to_state(sd);
  144. u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
  145. if (!cx23888_ir_dbg_match(&reg->match))
  146. return -EINVAL;
  147. if ((addr & 0x3) != 0)
  148. return -EINVAL;
  149. if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
  150. return -EINVAL;
  151. if (!capable(CAP_SYS_ADMIN))
  152. return -EPERM;
  153. cx23888_ir_write4(state->dev, addr, reg->val);
  154. return 0;
  155. }
  156. #endif
  157. static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = {
  158. .g_chip_ident = cx23888_ir_g_chip_ident,
  159. .log_status = cx23888_ir_log_status,
  160. #ifdef CONFIG_VIDEO_ADV_DEBUG
  161. .g_register = cx23888_ir_g_register,
  162. .s_register = cx23888_ir_s_register,
  163. #endif
  164. };
  165. static const struct v4l2_subdev_ops cx23888_ir_controller_ops = {
  166. .core = &cx23888_ir_core_ops,
  167. };
  168. int cx23888_ir_probe(struct cx23885_dev *dev)
  169. {
  170. struct cx23888_ir_state *state;
  171. struct v4l2_subdev *sd;
  172. state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL);
  173. if (state == NULL)
  174. return -ENOMEM;
  175. state->dev = dev;
  176. state->id = V4L2_IDENT_CX23888_IR;
  177. state->rev = 0;
  178. sd = &state->sd;
  179. v4l2_subdev_init(sd, &cx23888_ir_controller_ops);
  180. v4l2_set_subdevdata(sd, state);
  181. /* FIXME - fix the formatting of dev->v4l2_dev.name and use it */
  182. snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name);
  183. sd->grp_id = CX23885_HW_888_IR;
  184. return v4l2_device_register_subdev(&dev->v4l2_dev, sd);
  185. }
  186. int cx23888_ir_remove(struct cx23885_dev *dev)
  187. {
  188. struct v4l2_subdev *sd;
  189. struct cx23888_ir_state *state;
  190. sd = cx23885_find_hw(dev, CX23885_HW_888_IR);
  191. if (sd == NULL)
  192. return -ENODEV;
  193. /* Disable receiver and transmitter */
  194. cx23888_ir_and_or(dev, CX23888_IR_CNTRL_REG+1, 0xfc, 0);
  195. state = to_state(sd);
  196. v4l2_device_unregister_subdev(sd);
  197. kfree(state);
  198. /* Nothing more to free() as state held the actual v4l2_subdev object */
  199. return 0;
  200. }