cs4271.c 21 KB

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  1. /*
  2. * CS4271 ASoC codec driver
  3. *
  4. * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * This driver support CS4271 codec being master or slave, working
  17. * in control port mode, connected either via SPI or I2C.
  18. * The data format accepted is I2S or left-justified.
  19. * DAPM support not implemented.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #include <linux/gpio.h>
  25. #include <linux/i2c.h>
  26. #include <linux/spi/spi.h>
  27. #include <linux/of_device.h>
  28. #include <linux/of_gpio.h>
  29. #include <sound/pcm.h>
  30. #include <sound/soc.h>
  31. #include <sound/tlv.h>
  32. #include <sound/cs4271.h>
  33. #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  34. SNDRV_PCM_FMTBIT_S24_LE | \
  35. SNDRV_PCM_FMTBIT_S32_LE)
  36. #define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000
  37. /*
  38. * CS4271 registers
  39. */
  40. #define CS4271_MODE1 0x01 /* Mode Control 1 */
  41. #define CS4271_DACCTL 0x02 /* DAC Control */
  42. #define CS4271_DACVOL 0x03 /* DAC Volume & Mixing Control */
  43. #define CS4271_VOLA 0x04 /* DAC Channel A Volume Control */
  44. #define CS4271_VOLB 0x05 /* DAC Channel B Volume Control */
  45. #define CS4271_ADCCTL 0x06 /* ADC Control */
  46. #define CS4271_MODE2 0x07 /* Mode Control 2 */
  47. #define CS4271_CHIPID 0x08 /* Chip ID */
  48. #define CS4271_FIRSTREG CS4271_MODE1
  49. #define CS4271_LASTREG CS4271_MODE2
  50. #define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1)
  51. /* Bit masks for the CS4271 registers */
  52. #define CS4271_MODE1_MODE_MASK 0xC0
  53. #define CS4271_MODE1_MODE_1X 0x00
  54. #define CS4271_MODE1_MODE_2X 0x80
  55. #define CS4271_MODE1_MODE_4X 0xC0
  56. #define CS4271_MODE1_DIV_MASK 0x30
  57. #define CS4271_MODE1_DIV_1 0x00
  58. #define CS4271_MODE1_DIV_15 0x10
  59. #define CS4271_MODE1_DIV_2 0x20
  60. #define CS4271_MODE1_DIV_3 0x30
  61. #define CS4271_MODE1_MASTER 0x08
  62. #define CS4271_MODE1_DAC_DIF_MASK 0x07
  63. #define CS4271_MODE1_DAC_DIF_LJ 0x00
  64. #define CS4271_MODE1_DAC_DIF_I2S 0x01
  65. #define CS4271_MODE1_DAC_DIF_RJ16 0x02
  66. #define CS4271_MODE1_DAC_DIF_RJ24 0x03
  67. #define CS4271_MODE1_DAC_DIF_RJ20 0x04
  68. #define CS4271_MODE1_DAC_DIF_RJ18 0x05
  69. #define CS4271_DACCTL_AMUTE 0x80
  70. #define CS4271_DACCTL_IF_SLOW 0x40
  71. #define CS4271_DACCTL_DEM_MASK 0x30
  72. #define CS4271_DACCTL_DEM_DIS 0x00
  73. #define CS4271_DACCTL_DEM_441 0x10
  74. #define CS4271_DACCTL_DEM_48 0x20
  75. #define CS4271_DACCTL_DEM_32 0x30
  76. #define CS4271_DACCTL_SVRU 0x08
  77. #define CS4271_DACCTL_SRD 0x04
  78. #define CS4271_DACCTL_INVA 0x02
  79. #define CS4271_DACCTL_INVB 0x01
  80. #define CS4271_DACVOL_BEQUA 0x40
  81. #define CS4271_DACVOL_SOFT 0x20
  82. #define CS4271_DACVOL_ZEROC 0x10
  83. #define CS4271_DACVOL_ATAPI_MASK 0x0F
  84. #define CS4271_DACVOL_ATAPI_M_M 0x00
  85. #define CS4271_DACVOL_ATAPI_M_BR 0x01
  86. #define CS4271_DACVOL_ATAPI_M_BL 0x02
  87. #define CS4271_DACVOL_ATAPI_M_BLR2 0x03
  88. #define CS4271_DACVOL_ATAPI_AR_M 0x04
  89. #define CS4271_DACVOL_ATAPI_AR_BR 0x05
  90. #define CS4271_DACVOL_ATAPI_AR_BL 0x06
  91. #define CS4271_DACVOL_ATAPI_AR_BLR2 0x07
  92. #define CS4271_DACVOL_ATAPI_AL_M 0x08
  93. #define CS4271_DACVOL_ATAPI_AL_BR 0x09
  94. #define CS4271_DACVOL_ATAPI_AL_BL 0x0A
  95. #define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B
  96. #define CS4271_DACVOL_ATAPI_ALR2_M 0x0C
  97. #define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D
  98. #define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E
  99. #define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F
  100. #define CS4271_VOLA_MUTE 0x80
  101. #define CS4271_VOLA_VOL_MASK 0x7F
  102. #define CS4271_VOLB_MUTE 0x80
  103. #define CS4271_VOLB_VOL_MASK 0x7F
  104. #define CS4271_ADCCTL_DITHER16 0x20
  105. #define CS4271_ADCCTL_ADC_DIF_MASK 0x10
  106. #define CS4271_ADCCTL_ADC_DIF_LJ 0x00
  107. #define CS4271_ADCCTL_ADC_DIF_I2S 0x10
  108. #define CS4271_ADCCTL_MUTEA 0x08
  109. #define CS4271_ADCCTL_MUTEB 0x04
  110. #define CS4271_ADCCTL_HPFDA 0x02
  111. #define CS4271_ADCCTL_HPFDB 0x01
  112. #define CS4271_MODE2_LOOP 0x10
  113. #define CS4271_MODE2_MUTECAEQUB 0x08
  114. #define CS4271_MODE2_FREEZE 0x04
  115. #define CS4271_MODE2_CPEN 0x02
  116. #define CS4271_MODE2_PDN 0x01
  117. #define CS4271_CHIPID_PART_MASK 0xF0
  118. #define CS4271_CHIPID_REV_MASK 0x0F
  119. /*
  120. * Default CS4271 power-up configuration
  121. * Array contains non-existing in hw register at address 0
  122. * Array do not include Chip ID, as codec driver does not use
  123. * registers read operations at all
  124. */
  125. static const struct reg_default cs4271_reg_defaults[] = {
  126. { CS4271_MODE1, 0, },
  127. { CS4271_DACCTL, CS4271_DACCTL_AMUTE, },
  128. { CS4271_DACVOL, CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, },
  129. { CS4271_VOLA, 0, },
  130. { CS4271_VOLB, 0, },
  131. { CS4271_ADCCTL, 0, },
  132. { CS4271_MODE2, 0, },
  133. };
  134. static bool cs4271_volatile_reg(struct device *dev, unsigned int reg)
  135. {
  136. return reg == CS4271_CHIPID;
  137. }
  138. struct cs4271_private {
  139. /* SND_SOC_I2C or SND_SOC_SPI */
  140. unsigned int mclk;
  141. bool master;
  142. bool deemph;
  143. struct regmap *regmap;
  144. /* Current sample rate for de-emphasis control */
  145. int rate;
  146. /* GPIO driving Reset pin, if any */
  147. int gpio_nreset;
  148. /* GPIO that disable serial bus, if any */
  149. int gpio_disable;
  150. /* enable soft reset workaround */
  151. bool enable_soft_reset;
  152. };
  153. static const struct snd_soc_dapm_widget cs4271_dapm_widgets[] = {
  154. SND_SOC_DAPM_INPUT("AINA"),
  155. SND_SOC_DAPM_INPUT("AINB"),
  156. SND_SOC_DAPM_OUTPUT("AOUTA+"),
  157. SND_SOC_DAPM_OUTPUT("AOUTA-"),
  158. SND_SOC_DAPM_OUTPUT("AOUTB+"),
  159. SND_SOC_DAPM_OUTPUT("AOUTB-"),
  160. };
  161. static const struct snd_soc_dapm_route cs4271_dapm_routes[] = {
  162. { "Capture", NULL, "AINA" },
  163. { "Capture", NULL, "AINB" },
  164. { "AOUTA+", NULL, "Playback" },
  165. { "AOUTA-", NULL, "Playback" },
  166. { "AOUTB+", NULL, "Playback" },
  167. { "AOUTB-", NULL, "Playback" },
  168. };
  169. /*
  170. * @freq is the desired MCLK rate
  171. * MCLK rate should (c) be the sample rate, multiplied by one of the
  172. * ratios listed in cs4271_mclk_fs_ratios table
  173. */
  174. static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  175. int clk_id, unsigned int freq, int dir)
  176. {
  177. struct snd_soc_codec *codec = codec_dai->codec;
  178. struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
  179. cs4271->mclk = freq;
  180. return 0;
  181. }
  182. static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
  183. unsigned int format)
  184. {
  185. struct snd_soc_codec *codec = codec_dai->codec;
  186. struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
  187. unsigned int val = 0;
  188. int ret;
  189. switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
  190. case SND_SOC_DAIFMT_CBS_CFS:
  191. cs4271->master = 0;
  192. break;
  193. case SND_SOC_DAIFMT_CBM_CFM:
  194. cs4271->master = 1;
  195. val |= CS4271_MODE1_MASTER;
  196. break;
  197. default:
  198. dev_err(codec->dev, "Invalid DAI format\n");
  199. return -EINVAL;
  200. }
  201. switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
  202. case SND_SOC_DAIFMT_LEFT_J:
  203. val |= CS4271_MODE1_DAC_DIF_LJ;
  204. ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
  205. CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
  206. if (ret < 0)
  207. return ret;
  208. break;
  209. case SND_SOC_DAIFMT_I2S:
  210. val |= CS4271_MODE1_DAC_DIF_I2S;
  211. ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
  212. CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
  213. if (ret < 0)
  214. return ret;
  215. break;
  216. default:
  217. dev_err(codec->dev, "Invalid DAI format\n");
  218. return -EINVAL;
  219. }
  220. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
  221. CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val);
  222. if (ret < 0)
  223. return ret;
  224. return 0;
  225. }
  226. static int cs4271_deemph[] = {0, 44100, 48000, 32000};
  227. static int cs4271_set_deemph(struct snd_soc_codec *codec)
  228. {
  229. struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
  230. int i, ret;
  231. int val = CS4271_DACCTL_DEM_DIS;
  232. if (cs4271->deemph) {
  233. /* Find closest de-emphasis freq */
  234. val = 1;
  235. for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
  236. if (abs(cs4271_deemph[i] - cs4271->rate) <
  237. abs(cs4271_deemph[val] - cs4271->rate))
  238. val = i;
  239. val <<= 4;
  240. }
  241. ret = regmap_update_bits(cs4271->regmap, CS4271_DACCTL,
  242. CS4271_DACCTL_DEM_MASK, val);
  243. if (ret < 0)
  244. return ret;
  245. return 0;
  246. }
  247. static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
  248. struct snd_ctl_elem_value *ucontrol)
  249. {
  250. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  251. struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
  252. ucontrol->value.enumerated.item[0] = cs4271->deemph;
  253. return 0;
  254. }
  255. static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
  256. struct snd_ctl_elem_value *ucontrol)
  257. {
  258. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  259. struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
  260. cs4271->deemph = ucontrol->value.enumerated.item[0];
  261. return cs4271_set_deemph(codec);
  262. }
  263. struct cs4271_clk_cfg {
  264. bool master; /* codec mode */
  265. u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */
  266. unsigned short ratio; /* MCLK / sample rate */
  267. u8 ratio_mask; /* ratio bit mask for Master mode */
  268. };
  269. static struct cs4271_clk_cfg cs4271_clk_tab[] = {
  270. {1, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1},
  271. {1, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_15},
  272. {1, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_2},
  273. {1, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_3},
  274. {1, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1},
  275. {1, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_15},
  276. {1, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_2},
  277. {1, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_3},
  278. {1, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1},
  279. {1, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_15},
  280. {1, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_2},
  281. {1, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_3},
  282. {0, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1},
  283. {0, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_1},
  284. {0, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_1},
  285. {0, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_2},
  286. {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2},
  287. {0, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1},
  288. {0, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_1},
  289. {0, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_1},
  290. {0, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_2},
  291. {0, CS4271_MODE1_MODE_2X, 512, CS4271_MODE1_DIV_2},
  292. {0, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1},
  293. {0, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_1},
  294. {0, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_1},
  295. {0, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_2},
  296. {0, CS4271_MODE1_MODE_4X, 256, CS4271_MODE1_DIV_2},
  297. };
  298. #define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)
  299. static int cs4271_hw_params(struct snd_pcm_substream *substream,
  300. struct snd_pcm_hw_params *params,
  301. struct snd_soc_dai *dai)
  302. {
  303. struct snd_soc_codec *codec = dai->codec;
  304. struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
  305. int i, ret;
  306. unsigned int ratio, val;
  307. if (cs4271->enable_soft_reset) {
  308. /*
  309. * Put the codec in soft reset and back again in case it's not
  310. * currently streaming data. This way of bringing the codec in
  311. * sync to the current clocks is not explicitly documented in
  312. * the data sheet, but it seems to work fine, and in contrast
  313. * to a read hardware reset, we don't have to sync back all
  314. * registers every time.
  315. */
  316. if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
  317. !dai->capture_active) ||
  318. (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
  319. !dai->playback_active)) {
  320. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  321. CS4271_MODE2_PDN,
  322. CS4271_MODE2_PDN);
  323. if (ret < 0)
  324. return ret;
  325. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  326. CS4271_MODE2_PDN, 0);
  327. if (ret < 0)
  328. return ret;
  329. }
  330. }
  331. cs4271->rate = params_rate(params);
  332. /* Configure DAC */
  333. if (cs4271->rate < 50000)
  334. val = CS4271_MODE1_MODE_1X;
  335. else if (cs4271->rate < 100000)
  336. val = CS4271_MODE1_MODE_2X;
  337. else
  338. val = CS4271_MODE1_MODE_4X;
  339. ratio = cs4271->mclk / cs4271->rate;
  340. for (i = 0; i < CS4171_NR_RATIOS; i++)
  341. if ((cs4271_clk_tab[i].master == cs4271->master) &&
  342. (cs4271_clk_tab[i].speed_mode == val) &&
  343. (cs4271_clk_tab[i].ratio == ratio))
  344. break;
  345. if (i == CS4171_NR_RATIOS) {
  346. dev_err(codec->dev, "Invalid sample rate\n");
  347. return -EINVAL;
  348. }
  349. val |= cs4271_clk_tab[i].ratio_mask;
  350. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
  351. CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val);
  352. if (ret < 0)
  353. return ret;
  354. return cs4271_set_deemph(codec);
  355. }
  356. static int cs4271_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
  357. {
  358. struct snd_soc_codec *codec = dai->codec;
  359. struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
  360. int ret;
  361. int val_a = 0;
  362. int val_b = 0;
  363. if (stream != SNDRV_PCM_STREAM_PLAYBACK)
  364. return 0;
  365. if (mute) {
  366. val_a = CS4271_VOLA_MUTE;
  367. val_b = CS4271_VOLB_MUTE;
  368. }
  369. ret = regmap_update_bits(cs4271->regmap, CS4271_VOLA,
  370. CS4271_VOLA_MUTE, val_a);
  371. if (ret < 0)
  372. return ret;
  373. ret = regmap_update_bits(cs4271->regmap, CS4271_VOLB,
  374. CS4271_VOLB_MUTE, val_b);
  375. if (ret < 0)
  376. return ret;
  377. return 0;
  378. }
  379. /* CS4271 controls */
  380. static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0);
  381. static const struct snd_kcontrol_new cs4271_snd_controls[] = {
  382. SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB,
  383. 0, 0x7F, 1, cs4271_dac_tlv),
  384. SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0),
  385. SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0),
  386. SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0),
  387. SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
  388. cs4271_get_deemph, cs4271_put_deemph),
  389. SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0),
  390. SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0),
  391. SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0),
  392. SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0),
  393. SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0),
  394. SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0),
  395. SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1),
  396. SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0),
  397. SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1),
  398. SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB,
  399. 7, 1, 1),
  400. };
  401. static const struct snd_soc_dai_ops cs4271_dai_ops = {
  402. .hw_params = cs4271_hw_params,
  403. .set_sysclk = cs4271_set_dai_sysclk,
  404. .set_fmt = cs4271_set_dai_fmt,
  405. .mute_stream = cs4271_mute_stream,
  406. };
  407. static struct snd_soc_dai_driver cs4271_dai = {
  408. .name = "cs4271-hifi",
  409. .playback = {
  410. .stream_name = "Playback",
  411. .channels_min = 2,
  412. .channels_max = 2,
  413. .rates = CS4271_PCM_RATES,
  414. .formats = CS4271_PCM_FORMATS,
  415. },
  416. .capture = {
  417. .stream_name = "Capture",
  418. .channels_min = 2,
  419. .channels_max = 2,
  420. .rates = CS4271_PCM_RATES,
  421. .formats = CS4271_PCM_FORMATS,
  422. },
  423. .ops = &cs4271_dai_ops,
  424. .symmetric_rates = 1,
  425. };
  426. #ifdef CONFIG_PM
  427. static int cs4271_soc_suspend(struct snd_soc_codec *codec)
  428. {
  429. int ret;
  430. struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
  431. /* Set power-down bit */
  432. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  433. CS4271_MODE2_PDN, CS4271_MODE2_PDN);
  434. if (ret < 0)
  435. return ret;
  436. return 0;
  437. }
  438. static int cs4271_soc_resume(struct snd_soc_codec *codec)
  439. {
  440. int ret;
  441. struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
  442. /* Restore codec state */
  443. ret = regcache_sync(cs4271->regmap);
  444. if (ret < 0)
  445. return ret;
  446. /* then disable the power-down bit */
  447. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  448. CS4271_MODE2_PDN, 0);
  449. if (ret < 0)
  450. return ret;
  451. return 0;
  452. }
  453. #else
  454. #define cs4271_soc_suspend NULL
  455. #define cs4271_soc_resume NULL
  456. #endif /* CONFIG_PM */
  457. #ifdef CONFIG_OF
  458. static const struct of_device_id cs4271_dt_ids[] = {
  459. { .compatible = "cirrus,cs4271", },
  460. { }
  461. };
  462. MODULE_DEVICE_TABLE(of, cs4271_dt_ids);
  463. #endif
  464. static int cs4271_probe(struct snd_soc_codec *codec)
  465. {
  466. struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
  467. struct cs4271_platform_data *cs4271plat = codec->dev->platform_data;
  468. int ret;
  469. int gpio_nreset = -EINVAL;
  470. bool amutec_eq_bmutec = false;
  471. #ifdef CONFIG_OF
  472. if (of_match_device(cs4271_dt_ids, codec->dev)) {
  473. gpio_nreset = of_get_named_gpio(codec->dev->of_node,
  474. "reset-gpio", 0);
  475. if (of_get_property(codec->dev->of_node,
  476. "cirrus,amutec-eq-bmutec", NULL))
  477. amutec_eq_bmutec = true;
  478. if (of_get_property(codec->dev->of_node,
  479. "cirrus,enable-soft-reset", NULL))
  480. cs4271->enable_soft_reset = true;
  481. }
  482. #endif
  483. if (cs4271plat) {
  484. if (gpio_is_valid(cs4271plat->gpio_nreset))
  485. gpio_nreset = cs4271plat->gpio_nreset;
  486. amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec;
  487. cs4271->enable_soft_reset = cs4271plat->enable_soft_reset;
  488. }
  489. if (gpio_nreset >= 0)
  490. if (devm_gpio_request(codec->dev, gpio_nreset, "CS4271 Reset"))
  491. gpio_nreset = -EINVAL;
  492. if (gpio_nreset >= 0) {
  493. /* Reset codec */
  494. gpio_direction_output(gpio_nreset, 0);
  495. udelay(1);
  496. gpio_set_value(gpio_nreset, 1);
  497. /* Give the codec time to wake up */
  498. udelay(1);
  499. }
  500. cs4271->gpio_nreset = gpio_nreset;
  501. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  502. CS4271_MODE2_PDN | CS4271_MODE2_CPEN,
  503. CS4271_MODE2_PDN | CS4271_MODE2_CPEN);
  504. if (ret < 0)
  505. return ret;
  506. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  507. CS4271_MODE2_PDN, 0);
  508. if (ret < 0)
  509. return ret;
  510. /* Power-up sequence requires 85 uS */
  511. udelay(85);
  512. if (amutec_eq_bmutec)
  513. regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  514. CS4271_MODE2_MUTECAEQUB,
  515. CS4271_MODE2_MUTECAEQUB);
  516. return 0;
  517. }
  518. static int cs4271_remove(struct snd_soc_codec *codec)
  519. {
  520. struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
  521. if (gpio_is_valid(cs4271->gpio_nreset))
  522. /* Set codec to the reset state */
  523. gpio_set_value(cs4271->gpio_nreset, 0);
  524. return 0;
  525. };
  526. static struct snd_soc_codec_driver soc_codec_dev_cs4271 = {
  527. .probe = cs4271_probe,
  528. .remove = cs4271_remove,
  529. .suspend = cs4271_soc_suspend,
  530. .resume = cs4271_soc_resume,
  531. .controls = cs4271_snd_controls,
  532. .num_controls = ARRAY_SIZE(cs4271_snd_controls),
  533. .dapm_widgets = cs4271_dapm_widgets,
  534. .num_dapm_widgets = ARRAY_SIZE(cs4271_dapm_widgets),
  535. .dapm_routes = cs4271_dapm_routes,
  536. .num_dapm_routes = ARRAY_SIZE(cs4271_dapm_routes),
  537. };
  538. #if defined(CONFIG_SPI_MASTER)
  539. static const struct regmap_config cs4271_spi_regmap = {
  540. .reg_bits = 16,
  541. .val_bits = 8,
  542. .max_register = CS4271_LASTREG,
  543. .read_flag_mask = 0x21,
  544. .write_flag_mask = 0x20,
  545. .reg_defaults = cs4271_reg_defaults,
  546. .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults),
  547. .cache_type = REGCACHE_RBTREE,
  548. .volatile_reg = cs4271_volatile_reg,
  549. };
  550. static int cs4271_spi_probe(struct spi_device *spi)
  551. {
  552. struct cs4271_private *cs4271;
  553. cs4271 = devm_kzalloc(&spi->dev, sizeof(*cs4271), GFP_KERNEL);
  554. if (!cs4271)
  555. return -ENOMEM;
  556. spi_set_drvdata(spi, cs4271);
  557. cs4271->regmap = devm_regmap_init_spi(spi, &cs4271_spi_regmap);
  558. if (IS_ERR(cs4271->regmap))
  559. return PTR_ERR(cs4271->regmap);
  560. return snd_soc_register_codec(&spi->dev, &soc_codec_dev_cs4271,
  561. &cs4271_dai, 1);
  562. }
  563. static int cs4271_spi_remove(struct spi_device *spi)
  564. {
  565. snd_soc_unregister_codec(&spi->dev);
  566. return 0;
  567. }
  568. static struct spi_driver cs4271_spi_driver = {
  569. .driver = {
  570. .name = "cs4271",
  571. .owner = THIS_MODULE,
  572. .of_match_table = of_match_ptr(cs4271_dt_ids),
  573. },
  574. .probe = cs4271_spi_probe,
  575. .remove = cs4271_spi_remove,
  576. };
  577. #endif /* defined(CONFIG_SPI_MASTER) */
  578. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  579. static const struct i2c_device_id cs4271_i2c_id[] = {
  580. {"cs4271", 0},
  581. {}
  582. };
  583. MODULE_DEVICE_TABLE(i2c, cs4271_i2c_id);
  584. static const struct regmap_config cs4271_i2c_regmap = {
  585. .reg_bits = 8,
  586. .val_bits = 8,
  587. .max_register = CS4271_LASTREG,
  588. .reg_defaults = cs4271_reg_defaults,
  589. .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults),
  590. .cache_type = REGCACHE_RBTREE,
  591. .volatile_reg = cs4271_volatile_reg,
  592. };
  593. static int cs4271_i2c_probe(struct i2c_client *client,
  594. const struct i2c_device_id *id)
  595. {
  596. struct cs4271_private *cs4271;
  597. cs4271 = devm_kzalloc(&client->dev, sizeof(*cs4271), GFP_KERNEL);
  598. if (!cs4271)
  599. return -ENOMEM;
  600. i2c_set_clientdata(client, cs4271);
  601. cs4271->regmap = devm_regmap_init_i2c(client, &cs4271_i2c_regmap);
  602. if (IS_ERR(cs4271->regmap))
  603. return PTR_ERR(cs4271->regmap);
  604. return snd_soc_register_codec(&client->dev, &soc_codec_dev_cs4271,
  605. &cs4271_dai, 1);
  606. }
  607. static int cs4271_i2c_remove(struct i2c_client *client)
  608. {
  609. snd_soc_unregister_codec(&client->dev);
  610. return 0;
  611. }
  612. static struct i2c_driver cs4271_i2c_driver = {
  613. .driver = {
  614. .name = "cs4271",
  615. .owner = THIS_MODULE,
  616. .of_match_table = of_match_ptr(cs4271_dt_ids),
  617. },
  618. .id_table = cs4271_i2c_id,
  619. .probe = cs4271_i2c_probe,
  620. .remove = cs4271_i2c_remove,
  621. };
  622. #endif /* defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) */
  623. /*
  624. * We only register our serial bus driver here without
  625. * assignment to particular chip. So if any of the below
  626. * fails, there is some problem with I2C or SPI subsystem.
  627. * In most cases this module will be compiled with support
  628. * of only one serial bus.
  629. */
  630. static int __init cs4271_modinit(void)
  631. {
  632. int ret;
  633. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  634. ret = i2c_add_driver(&cs4271_i2c_driver);
  635. if (ret) {
  636. pr_err("Failed to register CS4271 I2C driver: %d\n", ret);
  637. return ret;
  638. }
  639. #endif
  640. #if defined(CONFIG_SPI_MASTER)
  641. ret = spi_register_driver(&cs4271_spi_driver);
  642. if (ret) {
  643. pr_err("Failed to register CS4271 SPI driver: %d\n", ret);
  644. return ret;
  645. }
  646. #endif
  647. return 0;
  648. }
  649. module_init(cs4271_modinit);
  650. static void __exit cs4271_modexit(void)
  651. {
  652. #if defined(CONFIG_SPI_MASTER)
  653. spi_unregister_driver(&cs4271_spi_driver);
  654. #endif
  655. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  656. i2c_del_driver(&cs4271_i2c_driver);
  657. #endif
  658. }
  659. module_exit(cs4271_modexit);
  660. MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
  661. MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
  662. MODULE_LICENSE("GPL");