dm9000.c 31 KB

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  1. /*
  2. * dm9000.c: Version 1.2 03/18/2003
  3. *
  4. * A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
  5. * Copyright (C) 1997 Sten Wang
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version 2
  10. * of the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
  18. *
  19. * V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
  20. * 06/22/2001 Support DM9801 progrmming
  21. * E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
  22. * E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
  23. * R17 = (R17 & 0xfff0) | NF + 3
  24. * E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
  25. * R17 = (R17 & 0xfff0) | NF
  26. *
  27. * v1.00 modify by simon 2001.9.5
  28. * change for kernel 2.4.x
  29. *
  30. * v1.1 11/09/2001 fix force mode bug
  31. *
  32. * v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
  33. * Fixed phy reset.
  34. * Added tx/rx 32 bit mode.
  35. * Cleaned up for kernel merge.
  36. *
  37. * 03/03/2004 Sascha Hauer <s.hauer@pengutronix.de>
  38. * Port to 2.6 kernel
  39. *
  40. * 24-Sep-2004 Ben Dooks <ben@simtec.co.uk>
  41. * Cleanup of code to remove ifdefs
  42. * Allowed platform device data to influence access width
  43. * Reformatting areas of code
  44. *
  45. * 17-Mar-2005 Sascha Hauer <s.hauer@pengutronix.de>
  46. * * removed 2.4 style module parameters
  47. * * removed removed unused stat counter and fixed
  48. * net_device_stats
  49. * * introduced tx_timeout function
  50. * * reworked locking
  51. *
  52. * 01-Jul-2005 Ben Dooks <ben@simtec.co.uk>
  53. * * fixed spinlock call without pointer
  54. * * ensure spinlock is initialised
  55. */
  56. #include <linux/module.h>
  57. #include <linux/ioport.h>
  58. #include <linux/netdevice.h>
  59. #include <linux/etherdevice.h>
  60. #include <linux/init.h>
  61. #include <linux/skbuff.h>
  62. #include <linux/spinlock.h>
  63. #include <linux/crc32.h>
  64. #include <linux/mii.h>
  65. #include <linux/ethtool.h>
  66. #include <linux/dm9000.h>
  67. #include <linux/delay.h>
  68. #include <linux/platform_device.h>
  69. #include <linux/irq.h>
  70. #include <asm/delay.h>
  71. #include <asm/irq.h>
  72. #include <asm/io.h>
  73. #include "dm9000.h"
  74. /* Board/System/Debug information/definition ---------------- */
  75. #define DM9000_PHY 0x40 /* PHY address 0x01 */
  76. #define CARDNAME "dm9000"
  77. #define PFX CARDNAME ": "
  78. #define DRV_VERSION "1.30"
  79. #ifdef CONFIG_BLACKFIN
  80. #define readsb insb
  81. #define readsw insw
  82. #define readsl insl
  83. #define writesb outsb
  84. #define writesw outsw
  85. #define writesl outsl
  86. #define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH
  87. #else
  88. #define DEFAULT_TRIGGER (0)
  89. #endif
  90. /*
  91. * Transmit timeout, default 5 seconds.
  92. */
  93. static int watchdog = 5000;
  94. module_param(watchdog, int, 0400);
  95. MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
  96. /* DM9000 register address locking.
  97. *
  98. * The DM9000 uses an address register to control where data written
  99. * to the data register goes. This means that the address register
  100. * must be preserved over interrupts or similar calls.
  101. *
  102. * During interrupt and other critical calls, a spinlock is used to
  103. * protect the system, but the calls themselves save the address
  104. * in the address register in case they are interrupting another
  105. * access to the device.
  106. *
  107. * For general accesses a lock is provided so that calls which are
  108. * allowed to sleep are serialised so that the address register does
  109. * not need to be saved. This lock also serves to serialise access
  110. * to the EEPROM and PHY access registers which are shared between
  111. * these two devices.
  112. */
  113. /* Structure/enum declaration ------------------------------- */
  114. typedef struct board_info {
  115. void __iomem *io_addr; /* Register I/O base address */
  116. void __iomem *io_data; /* Data I/O address */
  117. u16 irq; /* IRQ */
  118. u16 tx_pkt_cnt;
  119. u16 queue_pkt_len;
  120. u16 queue_start_addr;
  121. u16 dbug_cnt;
  122. u8 io_mode; /* 0:word, 2:byte */
  123. u8 phy_addr;
  124. unsigned int flags;
  125. unsigned int in_suspend :1;
  126. int debug_level;
  127. void (*inblk)(void __iomem *port, void *data, int length);
  128. void (*outblk)(void __iomem *port, void *data, int length);
  129. void (*dumpblk)(void __iomem *port, int length);
  130. struct device *dev; /* parent device */
  131. struct resource *addr_res; /* resources found */
  132. struct resource *data_res;
  133. struct resource *addr_req; /* resources requested */
  134. struct resource *data_req;
  135. struct resource *irq_res;
  136. struct mutex addr_lock; /* phy and eeprom access lock */
  137. spinlock_t lock;
  138. struct mii_if_info mii;
  139. u32 msg_enable;
  140. } board_info_t;
  141. /* debug code */
  142. #define dm9000_dbg(db, lev, msg...) do { \
  143. if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \
  144. (lev) < db->debug_level) { \
  145. dev_dbg(db->dev, msg); \
  146. } \
  147. } while (0)
  148. static inline board_info_t *to_dm9000_board(struct net_device *dev)
  149. {
  150. return dev->priv;
  151. }
  152. /* function declaration ------------------------------------- */
  153. static int dm9000_probe(struct platform_device *);
  154. static int dm9000_open(struct net_device *);
  155. static int dm9000_start_xmit(struct sk_buff *, struct net_device *);
  156. static int dm9000_stop(struct net_device *);
  157. static void dm9000_init_dm9000(struct net_device *);
  158. static irqreturn_t dm9000_interrupt(int, void *);
  159. static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg);
  160. static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg,
  161. int value);
  162. static void dm9000_read_eeprom(board_info_t *, int addr, u8 *to);
  163. static void dm9000_write_eeprom(board_info_t *, int addr, u8 *dp);
  164. static void dm9000_rx(struct net_device *);
  165. static void dm9000_hash_table(struct net_device *);
  166. //#define DM9000_PROGRAM_EEPROM
  167. #ifdef DM9000_PROGRAM_EEPROM
  168. static void program_eeprom(board_info_t * db);
  169. #endif
  170. /* DM9000 network board routine ---------------------------- */
  171. static void
  172. dm9000_reset(board_info_t * db)
  173. {
  174. dev_dbg(db->dev, "resetting device\n");
  175. /* RESET device */
  176. writeb(DM9000_NCR, db->io_addr);
  177. udelay(200);
  178. writeb(NCR_RST, db->io_data);
  179. udelay(200);
  180. }
  181. /*
  182. * Read a byte from I/O port
  183. */
  184. static u8
  185. ior(board_info_t * db, int reg)
  186. {
  187. writeb(reg, db->io_addr);
  188. return readb(db->io_data);
  189. }
  190. /*
  191. * Write a byte to I/O port
  192. */
  193. static void
  194. iow(board_info_t * db, int reg, int value)
  195. {
  196. writeb(reg, db->io_addr);
  197. writeb(value, db->io_data);
  198. }
  199. /* routines for sending block to chip */
  200. static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
  201. {
  202. writesb(reg, data, count);
  203. }
  204. static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count)
  205. {
  206. writesw(reg, data, (count+1) >> 1);
  207. }
  208. static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count)
  209. {
  210. writesl(reg, data, (count+3) >> 2);
  211. }
  212. /* input block from chip to memory */
  213. static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count)
  214. {
  215. readsb(reg, data, count);
  216. }
  217. static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count)
  218. {
  219. readsw(reg, data, (count+1) >> 1);
  220. }
  221. static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count)
  222. {
  223. readsl(reg, data, (count+3) >> 2);
  224. }
  225. /* dump block from chip to null */
  226. static void dm9000_dumpblk_8bit(void __iomem *reg, int count)
  227. {
  228. int i;
  229. int tmp;
  230. for (i = 0; i < count; i++)
  231. tmp = readb(reg);
  232. }
  233. static void dm9000_dumpblk_16bit(void __iomem *reg, int count)
  234. {
  235. int i;
  236. int tmp;
  237. count = (count + 1) >> 1;
  238. for (i = 0; i < count; i++)
  239. tmp = readw(reg);
  240. }
  241. static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
  242. {
  243. int i;
  244. int tmp;
  245. count = (count + 3) >> 2;
  246. for (i = 0; i < count; i++)
  247. tmp = readl(reg);
  248. }
  249. /* dm9000_set_io
  250. *
  251. * select the specified set of io routines to use with the
  252. * device
  253. */
  254. static void dm9000_set_io(struct board_info *db, int byte_width)
  255. {
  256. /* use the size of the data resource to work out what IO
  257. * routines we want to use
  258. */
  259. switch (byte_width) {
  260. case 1:
  261. db->dumpblk = dm9000_dumpblk_8bit;
  262. db->outblk = dm9000_outblk_8bit;
  263. db->inblk = dm9000_inblk_8bit;
  264. break;
  265. case 3:
  266. dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n");
  267. case 2:
  268. db->dumpblk = dm9000_dumpblk_16bit;
  269. db->outblk = dm9000_outblk_16bit;
  270. db->inblk = dm9000_inblk_16bit;
  271. break;
  272. case 4:
  273. default:
  274. db->dumpblk = dm9000_dumpblk_32bit;
  275. db->outblk = dm9000_outblk_32bit;
  276. db->inblk = dm9000_inblk_32bit;
  277. break;
  278. }
  279. }
  280. /* Our watchdog timed out. Called by the networking layer */
  281. static void dm9000_timeout(struct net_device *dev)
  282. {
  283. board_info_t *db = (board_info_t *) dev->priv;
  284. u8 reg_save;
  285. unsigned long flags;
  286. /* Save previous register address */
  287. reg_save = readb(db->io_addr);
  288. spin_lock_irqsave(&db->lock,flags);
  289. netif_stop_queue(dev);
  290. dm9000_reset(db);
  291. dm9000_init_dm9000(dev);
  292. /* We can accept TX packets again */
  293. dev->trans_start = jiffies;
  294. netif_wake_queue(dev);
  295. /* Restore previous register address */
  296. writeb(reg_save, db->io_addr);
  297. spin_unlock_irqrestore(&db->lock,flags);
  298. }
  299. #ifdef CONFIG_NET_POLL_CONTROLLER
  300. /*
  301. *Used by netconsole
  302. */
  303. static void dm9000_poll_controller(struct net_device *dev)
  304. {
  305. disable_irq(dev->irq);
  306. dm9000_interrupt(dev->irq,dev);
  307. enable_irq(dev->irq);
  308. }
  309. #endif
  310. /* ethtool ops */
  311. static void dm9000_get_drvinfo(struct net_device *dev,
  312. struct ethtool_drvinfo *info)
  313. {
  314. board_info_t *dm = to_dm9000_board(dev);
  315. strcpy(info->driver, CARDNAME);
  316. strcpy(info->version, DRV_VERSION);
  317. strcpy(info->bus_info, to_platform_device(dm->dev)->name);
  318. }
  319. static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  320. {
  321. board_info_t *dm = to_dm9000_board(dev);
  322. mii_ethtool_gset(&dm->mii, cmd);
  323. return 0;
  324. }
  325. static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  326. {
  327. board_info_t *dm = to_dm9000_board(dev);
  328. return mii_ethtool_sset(&dm->mii, cmd);
  329. }
  330. static int dm9000_nway_reset(struct net_device *dev)
  331. {
  332. board_info_t *dm = to_dm9000_board(dev);
  333. return mii_nway_restart(&dm->mii);
  334. }
  335. static u32 dm9000_get_link(struct net_device *dev)
  336. {
  337. board_info_t *dm = to_dm9000_board(dev);
  338. return mii_link_ok(&dm->mii);
  339. }
  340. #define DM_EEPROM_MAGIC (0x444D394B)
  341. static int dm9000_get_eeprom_len(struct net_device *dev)
  342. {
  343. return 128;
  344. }
  345. static int dm9000_get_eeprom(struct net_device *dev,
  346. struct ethtool_eeprom *ee, u8 *data)
  347. {
  348. board_info_t *dm = to_dm9000_board(dev);
  349. int offset = ee->offset;
  350. int len = ee->len;
  351. int i;
  352. /* EEPROM access is aligned to two bytes */
  353. if ((len & 1) != 0 || (offset & 1) != 0)
  354. return -EINVAL;
  355. ee->magic = DM_EEPROM_MAGIC;
  356. for (i = 0; i < len; i += 2)
  357. dm9000_read_eeprom(dm, (offset + i) / 2, data + i);
  358. return 0;
  359. }
  360. static int dm9000_set_eeprom(struct net_device *dev,
  361. struct ethtool_eeprom *ee, u8 *data)
  362. {
  363. board_info_t *dm = to_dm9000_board(dev);
  364. int offset = ee->offset;
  365. int len = ee->len;
  366. int i;
  367. /* EEPROM access is aligned to two bytes */
  368. if ((len & 1) != 0 || (offset & 1) != 0)
  369. return -EINVAL;
  370. if (ee->magic != DM_EEPROM_MAGIC)
  371. return -EINVAL;
  372. for (i = 0; i < len; i += 2)
  373. dm9000_write_eeprom(dm, (offset + i) / 2, data + i);
  374. return 0;
  375. }
  376. static const struct ethtool_ops dm9000_ethtool_ops = {
  377. .get_drvinfo = dm9000_get_drvinfo,
  378. .get_settings = dm9000_get_settings,
  379. .set_settings = dm9000_set_settings,
  380. .nway_reset = dm9000_nway_reset,
  381. .get_link = dm9000_get_link,
  382. .get_eeprom_len = dm9000_get_eeprom_len,
  383. .get_eeprom = dm9000_get_eeprom,
  384. .set_eeprom = dm9000_set_eeprom,
  385. };
  386. /* dm9000_release_board
  387. *
  388. * release a board, and any mapped resources
  389. */
  390. static void
  391. dm9000_release_board(struct platform_device *pdev, struct board_info *db)
  392. {
  393. if (db->data_res == NULL) {
  394. if (db->addr_res != NULL)
  395. release_mem_region((unsigned long)db->io_addr, 4);
  396. return;
  397. }
  398. /* unmap our resources */
  399. iounmap(db->io_addr);
  400. iounmap(db->io_data);
  401. /* release the resources */
  402. if (db->data_req != NULL) {
  403. release_resource(db->data_req);
  404. kfree(db->data_req);
  405. }
  406. if (db->addr_req != NULL) {
  407. release_resource(db->addr_req);
  408. kfree(db->addr_req);
  409. }
  410. }
  411. #define res_size(_r) (((_r)->end - (_r)->start) + 1)
  412. /*
  413. * Search DM9000 board, allocate space and register it
  414. */
  415. static int
  416. dm9000_probe(struct platform_device *pdev)
  417. {
  418. struct dm9000_plat_data *pdata = pdev->dev.platform_data;
  419. struct board_info *db; /* Point a board information structure */
  420. struct net_device *ndev;
  421. unsigned long base;
  422. int ret = 0;
  423. int iosize;
  424. int i;
  425. u32 id_val;
  426. /* Init network device */
  427. ndev = alloc_etherdev(sizeof (struct board_info));
  428. if (!ndev) {
  429. dev_err(&pdev->dev, "could not allocate device.\n");
  430. return -ENOMEM;
  431. }
  432. SET_NETDEV_DEV(ndev, &pdev->dev);
  433. dev_dbg(&pdev->dev, "dm9000_probe()");
  434. /* setup board info structure */
  435. db = (struct board_info *) ndev->priv;
  436. memset(db, 0, sizeof (*db));
  437. db->dev = &pdev->dev;
  438. spin_lock_init(&db->lock);
  439. mutex_init(&db->addr_lock);
  440. if (pdev->num_resources < 2) {
  441. ret = -ENODEV;
  442. goto out;
  443. } else if (pdev->num_resources == 2) {
  444. base = pdev->resource[0].start;
  445. if (!request_mem_region(base, 4, ndev->name)) {
  446. ret = -EBUSY;
  447. goto out;
  448. }
  449. ndev->base_addr = base;
  450. ndev->irq = pdev->resource[1].start;
  451. db->io_addr = (void __iomem *)base;
  452. db->io_data = (void __iomem *)(base + 4);
  453. /* ensure at least we have a default set of IO routines */
  454. dm9000_set_io(db, 2);
  455. } else {
  456. db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  457. db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  458. db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  459. if (db->addr_res == NULL || db->data_res == NULL ||
  460. db->irq_res == NULL) {
  461. dev_err(db->dev, "insufficient resources\n");
  462. ret = -ENOENT;
  463. goto out;
  464. }
  465. i = res_size(db->addr_res);
  466. db->addr_req = request_mem_region(db->addr_res->start, i,
  467. pdev->name);
  468. if (db->addr_req == NULL) {
  469. dev_err(db->dev, "cannot claim address reg area\n");
  470. ret = -EIO;
  471. goto out;
  472. }
  473. db->io_addr = ioremap(db->addr_res->start, i);
  474. if (db->io_addr == NULL) {
  475. dev_err(db->dev, "failed to ioremap address reg\n");
  476. ret = -EINVAL;
  477. goto out;
  478. }
  479. iosize = res_size(db->data_res);
  480. db->data_req = request_mem_region(db->data_res->start, iosize,
  481. pdev->name);
  482. if (db->data_req == NULL) {
  483. dev_err(db->dev, "cannot claim data reg area\n");
  484. ret = -EIO;
  485. goto out;
  486. }
  487. db->io_data = ioremap(db->data_res->start, iosize);
  488. if (db->io_data == NULL) {
  489. dev_err(db->dev,"failed to ioremap data reg\n");
  490. ret = -EINVAL;
  491. goto out;
  492. }
  493. /* fill in parameters for net-dev structure */
  494. ndev->base_addr = (unsigned long)db->io_addr;
  495. ndev->irq = db->irq_res->start;
  496. /* ensure at least we have a default set of IO routines */
  497. dm9000_set_io(db, iosize);
  498. }
  499. /* check to see if anything is being over-ridden */
  500. if (pdata != NULL) {
  501. /* check to see if the driver wants to over-ride the
  502. * default IO width */
  503. if (pdata->flags & DM9000_PLATF_8BITONLY)
  504. dm9000_set_io(db, 1);
  505. if (pdata->flags & DM9000_PLATF_16BITONLY)
  506. dm9000_set_io(db, 2);
  507. if (pdata->flags & DM9000_PLATF_32BITONLY)
  508. dm9000_set_io(db, 4);
  509. /* check to see if there are any IO routine
  510. * over-rides */
  511. if (pdata->inblk != NULL)
  512. db->inblk = pdata->inblk;
  513. if (pdata->outblk != NULL)
  514. db->outblk = pdata->outblk;
  515. if (pdata->dumpblk != NULL)
  516. db->dumpblk = pdata->dumpblk;
  517. db->flags = pdata->flags;
  518. }
  519. dm9000_reset(db);
  520. /* try two times, DM9000 sometimes gets the first read wrong */
  521. for (i = 0; i < 2; i++) {
  522. id_val = ior(db, DM9000_VIDL);
  523. id_val |= (u32)ior(db, DM9000_VIDH) << 8;
  524. id_val |= (u32)ior(db, DM9000_PIDL) << 16;
  525. id_val |= (u32)ior(db, DM9000_PIDH) << 24;
  526. if (id_val == DM9000_ID)
  527. break;
  528. dev_err(db->dev, "read wrong id 0x%08x\n", id_val);
  529. }
  530. if (id_val != DM9000_ID) {
  531. dev_err(db->dev, "wrong id: 0x%08x\n", id_val);
  532. ret = -ENODEV;
  533. goto out;
  534. }
  535. /* from this point we assume that we have found a DM9000 */
  536. /* driver system function */
  537. ether_setup(ndev);
  538. ndev->open = &dm9000_open;
  539. ndev->hard_start_xmit = &dm9000_start_xmit;
  540. ndev->tx_timeout = &dm9000_timeout;
  541. ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
  542. ndev->stop = &dm9000_stop;
  543. ndev->set_multicast_list = &dm9000_hash_table;
  544. ndev->ethtool_ops = &dm9000_ethtool_ops;
  545. #ifdef CONFIG_NET_POLL_CONTROLLER
  546. ndev->poll_controller = &dm9000_poll_controller;
  547. #endif
  548. #ifdef DM9000_PROGRAM_EEPROM
  549. program_eeprom(db);
  550. #endif
  551. db->msg_enable = NETIF_MSG_LINK;
  552. db->mii.phy_id_mask = 0x1f;
  553. db->mii.reg_num_mask = 0x1f;
  554. db->mii.force_media = 0;
  555. db->mii.full_duplex = 0;
  556. db->mii.dev = ndev;
  557. db->mii.mdio_read = dm9000_phy_read;
  558. db->mii.mdio_write = dm9000_phy_write;
  559. /* try reading the node address from the attached EEPROM */
  560. for (i = 0; i < 6; i += 2)
  561. dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i);
  562. if (!is_valid_ether_addr(ndev->dev_addr)) {
  563. /* try reading from mac */
  564. for (i = 0; i < 6; i++)
  565. ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
  566. }
  567. if (!is_valid_ether_addr(ndev->dev_addr))
  568. dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
  569. "set using ifconfig\n", ndev->name);
  570. platform_set_drvdata(pdev, ndev);
  571. ret = register_netdev(ndev);
  572. if (ret == 0) {
  573. DECLARE_MAC_BUF(mac);
  574. printk("%s: dm9000 at %p,%p IRQ %d MAC: %s\n",
  575. ndev->name, db->io_addr, db->io_data, ndev->irq,
  576. print_mac(mac, ndev->dev_addr));
  577. }
  578. return 0;
  579. out:
  580. dev_err(db->dev, "not found (%d).\n", ret);
  581. dm9000_release_board(pdev, db);
  582. free_netdev(ndev);
  583. return ret;
  584. }
  585. /*
  586. * Open the interface.
  587. * The interface is opened whenever "ifconfig" actives it.
  588. */
  589. static int
  590. dm9000_open(struct net_device *dev)
  591. {
  592. board_info_t *db = (board_info_t *) dev->priv;
  593. unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK;
  594. dev_dbg(db->dev, "entering %s\n", __func__);
  595. /* If there is no IRQ type specified, default to something that
  596. * may work, and tell the user that this is a problem */
  597. if (irqflags == IRQF_TRIGGER_NONE) {
  598. dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n");
  599. irqflags = DEFAULT_TRIGGER;
  600. }
  601. irqflags |= IRQF_SHARED;
  602. if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev))
  603. return -EAGAIN;
  604. /* Initialize DM9000 board */
  605. dm9000_reset(db);
  606. dm9000_init_dm9000(dev);
  607. /* Init driver variable */
  608. db->dbug_cnt = 0;
  609. mii_check_media(&db->mii, netif_msg_link(db), 1);
  610. netif_start_queue(dev);
  611. return 0;
  612. }
  613. /*
  614. * Initilize dm9000 board
  615. */
  616. static void
  617. dm9000_init_dm9000(struct net_device *dev)
  618. {
  619. board_info_t *db = (board_info_t *) dev->priv;
  620. dm9000_dbg(db, 1, "entering %s\n", __func__);
  621. /* I/O mode */
  622. db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
  623. /* GPIO0 on pre-activate PHY */
  624. iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
  625. iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
  626. iow(db, DM9000_GPR, 0); /* Enable PHY */
  627. if (db->flags & DM9000_PLATF_EXT_PHY)
  628. iow(db, DM9000_NCR, NCR_EXT_PHY);
  629. /* Program operating register */
  630. iow(db, DM9000_TCR, 0); /* TX Polling clear */
  631. iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
  632. iow(db, DM9000_FCR, 0xff); /* Flow Control */
  633. iow(db, DM9000_SMCR, 0); /* Special Mode */
  634. /* clear TX status */
  635. iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
  636. iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
  637. /* Set address filter table */
  638. dm9000_hash_table(dev);
  639. /* Activate DM9000 */
  640. iow(db, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
  641. /* Enable TX/RX interrupt mask */
  642. iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
  643. /* Init Driver variable */
  644. db->tx_pkt_cnt = 0;
  645. db->queue_pkt_len = 0;
  646. dev->trans_start = 0;
  647. }
  648. /*
  649. * Hardware start transmission.
  650. * Send a packet to media from the upper layer.
  651. */
  652. static int
  653. dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
  654. {
  655. unsigned long flags;
  656. board_info_t *db = (board_info_t *) dev->priv;
  657. dm9000_dbg(db, 3, "%s:\n", __func__);
  658. if (db->tx_pkt_cnt > 1)
  659. return 1;
  660. spin_lock_irqsave(&db->lock, flags);
  661. /* Move data to DM9000 TX RAM */
  662. writeb(DM9000_MWCMD, db->io_addr);
  663. (db->outblk)(db->io_data, skb->data, skb->len);
  664. dev->stats.tx_bytes += skb->len;
  665. db->tx_pkt_cnt++;
  666. /* TX control: First packet immediately send, second packet queue */
  667. if (db->tx_pkt_cnt == 1) {
  668. /* Set TX length to DM9000 */
  669. iow(db, DM9000_TXPLL, skb->len & 0xff);
  670. iow(db, DM9000_TXPLH, (skb->len >> 8) & 0xff);
  671. /* Issue TX polling command */
  672. iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
  673. dev->trans_start = jiffies; /* save the time stamp */
  674. } else {
  675. /* Second packet */
  676. db->queue_pkt_len = skb->len;
  677. netif_stop_queue(dev);
  678. }
  679. spin_unlock_irqrestore(&db->lock, flags);
  680. /* free this SKB */
  681. dev_kfree_skb(skb);
  682. return 0;
  683. }
  684. static void
  685. dm9000_shutdown(struct net_device *dev)
  686. {
  687. board_info_t *db = (board_info_t *) dev->priv;
  688. /* RESET device */
  689. dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
  690. iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
  691. iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */
  692. iow(db, DM9000_RCR, 0x00); /* Disable RX */
  693. }
  694. /*
  695. * Stop the interface.
  696. * The interface is stopped when it is brought.
  697. */
  698. static int
  699. dm9000_stop(struct net_device *ndev)
  700. {
  701. board_info_t *db = (board_info_t *) ndev->priv;
  702. dm9000_dbg(db, 1, "entering %s\n", __func__);
  703. netif_stop_queue(ndev);
  704. netif_carrier_off(ndev);
  705. /* free interrupt */
  706. free_irq(ndev->irq, ndev);
  707. dm9000_shutdown(ndev);
  708. return 0;
  709. }
  710. /*
  711. * DM9000 interrupt handler
  712. * receive the packet to upper layer, free the transmitted packet
  713. */
  714. static void
  715. dm9000_tx_done(struct net_device *dev, board_info_t * db)
  716. {
  717. int tx_status = ior(db, DM9000_NSR); /* Got TX status */
  718. if (tx_status & (NSR_TX2END | NSR_TX1END)) {
  719. /* One packet sent complete */
  720. db->tx_pkt_cnt--;
  721. dev->stats.tx_packets++;
  722. /* Queue packet check & send */
  723. if (db->tx_pkt_cnt > 0) {
  724. iow(db, DM9000_TXPLL, db->queue_pkt_len & 0xff);
  725. iow(db, DM9000_TXPLH, (db->queue_pkt_len >> 8) & 0xff);
  726. iow(db, DM9000_TCR, TCR_TXREQ);
  727. dev->trans_start = jiffies;
  728. }
  729. netif_wake_queue(dev);
  730. }
  731. }
  732. static irqreturn_t
  733. dm9000_interrupt(int irq, void *dev_id)
  734. {
  735. struct net_device *dev = dev_id;
  736. board_info_t *db = (board_info_t *) dev->priv;
  737. int int_status;
  738. u8 reg_save;
  739. dm9000_dbg(db, 3, "entering %s\n", __func__);
  740. /* A real interrupt coming */
  741. spin_lock(&db->lock);
  742. /* Save previous register address */
  743. reg_save = readb(db->io_addr);
  744. /* Disable all interrupts */
  745. iow(db, DM9000_IMR, IMR_PAR);
  746. /* Got DM9000 interrupt status */
  747. int_status = ior(db, DM9000_ISR); /* Got ISR */
  748. iow(db, DM9000_ISR, int_status); /* Clear ISR status */
  749. /* Received the coming packet */
  750. if (int_status & ISR_PRS)
  751. dm9000_rx(dev);
  752. /* Trnasmit Interrupt check */
  753. if (int_status & ISR_PTS)
  754. dm9000_tx_done(dev, db);
  755. /* Re-enable interrupt mask */
  756. iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
  757. /* Restore previous register address */
  758. writeb(reg_save, db->io_addr);
  759. spin_unlock(&db->lock);
  760. return IRQ_HANDLED;
  761. }
  762. struct dm9000_rxhdr {
  763. u8 RxPktReady;
  764. u8 RxStatus;
  765. u16 RxLen;
  766. } __attribute__((__packed__));
  767. /*
  768. * Received a packet and pass to upper layer
  769. */
  770. static void
  771. dm9000_rx(struct net_device *dev)
  772. {
  773. board_info_t *db = (board_info_t *) dev->priv;
  774. struct dm9000_rxhdr rxhdr;
  775. struct sk_buff *skb;
  776. u8 rxbyte, *rdptr;
  777. bool GoodPacket;
  778. int RxLen;
  779. /* Check packet ready or not */
  780. do {
  781. ior(db, DM9000_MRCMDX); /* Dummy read */
  782. /* Get most updated data */
  783. rxbyte = readb(db->io_data);
  784. /* Status check: this byte must be 0 or 1 */
  785. if (rxbyte > DM9000_PKT_RDY) {
  786. dev_warn(db->dev, "status check fail: %d\n", rxbyte);
  787. iow(db, DM9000_RCR, 0x00); /* Stop Device */
  788. iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */
  789. return;
  790. }
  791. if (rxbyte != DM9000_PKT_RDY)
  792. return;
  793. /* A packet ready now & Get status/length */
  794. GoodPacket = true;
  795. writeb(DM9000_MRCMD, db->io_addr);
  796. (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));
  797. RxLen = le16_to_cpu(rxhdr.RxLen);
  798. /* Packet Status check */
  799. if (RxLen < 0x40) {
  800. GoodPacket = false;
  801. dev_dbg(db->dev, "Bad Packet received (runt)\n");
  802. }
  803. if (RxLen > DM9000_PKT_MAX) {
  804. dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen);
  805. }
  806. if (rxhdr.RxStatus & 0xbf) {
  807. GoodPacket = false;
  808. if (rxhdr.RxStatus & 0x01) {
  809. dev_dbg(db->dev, "fifo error\n");
  810. dev->stats.rx_fifo_errors++;
  811. }
  812. if (rxhdr.RxStatus & 0x02) {
  813. dev_dbg(db->dev, "crc error\n");
  814. dev->stats.rx_crc_errors++;
  815. }
  816. if (rxhdr.RxStatus & 0x80) {
  817. dev_dbg(db->dev, "length error\n");
  818. dev->stats.rx_length_errors++;
  819. }
  820. }
  821. /* Move data from DM9000 */
  822. if (GoodPacket
  823. && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) {
  824. skb_reserve(skb, 2);
  825. rdptr = (u8 *) skb_put(skb, RxLen - 4);
  826. /* Read received packet from RX SRAM */
  827. (db->inblk)(db->io_data, rdptr, RxLen);
  828. dev->stats.rx_bytes += RxLen;
  829. /* Pass to upper layer */
  830. skb->protocol = eth_type_trans(skb, dev);
  831. netif_rx(skb);
  832. dev->stats.rx_packets++;
  833. } else {
  834. /* need to dump the packet's data */
  835. (db->dumpblk)(db->io_data, RxLen);
  836. }
  837. } while (rxbyte == DM9000_PKT_RDY);
  838. }
  839. /*
  840. * Read a word data from EEPROM
  841. */
  842. static void
  843. dm9000_read_eeprom(board_info_t *db, int offset, u8 *to)
  844. {
  845. mutex_lock(&db->addr_lock);
  846. iow(db, DM9000_EPAR, offset);
  847. iow(db, DM9000_EPCR, EPCR_ERPRR);
  848. mdelay(8); /* according to the datasheet 200us should be enough,
  849. but it doesn't work */
  850. iow(db, DM9000_EPCR, 0x0);
  851. to[0] = ior(db, DM9000_EPDRL);
  852. to[1] = ior(db, DM9000_EPDRH);
  853. mutex_unlock(&db->addr_lock);
  854. }
  855. /*
  856. * Write a word data to SROM
  857. */
  858. static void
  859. dm9000_write_eeprom(board_info_t *db, int offset, u8 *data)
  860. {
  861. mutex_lock(&db->addr_lock);
  862. iow(db, DM9000_EPAR, offset);
  863. iow(db, DM9000_EPDRH, data[1]);
  864. iow(db, DM9000_EPDRL, data[0]);
  865. iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
  866. mdelay(8); /* same shit */
  867. iow(db, DM9000_EPCR, 0);
  868. mutex_unlock(&db->addr_lock);
  869. }
  870. #ifdef DM9000_PROGRAM_EEPROM
  871. /*
  872. * Only for development:
  873. * Here we write static data to the eeprom in case
  874. * we don't have valid content on a new board
  875. */
  876. static void
  877. program_eeprom(board_info_t * db)
  878. {
  879. u16 eeprom[] = { 0x0c00, 0x007f, 0x1300, /* MAC Address */
  880. 0x0000, /* Autoload: accept nothing */
  881. 0x0a46, 0x9000, /* Vendor / Product ID */
  882. 0x0000, /* pin control */
  883. 0x0000,
  884. }; /* Wake-up mode control */
  885. int i;
  886. for (i = 0; i < 8; i++)
  887. write_srom_word(db, i, eeprom[i]);
  888. }
  889. #endif
  890. /*
  891. * Calculate the CRC valude of the Rx packet
  892. * flag = 1 : return the reverse CRC (for the received packet CRC)
  893. * 0 : return the normal CRC (for Hash Table index)
  894. */
  895. static unsigned long
  896. cal_CRC(unsigned char *Data, unsigned int Len, u8 flag)
  897. {
  898. u32 crc = ether_crc_le(Len, Data);
  899. if (flag)
  900. return ~crc;
  901. return crc;
  902. }
  903. /*
  904. * Set DM9000 multicast address
  905. */
  906. static void
  907. dm9000_hash_table(struct net_device *dev)
  908. {
  909. board_info_t *db = (board_info_t *) dev->priv;
  910. struct dev_mc_list *mcptr = dev->mc_list;
  911. int mc_cnt = dev->mc_count;
  912. u32 hash_val;
  913. u16 i, oft, hash_table[4];
  914. unsigned long flags;
  915. dm9000_dbg(db, 1, "entering %s\n", __func__);
  916. spin_lock_irqsave(&db->lock,flags);
  917. for (i = 0, oft = 0x10; i < 6; i++, oft++)
  918. iow(db, oft, dev->dev_addr[i]);
  919. /* Clear Hash Table */
  920. for (i = 0; i < 4; i++)
  921. hash_table[i] = 0x0;
  922. /* broadcast address */
  923. hash_table[3] = 0x8000;
  924. /* the multicast address in Hash Table : 64 bits */
  925. for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
  926. hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
  927. hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
  928. }
  929. /* Write the hash table to MAC MD table */
  930. for (i = 0, oft = 0x16; i < 4; i++) {
  931. iow(db, oft++, hash_table[i] & 0xff);
  932. iow(db, oft++, (hash_table[i] >> 8) & 0xff);
  933. }
  934. spin_unlock_irqrestore(&db->lock,flags);
  935. }
  936. /*
  937. * Sleep, either by using msleep() or if we are suspending, then
  938. * use mdelay() to sleep.
  939. */
  940. static void dm9000_msleep(board_info_t *db, unsigned int ms)
  941. {
  942. if (db->in_suspend)
  943. mdelay(ms);
  944. else
  945. msleep(ms);
  946. }
  947. /*
  948. * Read a word from phyxcer
  949. */
  950. static int
  951. dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
  952. {
  953. board_info_t *db = (board_info_t *) dev->priv;
  954. unsigned long flags;
  955. unsigned int reg_save;
  956. int ret;
  957. mutex_lock(&db->addr_lock);
  958. spin_lock_irqsave(&db->lock,flags);
  959. /* Save previous register address */
  960. reg_save = readb(db->io_addr);
  961. /* Fill the phyxcer register into REG_0C */
  962. iow(db, DM9000_EPAR, DM9000_PHY | reg);
  963. iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */
  964. writeb(reg_save, db->io_addr);
  965. spin_unlock_irqrestore(&db->lock,flags);
  966. dm9000_msleep(db, 1); /* Wait read complete */
  967. spin_lock_irqsave(&db->lock,flags);
  968. reg_save = readb(db->io_addr);
  969. iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
  970. /* The read data keeps on REG_0D & REG_0E */
  971. ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
  972. /* restore the previous address */
  973. writeb(reg_save, db->io_addr);
  974. spin_unlock_irqrestore(&db->lock,flags);
  975. mutex_unlock(&db->addr_lock);
  976. return ret;
  977. }
  978. /*
  979. * Write a word to phyxcer
  980. */
  981. static void
  982. dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value)
  983. {
  984. board_info_t *db = (board_info_t *) dev->priv;
  985. unsigned long flags;
  986. unsigned long reg_save;
  987. mutex_lock(&db->addr_lock);
  988. spin_lock_irqsave(&db->lock,flags);
  989. /* Save previous register address */
  990. reg_save = readb(db->io_addr);
  991. /* Fill the phyxcer register into REG_0C */
  992. iow(db, DM9000_EPAR, DM9000_PHY | reg);
  993. /* Fill the written data into REG_0D & REG_0E */
  994. iow(db, DM9000_EPDRL, (value & 0xff));
  995. iow(db, DM9000_EPDRH, ((value >> 8) & 0xff));
  996. iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */
  997. writeb(reg_save, db->io_addr);
  998. spin_unlock_irqrestore(&db->lock, flags);
  999. dm9000_msleep(db, 1); /* Wait write complete */
  1000. spin_lock_irqsave(&db->lock,flags);
  1001. reg_save = readb(db->io_addr);
  1002. iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
  1003. /* restore the previous address */
  1004. writeb(reg_save, db->io_addr);
  1005. spin_unlock_irqrestore(&db->lock, flags);
  1006. mutex_unlock(&db->addr_lock);
  1007. }
  1008. static int
  1009. dm9000_drv_suspend(struct platform_device *dev, pm_message_t state)
  1010. {
  1011. struct net_device *ndev = platform_get_drvdata(dev);
  1012. board_info_t *db;
  1013. if (ndev) {
  1014. db = (board_info_t *) ndev->priv;
  1015. db->in_suspend = 1;
  1016. if (netif_running(ndev)) {
  1017. netif_device_detach(ndev);
  1018. dm9000_shutdown(ndev);
  1019. }
  1020. }
  1021. return 0;
  1022. }
  1023. static int
  1024. dm9000_drv_resume(struct platform_device *dev)
  1025. {
  1026. struct net_device *ndev = platform_get_drvdata(dev);
  1027. board_info_t *db = (board_info_t *) ndev->priv;
  1028. if (ndev) {
  1029. if (netif_running(ndev)) {
  1030. dm9000_reset(db);
  1031. dm9000_init_dm9000(ndev);
  1032. netif_device_attach(ndev);
  1033. }
  1034. db->in_suspend = 0;
  1035. }
  1036. return 0;
  1037. }
  1038. static int
  1039. dm9000_drv_remove(struct platform_device *pdev)
  1040. {
  1041. struct net_device *ndev = platform_get_drvdata(pdev);
  1042. platform_set_drvdata(pdev, NULL);
  1043. unregister_netdev(ndev);
  1044. dm9000_release_board(pdev, (board_info_t *) ndev->priv);
  1045. free_netdev(ndev); /* free device structure */
  1046. dev_dbg(&pdev->dev, "released and freed device\n");
  1047. return 0;
  1048. }
  1049. static struct platform_driver dm9000_driver = {
  1050. .driver = {
  1051. .name = "dm9000",
  1052. .owner = THIS_MODULE,
  1053. },
  1054. .probe = dm9000_probe,
  1055. .remove = dm9000_drv_remove,
  1056. .suspend = dm9000_drv_suspend,
  1057. .resume = dm9000_drv_resume,
  1058. };
  1059. static int __init
  1060. dm9000_init(void)
  1061. {
  1062. printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION);
  1063. return platform_driver_register(&dm9000_driver); /* search board and register */
  1064. }
  1065. static void __exit
  1066. dm9000_cleanup(void)
  1067. {
  1068. platform_driver_unregister(&dm9000_driver);
  1069. }
  1070. module_init(dm9000_init);
  1071. module_exit(dm9000_cleanup);
  1072. MODULE_AUTHOR("Sascha Hauer, Ben Dooks");
  1073. MODULE_DESCRIPTION("Davicom DM9000 network driver");
  1074. MODULE_LICENSE("GPL");