spi-pl022.c 68 KB

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  1. /*
  2. * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
  3. *
  4. * Copyright (C) 2008-2012 ST-Ericsson AB
  5. * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
  6. *
  7. * Author: Linus Walleij <linus.walleij@stericsson.com>
  8. *
  9. * Initial version inspired by:
  10. * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
  11. * Initial adoption to PL022 by:
  12. * Sachin Verma <sachin.verma@st.com>
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. */
  24. #include <linux/init.h>
  25. #include <linux/module.h>
  26. #include <linux/device.h>
  27. #include <linux/ioport.h>
  28. #include <linux/errno.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/spi/spi.h>
  31. #include <linux/delay.h>
  32. #include <linux/clk.h>
  33. #include <linux/err.h>
  34. #include <linux/amba/bus.h>
  35. #include <linux/amba/pl022.h>
  36. #include <linux/io.h>
  37. #include <linux/slab.h>
  38. #include <linux/dmaengine.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/scatterlist.h>
  41. #include <linux/pm_runtime.h>
  42. #include <linux/gpio.h>
  43. #include <linux/of_gpio.h>
  44. #include <linux/pinctrl/consumer.h>
  45. /*
  46. * This macro is used to define some register default values.
  47. * reg is masked with mask, the OR:ed with an (again masked)
  48. * val shifted sb steps to the left.
  49. */
  50. #define SSP_WRITE_BITS(reg, val, mask, sb) \
  51. ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
  52. /*
  53. * This macro is also used to define some default values.
  54. * It will just shift val by sb steps to the left and mask
  55. * the result with mask.
  56. */
  57. #define GEN_MASK_BITS(val, mask, sb) \
  58. (((val)<<(sb)) & (mask))
  59. #define DRIVE_TX 0
  60. #define DO_NOT_DRIVE_TX 1
  61. #define DO_NOT_QUEUE_DMA 0
  62. #define QUEUE_DMA 1
  63. #define RX_TRANSFER 1
  64. #define TX_TRANSFER 2
  65. /*
  66. * Macros to access SSP Registers with their offsets
  67. */
  68. #define SSP_CR0(r) (r + 0x000)
  69. #define SSP_CR1(r) (r + 0x004)
  70. #define SSP_DR(r) (r + 0x008)
  71. #define SSP_SR(r) (r + 0x00C)
  72. #define SSP_CPSR(r) (r + 0x010)
  73. #define SSP_IMSC(r) (r + 0x014)
  74. #define SSP_RIS(r) (r + 0x018)
  75. #define SSP_MIS(r) (r + 0x01C)
  76. #define SSP_ICR(r) (r + 0x020)
  77. #define SSP_DMACR(r) (r + 0x024)
  78. #define SSP_ITCR(r) (r + 0x080)
  79. #define SSP_ITIP(r) (r + 0x084)
  80. #define SSP_ITOP(r) (r + 0x088)
  81. #define SSP_TDR(r) (r + 0x08C)
  82. #define SSP_PID0(r) (r + 0xFE0)
  83. #define SSP_PID1(r) (r + 0xFE4)
  84. #define SSP_PID2(r) (r + 0xFE8)
  85. #define SSP_PID3(r) (r + 0xFEC)
  86. #define SSP_CID0(r) (r + 0xFF0)
  87. #define SSP_CID1(r) (r + 0xFF4)
  88. #define SSP_CID2(r) (r + 0xFF8)
  89. #define SSP_CID3(r) (r + 0xFFC)
  90. /*
  91. * SSP Control Register 0 - SSP_CR0
  92. */
  93. #define SSP_CR0_MASK_DSS (0x0FUL << 0)
  94. #define SSP_CR0_MASK_FRF (0x3UL << 4)
  95. #define SSP_CR0_MASK_SPO (0x1UL << 6)
  96. #define SSP_CR0_MASK_SPH (0x1UL << 7)
  97. #define SSP_CR0_MASK_SCR (0xFFUL << 8)
  98. /*
  99. * The ST version of this block moves som bits
  100. * in SSP_CR0 and extends it to 32 bits
  101. */
  102. #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
  103. #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
  104. #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
  105. #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
  106. /*
  107. * SSP Control Register 0 - SSP_CR1
  108. */
  109. #define SSP_CR1_MASK_LBM (0x1UL << 0)
  110. #define SSP_CR1_MASK_SSE (0x1UL << 1)
  111. #define SSP_CR1_MASK_MS (0x1UL << 2)
  112. #define SSP_CR1_MASK_SOD (0x1UL << 3)
  113. /*
  114. * The ST version of this block adds some bits
  115. * in SSP_CR1
  116. */
  117. #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
  118. #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
  119. #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
  120. #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
  121. #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
  122. /* This one is only in the PL023 variant */
  123. #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
  124. /*
  125. * SSP Status Register - SSP_SR
  126. */
  127. #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
  128. #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
  129. #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
  130. #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
  131. #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
  132. /*
  133. * SSP Clock Prescale Register - SSP_CPSR
  134. */
  135. #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
  136. /*
  137. * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
  138. */
  139. #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
  140. #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
  141. #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
  142. #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
  143. /*
  144. * SSP Raw Interrupt Status Register - SSP_RIS
  145. */
  146. /* Receive Overrun Raw Interrupt status */
  147. #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
  148. /* Receive Timeout Raw Interrupt status */
  149. #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
  150. /* Receive FIFO Raw Interrupt status */
  151. #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
  152. /* Transmit FIFO Raw Interrupt status */
  153. #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
  154. /*
  155. * SSP Masked Interrupt Status Register - SSP_MIS
  156. */
  157. /* Receive Overrun Masked Interrupt status */
  158. #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
  159. /* Receive Timeout Masked Interrupt status */
  160. #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
  161. /* Receive FIFO Masked Interrupt status */
  162. #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
  163. /* Transmit FIFO Masked Interrupt status */
  164. #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
  165. /*
  166. * SSP Interrupt Clear Register - SSP_ICR
  167. */
  168. /* Receive Overrun Raw Clear Interrupt bit */
  169. #define SSP_ICR_MASK_RORIC (0x1UL << 0)
  170. /* Receive Timeout Clear Interrupt bit */
  171. #define SSP_ICR_MASK_RTIC (0x1UL << 1)
  172. /*
  173. * SSP DMA Control Register - SSP_DMACR
  174. */
  175. /* Receive DMA Enable bit */
  176. #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
  177. /* Transmit DMA Enable bit */
  178. #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
  179. /*
  180. * SSP Integration Test control Register - SSP_ITCR
  181. */
  182. #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
  183. #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
  184. /*
  185. * SSP Integration Test Input Register - SSP_ITIP
  186. */
  187. #define ITIP_MASK_SSPRXD (0x1UL << 0)
  188. #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
  189. #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
  190. #define ITIP_MASK_RXDMAC (0x1UL << 3)
  191. #define ITIP_MASK_TXDMAC (0x1UL << 4)
  192. #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
  193. /*
  194. * SSP Integration Test output Register - SSP_ITOP
  195. */
  196. #define ITOP_MASK_SSPTXD (0x1UL << 0)
  197. #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
  198. #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
  199. #define ITOP_MASK_SSPOEn (0x1UL << 3)
  200. #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
  201. #define ITOP_MASK_RORINTR (0x1UL << 5)
  202. #define ITOP_MASK_RTINTR (0x1UL << 6)
  203. #define ITOP_MASK_RXINTR (0x1UL << 7)
  204. #define ITOP_MASK_TXINTR (0x1UL << 8)
  205. #define ITOP_MASK_INTR (0x1UL << 9)
  206. #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
  207. #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
  208. #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
  209. #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
  210. /*
  211. * SSP Test Data Register - SSP_TDR
  212. */
  213. #define TDR_MASK_TESTDATA (0xFFFFFFFF)
  214. /*
  215. * Message State
  216. * we use the spi_message.state (void *) pointer to
  217. * hold a single state value, that's why all this
  218. * (void *) casting is done here.
  219. */
  220. #define STATE_START ((void *) 0)
  221. #define STATE_RUNNING ((void *) 1)
  222. #define STATE_DONE ((void *) 2)
  223. #define STATE_ERROR ((void *) -1)
  224. /*
  225. * SSP State - Whether Enabled or Disabled
  226. */
  227. #define SSP_DISABLED (0)
  228. #define SSP_ENABLED (1)
  229. /*
  230. * SSP DMA State - Whether DMA Enabled or Disabled
  231. */
  232. #define SSP_DMA_DISABLED (0)
  233. #define SSP_DMA_ENABLED (1)
  234. /*
  235. * SSP Clock Defaults
  236. */
  237. #define SSP_DEFAULT_CLKRATE 0x2
  238. #define SSP_DEFAULT_PRESCALE 0x40
  239. /*
  240. * SSP Clock Parameter ranges
  241. */
  242. #define CPSDVR_MIN 0x02
  243. #define CPSDVR_MAX 0xFE
  244. #define SCR_MIN 0x00
  245. #define SCR_MAX 0xFF
  246. /*
  247. * SSP Interrupt related Macros
  248. */
  249. #define DEFAULT_SSP_REG_IMSC 0x0UL
  250. #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
  251. #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
  252. #define CLEAR_ALL_INTERRUPTS 0x3
  253. #define SPI_POLLING_TIMEOUT 1000
  254. /*
  255. * The type of reading going on on this chip
  256. */
  257. enum ssp_reading {
  258. READING_NULL,
  259. READING_U8,
  260. READING_U16,
  261. READING_U32
  262. };
  263. /**
  264. * The type of writing going on on this chip
  265. */
  266. enum ssp_writing {
  267. WRITING_NULL,
  268. WRITING_U8,
  269. WRITING_U16,
  270. WRITING_U32
  271. };
  272. /**
  273. * struct vendor_data - vendor-specific config parameters
  274. * for PL022 derivates
  275. * @fifodepth: depth of FIFOs (both)
  276. * @max_bpw: maximum number of bits per word
  277. * @unidir: supports unidirection transfers
  278. * @extended_cr: 32 bit wide control register 0 with extra
  279. * features and extra features in CR1 as found in the ST variants
  280. * @pl023: supports a subset of the ST extensions called "PL023"
  281. */
  282. struct vendor_data {
  283. int fifodepth;
  284. int max_bpw;
  285. bool unidir;
  286. bool extended_cr;
  287. bool pl023;
  288. bool loopback;
  289. };
  290. /**
  291. * struct pl022 - This is the private SSP driver data structure
  292. * @adev: AMBA device model hookup
  293. * @vendor: vendor data for the IP block
  294. * @phybase: the physical memory where the SSP device resides
  295. * @virtbase: the virtual memory where the SSP is mapped
  296. * @clk: outgoing clock "SPICLK" for the SPI bus
  297. * @master: SPI framework hookup
  298. * @master_info: controller-specific data from machine setup
  299. * @kworker: thread struct for message pump
  300. * @kworker_task: pointer to task for message pump kworker thread
  301. * @pump_messages: work struct for scheduling work to the message pump
  302. * @queue_lock: spinlock to syncronise access to message queue
  303. * @queue: message queue
  304. * @busy: message pump is busy
  305. * @running: message pump is running
  306. * @pump_transfers: Tasklet used in Interrupt Transfer mode
  307. * @cur_msg: Pointer to current spi_message being processed
  308. * @cur_transfer: Pointer to current spi_transfer
  309. * @cur_chip: pointer to current clients chip(assigned from controller_state)
  310. * @next_msg_cs_active: the next message in the queue has been examined
  311. * and it was found that it uses the same chip select as the previous
  312. * message, so we left it active after the previous transfer, and it's
  313. * active already.
  314. * @tx: current position in TX buffer to be read
  315. * @tx_end: end position in TX buffer to be read
  316. * @rx: current position in RX buffer to be written
  317. * @rx_end: end position in RX buffer to be written
  318. * @read: the type of read currently going on
  319. * @write: the type of write currently going on
  320. * @exp_fifo_level: expected FIFO level
  321. * @dma_rx_channel: optional channel for RX DMA
  322. * @dma_tx_channel: optional channel for TX DMA
  323. * @sgt_rx: scattertable for the RX transfer
  324. * @sgt_tx: scattertable for the TX transfer
  325. * @dummypage: a dummy page used for driving data on the bus with DMA
  326. * @cur_cs: current chip select (gpio)
  327. * @chipselects: list of chipselects (gpios)
  328. */
  329. struct pl022 {
  330. struct amba_device *adev;
  331. struct vendor_data *vendor;
  332. resource_size_t phybase;
  333. void __iomem *virtbase;
  334. struct clk *clk;
  335. struct spi_master *master;
  336. struct pl022_ssp_controller *master_info;
  337. /* Message per-transfer pump */
  338. struct tasklet_struct pump_transfers;
  339. struct spi_message *cur_msg;
  340. struct spi_transfer *cur_transfer;
  341. struct chip_data *cur_chip;
  342. bool next_msg_cs_active;
  343. void *tx;
  344. void *tx_end;
  345. void *rx;
  346. void *rx_end;
  347. enum ssp_reading read;
  348. enum ssp_writing write;
  349. u32 exp_fifo_level;
  350. enum ssp_rx_level_trig rx_lev_trig;
  351. enum ssp_tx_level_trig tx_lev_trig;
  352. /* DMA settings */
  353. #ifdef CONFIG_DMA_ENGINE
  354. struct dma_chan *dma_rx_channel;
  355. struct dma_chan *dma_tx_channel;
  356. struct sg_table sgt_rx;
  357. struct sg_table sgt_tx;
  358. char *dummypage;
  359. bool dma_running;
  360. #endif
  361. int cur_cs;
  362. int *chipselects;
  363. };
  364. /**
  365. * struct chip_data - To maintain runtime state of SSP for each client chip
  366. * @cr0: Value of control register CR0 of SSP - on later ST variants this
  367. * register is 32 bits wide rather than just 16
  368. * @cr1: Value of control register CR1 of SSP
  369. * @dmacr: Value of DMA control Register of SSP
  370. * @cpsr: Value of Clock prescale register
  371. * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
  372. * @enable_dma: Whether to enable DMA or not
  373. * @read: function ptr to be used to read when doing xfer for this chip
  374. * @write: function ptr to be used to write when doing xfer for this chip
  375. * @cs_control: chip select callback provided by chip
  376. * @xfer_type: polling/interrupt/DMA
  377. *
  378. * Runtime state of the SSP controller, maintained per chip,
  379. * This would be set according to the current message that would be served
  380. */
  381. struct chip_data {
  382. u32 cr0;
  383. u16 cr1;
  384. u16 dmacr;
  385. u16 cpsr;
  386. u8 n_bytes;
  387. bool enable_dma;
  388. enum ssp_reading read;
  389. enum ssp_writing write;
  390. void (*cs_control) (u32 command);
  391. int xfer_type;
  392. };
  393. /**
  394. * null_cs_control - Dummy chip select function
  395. * @command: select/delect the chip
  396. *
  397. * If no chip select function is provided by client this is used as dummy
  398. * chip select
  399. */
  400. static void null_cs_control(u32 command)
  401. {
  402. pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
  403. }
  404. static void pl022_cs_control(struct pl022 *pl022, u32 command)
  405. {
  406. if (gpio_is_valid(pl022->cur_cs))
  407. gpio_set_value(pl022->cur_cs, command);
  408. else
  409. pl022->cur_chip->cs_control(command);
  410. }
  411. /**
  412. * giveback - current spi_message is over, schedule next message and call
  413. * callback of this message. Assumes that caller already
  414. * set message->status; dma and pio irqs are blocked
  415. * @pl022: SSP driver private data structure
  416. */
  417. static void giveback(struct pl022 *pl022)
  418. {
  419. struct spi_transfer *last_transfer;
  420. pl022->next_msg_cs_active = false;
  421. last_transfer = list_entry(pl022->cur_msg->transfers.prev,
  422. struct spi_transfer,
  423. transfer_list);
  424. /* Delay if requested before any change in chip select */
  425. if (last_transfer->delay_usecs)
  426. /*
  427. * FIXME: This runs in interrupt context.
  428. * Is this really smart?
  429. */
  430. udelay(last_transfer->delay_usecs);
  431. if (!last_transfer->cs_change) {
  432. struct spi_message *next_msg;
  433. /*
  434. * cs_change was not set. We can keep the chip select
  435. * enabled if there is message in the queue and it is
  436. * for the same spi device.
  437. *
  438. * We cannot postpone this until pump_messages, because
  439. * after calling msg->complete (below) the driver that
  440. * sent the current message could be unloaded, which
  441. * could invalidate the cs_control() callback...
  442. */
  443. /* get a pointer to the next message, if any */
  444. next_msg = spi_get_next_queued_message(pl022->master);
  445. /*
  446. * see if the next and current messages point
  447. * to the same spi device.
  448. */
  449. if (next_msg && next_msg->spi != pl022->cur_msg->spi)
  450. next_msg = NULL;
  451. if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
  452. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  453. else
  454. pl022->next_msg_cs_active = true;
  455. }
  456. pl022->cur_msg = NULL;
  457. pl022->cur_transfer = NULL;
  458. pl022->cur_chip = NULL;
  459. spi_finalize_current_message(pl022->master);
  460. /* disable the SPI/SSP operation */
  461. writew((readw(SSP_CR1(pl022->virtbase)) &
  462. (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
  463. }
  464. /**
  465. * flush - flush the FIFO to reach a clean state
  466. * @pl022: SSP driver private data structure
  467. */
  468. static int flush(struct pl022 *pl022)
  469. {
  470. unsigned long limit = loops_per_jiffy << 1;
  471. dev_dbg(&pl022->adev->dev, "flush\n");
  472. do {
  473. while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
  474. readw(SSP_DR(pl022->virtbase));
  475. } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
  476. pl022->exp_fifo_level = 0;
  477. return limit;
  478. }
  479. /**
  480. * restore_state - Load configuration of current chip
  481. * @pl022: SSP driver private data structure
  482. */
  483. static void restore_state(struct pl022 *pl022)
  484. {
  485. struct chip_data *chip = pl022->cur_chip;
  486. if (pl022->vendor->extended_cr)
  487. writel(chip->cr0, SSP_CR0(pl022->virtbase));
  488. else
  489. writew(chip->cr0, SSP_CR0(pl022->virtbase));
  490. writew(chip->cr1, SSP_CR1(pl022->virtbase));
  491. writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
  492. writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
  493. writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
  494. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  495. }
  496. /*
  497. * Default SSP Register Values
  498. */
  499. #define DEFAULT_SSP_REG_CR0 ( \
  500. GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
  501. GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
  502. GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
  503. GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
  504. GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
  505. )
  506. /* ST versions have slightly different bit layout */
  507. #define DEFAULT_SSP_REG_CR0_ST ( \
  508. GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
  509. GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
  510. GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
  511. GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
  512. GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
  513. GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
  514. GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
  515. )
  516. /* The PL023 version is slightly different again */
  517. #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
  518. GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
  519. GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
  520. GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
  521. GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
  522. )
  523. #define DEFAULT_SSP_REG_CR1 ( \
  524. GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
  525. GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
  526. GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
  527. GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
  528. )
  529. /* ST versions extend this register to use all 16 bits */
  530. #define DEFAULT_SSP_REG_CR1_ST ( \
  531. DEFAULT_SSP_REG_CR1 | \
  532. GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
  533. GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
  534. GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
  535. GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
  536. GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
  537. )
  538. /*
  539. * The PL023 variant has further differences: no loopback mode, no microwire
  540. * support, and a new clock feedback delay setting.
  541. */
  542. #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
  543. GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
  544. GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
  545. GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
  546. GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
  547. GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
  548. GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
  549. GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
  550. GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
  551. )
  552. #define DEFAULT_SSP_REG_CPSR ( \
  553. GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
  554. )
  555. #define DEFAULT_SSP_REG_DMACR (\
  556. GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
  557. GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
  558. )
  559. /**
  560. * load_ssp_default_config - Load default configuration for SSP
  561. * @pl022: SSP driver private data structure
  562. */
  563. static void load_ssp_default_config(struct pl022 *pl022)
  564. {
  565. if (pl022->vendor->pl023) {
  566. writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
  567. writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
  568. } else if (pl022->vendor->extended_cr) {
  569. writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
  570. writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
  571. } else {
  572. writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
  573. writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
  574. }
  575. writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
  576. writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
  577. writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
  578. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  579. }
  580. /**
  581. * This will write to TX and read from RX according to the parameters
  582. * set in pl022.
  583. */
  584. static void readwriter(struct pl022 *pl022)
  585. {
  586. /*
  587. * The FIFO depth is different between primecell variants.
  588. * I believe filling in too much in the FIFO might cause
  589. * errons in 8bit wide transfers on ARM variants (just 8 words
  590. * FIFO, means only 8x8 = 64 bits in FIFO) at least.
  591. *
  592. * To prevent this issue, the TX FIFO is only filled to the
  593. * unused RX FIFO fill length, regardless of what the TX
  594. * FIFO status flag indicates.
  595. */
  596. dev_dbg(&pl022->adev->dev,
  597. "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
  598. __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
  599. /* Read as much as you can */
  600. while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
  601. && (pl022->rx < pl022->rx_end)) {
  602. switch (pl022->read) {
  603. case READING_NULL:
  604. readw(SSP_DR(pl022->virtbase));
  605. break;
  606. case READING_U8:
  607. *(u8 *) (pl022->rx) =
  608. readw(SSP_DR(pl022->virtbase)) & 0xFFU;
  609. break;
  610. case READING_U16:
  611. *(u16 *) (pl022->rx) =
  612. (u16) readw(SSP_DR(pl022->virtbase));
  613. break;
  614. case READING_U32:
  615. *(u32 *) (pl022->rx) =
  616. readl(SSP_DR(pl022->virtbase));
  617. break;
  618. }
  619. pl022->rx += (pl022->cur_chip->n_bytes);
  620. pl022->exp_fifo_level--;
  621. }
  622. /*
  623. * Write as much as possible up to the RX FIFO size
  624. */
  625. while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
  626. && (pl022->tx < pl022->tx_end)) {
  627. switch (pl022->write) {
  628. case WRITING_NULL:
  629. writew(0x0, SSP_DR(pl022->virtbase));
  630. break;
  631. case WRITING_U8:
  632. writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
  633. break;
  634. case WRITING_U16:
  635. writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
  636. break;
  637. case WRITING_U32:
  638. writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
  639. break;
  640. }
  641. pl022->tx += (pl022->cur_chip->n_bytes);
  642. pl022->exp_fifo_level++;
  643. /*
  644. * This inner reader takes care of things appearing in the RX
  645. * FIFO as we're transmitting. This will happen a lot since the
  646. * clock starts running when you put things into the TX FIFO,
  647. * and then things are continuously clocked into the RX FIFO.
  648. */
  649. while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
  650. && (pl022->rx < pl022->rx_end)) {
  651. switch (pl022->read) {
  652. case READING_NULL:
  653. readw(SSP_DR(pl022->virtbase));
  654. break;
  655. case READING_U8:
  656. *(u8 *) (pl022->rx) =
  657. readw(SSP_DR(pl022->virtbase)) & 0xFFU;
  658. break;
  659. case READING_U16:
  660. *(u16 *) (pl022->rx) =
  661. (u16) readw(SSP_DR(pl022->virtbase));
  662. break;
  663. case READING_U32:
  664. *(u32 *) (pl022->rx) =
  665. readl(SSP_DR(pl022->virtbase));
  666. break;
  667. }
  668. pl022->rx += (pl022->cur_chip->n_bytes);
  669. pl022->exp_fifo_level--;
  670. }
  671. }
  672. /*
  673. * When we exit here the TX FIFO should be full and the RX FIFO
  674. * should be empty
  675. */
  676. }
  677. /**
  678. * next_transfer - Move to the Next transfer in the current spi message
  679. * @pl022: SSP driver private data structure
  680. *
  681. * This function moves though the linked list of spi transfers in the
  682. * current spi message and returns with the state of current spi
  683. * message i.e whether its last transfer is done(STATE_DONE) or
  684. * Next transfer is ready(STATE_RUNNING)
  685. */
  686. static void *next_transfer(struct pl022 *pl022)
  687. {
  688. struct spi_message *msg = pl022->cur_msg;
  689. struct spi_transfer *trans = pl022->cur_transfer;
  690. /* Move to next transfer */
  691. if (trans->transfer_list.next != &msg->transfers) {
  692. pl022->cur_transfer =
  693. list_entry(trans->transfer_list.next,
  694. struct spi_transfer, transfer_list);
  695. return STATE_RUNNING;
  696. }
  697. return STATE_DONE;
  698. }
  699. /*
  700. * This DMA functionality is only compiled in if we have
  701. * access to the generic DMA devices/DMA engine.
  702. */
  703. #ifdef CONFIG_DMA_ENGINE
  704. static void unmap_free_dma_scatter(struct pl022 *pl022)
  705. {
  706. /* Unmap and free the SG tables */
  707. dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
  708. pl022->sgt_tx.nents, DMA_TO_DEVICE);
  709. dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
  710. pl022->sgt_rx.nents, DMA_FROM_DEVICE);
  711. sg_free_table(&pl022->sgt_rx);
  712. sg_free_table(&pl022->sgt_tx);
  713. }
  714. static void dma_callback(void *data)
  715. {
  716. struct pl022 *pl022 = data;
  717. struct spi_message *msg = pl022->cur_msg;
  718. BUG_ON(!pl022->sgt_rx.sgl);
  719. #ifdef VERBOSE_DEBUG
  720. /*
  721. * Optionally dump out buffers to inspect contents, this is
  722. * good if you want to convince yourself that the loopback
  723. * read/write contents are the same, when adopting to a new
  724. * DMA engine.
  725. */
  726. {
  727. struct scatterlist *sg;
  728. unsigned int i;
  729. dma_sync_sg_for_cpu(&pl022->adev->dev,
  730. pl022->sgt_rx.sgl,
  731. pl022->sgt_rx.nents,
  732. DMA_FROM_DEVICE);
  733. for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
  734. dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
  735. print_hex_dump(KERN_ERR, "SPI RX: ",
  736. DUMP_PREFIX_OFFSET,
  737. 16,
  738. 1,
  739. sg_virt(sg),
  740. sg_dma_len(sg),
  741. 1);
  742. }
  743. for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
  744. dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
  745. print_hex_dump(KERN_ERR, "SPI TX: ",
  746. DUMP_PREFIX_OFFSET,
  747. 16,
  748. 1,
  749. sg_virt(sg),
  750. sg_dma_len(sg),
  751. 1);
  752. }
  753. }
  754. #endif
  755. unmap_free_dma_scatter(pl022);
  756. /* Update total bytes transferred */
  757. msg->actual_length += pl022->cur_transfer->len;
  758. if (pl022->cur_transfer->cs_change)
  759. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  760. /* Move to next transfer */
  761. msg->state = next_transfer(pl022);
  762. tasklet_schedule(&pl022->pump_transfers);
  763. }
  764. static void setup_dma_scatter(struct pl022 *pl022,
  765. void *buffer,
  766. unsigned int length,
  767. struct sg_table *sgtab)
  768. {
  769. struct scatterlist *sg;
  770. int bytesleft = length;
  771. void *bufp = buffer;
  772. int mapbytes;
  773. int i;
  774. if (buffer) {
  775. for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
  776. /*
  777. * If there are less bytes left than what fits
  778. * in the current page (plus page alignment offset)
  779. * we just feed in this, else we stuff in as much
  780. * as we can.
  781. */
  782. if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
  783. mapbytes = bytesleft;
  784. else
  785. mapbytes = PAGE_SIZE - offset_in_page(bufp);
  786. sg_set_page(sg, virt_to_page(bufp),
  787. mapbytes, offset_in_page(bufp));
  788. bufp += mapbytes;
  789. bytesleft -= mapbytes;
  790. dev_dbg(&pl022->adev->dev,
  791. "set RX/TX target page @ %p, %d bytes, %d left\n",
  792. bufp, mapbytes, bytesleft);
  793. }
  794. } else {
  795. /* Map the dummy buffer on every page */
  796. for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
  797. if (bytesleft < PAGE_SIZE)
  798. mapbytes = bytesleft;
  799. else
  800. mapbytes = PAGE_SIZE;
  801. sg_set_page(sg, virt_to_page(pl022->dummypage),
  802. mapbytes, 0);
  803. bytesleft -= mapbytes;
  804. dev_dbg(&pl022->adev->dev,
  805. "set RX/TX to dummy page %d bytes, %d left\n",
  806. mapbytes, bytesleft);
  807. }
  808. }
  809. BUG_ON(bytesleft);
  810. }
  811. /**
  812. * configure_dma - configures the channels for the next transfer
  813. * @pl022: SSP driver's private data structure
  814. */
  815. static int configure_dma(struct pl022 *pl022)
  816. {
  817. struct dma_slave_config rx_conf = {
  818. .src_addr = SSP_DR(pl022->phybase),
  819. .direction = DMA_DEV_TO_MEM,
  820. .device_fc = false,
  821. };
  822. struct dma_slave_config tx_conf = {
  823. .dst_addr = SSP_DR(pl022->phybase),
  824. .direction = DMA_MEM_TO_DEV,
  825. .device_fc = false,
  826. };
  827. unsigned int pages;
  828. int ret;
  829. int rx_sglen, tx_sglen;
  830. struct dma_chan *rxchan = pl022->dma_rx_channel;
  831. struct dma_chan *txchan = pl022->dma_tx_channel;
  832. struct dma_async_tx_descriptor *rxdesc;
  833. struct dma_async_tx_descriptor *txdesc;
  834. /* Check that the channels are available */
  835. if (!rxchan || !txchan)
  836. return -ENODEV;
  837. /*
  838. * If supplied, the DMA burstsize should equal the FIFO trigger level.
  839. * Notice that the DMA engine uses one-to-one mapping. Since we can
  840. * not trigger on 2 elements this needs explicit mapping rather than
  841. * calculation.
  842. */
  843. switch (pl022->rx_lev_trig) {
  844. case SSP_RX_1_OR_MORE_ELEM:
  845. rx_conf.src_maxburst = 1;
  846. break;
  847. case SSP_RX_4_OR_MORE_ELEM:
  848. rx_conf.src_maxburst = 4;
  849. break;
  850. case SSP_RX_8_OR_MORE_ELEM:
  851. rx_conf.src_maxburst = 8;
  852. break;
  853. case SSP_RX_16_OR_MORE_ELEM:
  854. rx_conf.src_maxburst = 16;
  855. break;
  856. case SSP_RX_32_OR_MORE_ELEM:
  857. rx_conf.src_maxburst = 32;
  858. break;
  859. default:
  860. rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
  861. break;
  862. }
  863. switch (pl022->tx_lev_trig) {
  864. case SSP_TX_1_OR_MORE_EMPTY_LOC:
  865. tx_conf.dst_maxburst = 1;
  866. break;
  867. case SSP_TX_4_OR_MORE_EMPTY_LOC:
  868. tx_conf.dst_maxburst = 4;
  869. break;
  870. case SSP_TX_8_OR_MORE_EMPTY_LOC:
  871. tx_conf.dst_maxburst = 8;
  872. break;
  873. case SSP_TX_16_OR_MORE_EMPTY_LOC:
  874. tx_conf.dst_maxburst = 16;
  875. break;
  876. case SSP_TX_32_OR_MORE_EMPTY_LOC:
  877. tx_conf.dst_maxburst = 32;
  878. break;
  879. default:
  880. tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
  881. break;
  882. }
  883. switch (pl022->read) {
  884. case READING_NULL:
  885. /* Use the same as for writing */
  886. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
  887. break;
  888. case READING_U8:
  889. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  890. break;
  891. case READING_U16:
  892. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  893. break;
  894. case READING_U32:
  895. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  896. break;
  897. }
  898. switch (pl022->write) {
  899. case WRITING_NULL:
  900. /* Use the same as for reading */
  901. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
  902. break;
  903. case WRITING_U8:
  904. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  905. break;
  906. case WRITING_U16:
  907. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  908. break;
  909. case WRITING_U32:
  910. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  911. break;
  912. }
  913. /* SPI pecularity: we need to read and write the same width */
  914. if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  915. rx_conf.src_addr_width = tx_conf.dst_addr_width;
  916. if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  917. tx_conf.dst_addr_width = rx_conf.src_addr_width;
  918. BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
  919. dmaengine_slave_config(rxchan, &rx_conf);
  920. dmaengine_slave_config(txchan, &tx_conf);
  921. /* Create sglists for the transfers */
  922. pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
  923. dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
  924. ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
  925. if (ret)
  926. goto err_alloc_rx_sg;
  927. ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
  928. if (ret)
  929. goto err_alloc_tx_sg;
  930. /* Fill in the scatterlists for the RX+TX buffers */
  931. setup_dma_scatter(pl022, pl022->rx,
  932. pl022->cur_transfer->len, &pl022->sgt_rx);
  933. setup_dma_scatter(pl022, pl022->tx,
  934. pl022->cur_transfer->len, &pl022->sgt_tx);
  935. /* Map DMA buffers */
  936. rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
  937. pl022->sgt_rx.nents, DMA_FROM_DEVICE);
  938. if (!rx_sglen)
  939. goto err_rx_sgmap;
  940. tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
  941. pl022->sgt_tx.nents, DMA_TO_DEVICE);
  942. if (!tx_sglen)
  943. goto err_tx_sgmap;
  944. /* Send both scatterlists */
  945. rxdesc = dmaengine_prep_slave_sg(rxchan,
  946. pl022->sgt_rx.sgl,
  947. rx_sglen,
  948. DMA_DEV_TO_MEM,
  949. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  950. if (!rxdesc)
  951. goto err_rxdesc;
  952. txdesc = dmaengine_prep_slave_sg(txchan,
  953. pl022->sgt_tx.sgl,
  954. tx_sglen,
  955. DMA_MEM_TO_DEV,
  956. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  957. if (!txdesc)
  958. goto err_txdesc;
  959. /* Put the callback on the RX transfer only, that should finish last */
  960. rxdesc->callback = dma_callback;
  961. rxdesc->callback_param = pl022;
  962. /* Submit and fire RX and TX with TX last so we're ready to read! */
  963. dmaengine_submit(rxdesc);
  964. dmaengine_submit(txdesc);
  965. dma_async_issue_pending(rxchan);
  966. dma_async_issue_pending(txchan);
  967. pl022->dma_running = true;
  968. return 0;
  969. err_txdesc:
  970. dmaengine_terminate_all(txchan);
  971. err_rxdesc:
  972. dmaengine_terminate_all(rxchan);
  973. dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
  974. pl022->sgt_tx.nents, DMA_TO_DEVICE);
  975. err_tx_sgmap:
  976. dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
  977. pl022->sgt_tx.nents, DMA_FROM_DEVICE);
  978. err_rx_sgmap:
  979. sg_free_table(&pl022->sgt_tx);
  980. err_alloc_tx_sg:
  981. sg_free_table(&pl022->sgt_rx);
  982. err_alloc_rx_sg:
  983. return -ENOMEM;
  984. }
  985. static int pl022_dma_probe(struct pl022 *pl022)
  986. {
  987. dma_cap_mask_t mask;
  988. /* Try to acquire a generic DMA engine slave channel */
  989. dma_cap_zero(mask);
  990. dma_cap_set(DMA_SLAVE, mask);
  991. /*
  992. * We need both RX and TX channels to do DMA, else do none
  993. * of them.
  994. */
  995. pl022->dma_rx_channel = dma_request_channel(mask,
  996. pl022->master_info->dma_filter,
  997. pl022->master_info->dma_rx_param);
  998. if (!pl022->dma_rx_channel) {
  999. dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
  1000. goto err_no_rxchan;
  1001. }
  1002. pl022->dma_tx_channel = dma_request_channel(mask,
  1003. pl022->master_info->dma_filter,
  1004. pl022->master_info->dma_tx_param);
  1005. if (!pl022->dma_tx_channel) {
  1006. dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
  1007. goto err_no_txchan;
  1008. }
  1009. pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
  1010. if (!pl022->dummypage) {
  1011. dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
  1012. goto err_no_dummypage;
  1013. }
  1014. dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
  1015. dma_chan_name(pl022->dma_rx_channel),
  1016. dma_chan_name(pl022->dma_tx_channel));
  1017. return 0;
  1018. err_no_dummypage:
  1019. dma_release_channel(pl022->dma_tx_channel);
  1020. err_no_txchan:
  1021. dma_release_channel(pl022->dma_rx_channel);
  1022. pl022->dma_rx_channel = NULL;
  1023. err_no_rxchan:
  1024. dev_err(&pl022->adev->dev,
  1025. "Failed to work in dma mode, work without dma!\n");
  1026. return -ENODEV;
  1027. }
  1028. static int pl022_dma_autoprobe(struct pl022 *pl022)
  1029. {
  1030. struct device *dev = &pl022->adev->dev;
  1031. /* automatically configure DMA channels from platform, normally using DT */
  1032. pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx");
  1033. if (!pl022->dma_rx_channel)
  1034. goto err_no_rxchan;
  1035. pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx");
  1036. if (!pl022->dma_tx_channel)
  1037. goto err_no_txchan;
  1038. pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
  1039. if (!pl022->dummypage)
  1040. goto err_no_dummypage;
  1041. return 0;
  1042. err_no_dummypage:
  1043. dma_release_channel(pl022->dma_tx_channel);
  1044. pl022->dma_tx_channel = NULL;
  1045. err_no_txchan:
  1046. dma_release_channel(pl022->dma_rx_channel);
  1047. pl022->dma_rx_channel = NULL;
  1048. err_no_rxchan:
  1049. return -ENODEV;
  1050. }
  1051. static void terminate_dma(struct pl022 *pl022)
  1052. {
  1053. struct dma_chan *rxchan = pl022->dma_rx_channel;
  1054. struct dma_chan *txchan = pl022->dma_tx_channel;
  1055. dmaengine_terminate_all(rxchan);
  1056. dmaengine_terminate_all(txchan);
  1057. unmap_free_dma_scatter(pl022);
  1058. pl022->dma_running = false;
  1059. }
  1060. static void pl022_dma_remove(struct pl022 *pl022)
  1061. {
  1062. if (pl022->dma_running)
  1063. terminate_dma(pl022);
  1064. if (pl022->dma_tx_channel)
  1065. dma_release_channel(pl022->dma_tx_channel);
  1066. if (pl022->dma_rx_channel)
  1067. dma_release_channel(pl022->dma_rx_channel);
  1068. kfree(pl022->dummypage);
  1069. }
  1070. #else
  1071. static inline int configure_dma(struct pl022 *pl022)
  1072. {
  1073. return -ENODEV;
  1074. }
  1075. static inline int pl022_dma_autoprobe(struct pl022 *pl022)
  1076. {
  1077. return 0;
  1078. }
  1079. static inline int pl022_dma_probe(struct pl022 *pl022)
  1080. {
  1081. return 0;
  1082. }
  1083. static inline void pl022_dma_remove(struct pl022 *pl022)
  1084. {
  1085. }
  1086. #endif
  1087. /**
  1088. * pl022_interrupt_handler - Interrupt handler for SSP controller
  1089. *
  1090. * This function handles interrupts generated for an interrupt based transfer.
  1091. * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
  1092. * current message's state as STATE_ERROR and schedule the tasklet
  1093. * pump_transfers which will do the postprocessing of the current message by
  1094. * calling giveback(). Otherwise it reads data from RX FIFO till there is no
  1095. * more data, and writes data in TX FIFO till it is not full. If we complete
  1096. * the transfer we move to the next transfer and schedule the tasklet.
  1097. */
  1098. static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
  1099. {
  1100. struct pl022 *pl022 = dev_id;
  1101. struct spi_message *msg = pl022->cur_msg;
  1102. u16 irq_status = 0;
  1103. u16 flag = 0;
  1104. if (unlikely(!msg)) {
  1105. dev_err(&pl022->adev->dev,
  1106. "bad message state in interrupt handler");
  1107. /* Never fail */
  1108. return IRQ_HANDLED;
  1109. }
  1110. /* Read the Interrupt Status Register */
  1111. irq_status = readw(SSP_MIS(pl022->virtbase));
  1112. if (unlikely(!irq_status))
  1113. return IRQ_NONE;
  1114. /*
  1115. * This handles the FIFO interrupts, the timeout
  1116. * interrupts are flatly ignored, they cannot be
  1117. * trusted.
  1118. */
  1119. if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
  1120. /*
  1121. * Overrun interrupt - bail out since our Data has been
  1122. * corrupted
  1123. */
  1124. dev_err(&pl022->adev->dev, "FIFO overrun\n");
  1125. if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
  1126. dev_err(&pl022->adev->dev,
  1127. "RXFIFO is full\n");
  1128. if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
  1129. dev_err(&pl022->adev->dev,
  1130. "TXFIFO is full\n");
  1131. /*
  1132. * Disable and clear interrupts, disable SSP,
  1133. * mark message with bad status so it can be
  1134. * retried.
  1135. */
  1136. writew(DISABLE_ALL_INTERRUPTS,
  1137. SSP_IMSC(pl022->virtbase));
  1138. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  1139. writew((readw(SSP_CR1(pl022->virtbase)) &
  1140. (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
  1141. msg->state = STATE_ERROR;
  1142. /* Schedule message queue handler */
  1143. tasklet_schedule(&pl022->pump_transfers);
  1144. return IRQ_HANDLED;
  1145. }
  1146. readwriter(pl022);
  1147. if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
  1148. flag = 1;
  1149. /* Disable Transmit interrupt, enable receive interrupt */
  1150. writew((readw(SSP_IMSC(pl022->virtbase)) &
  1151. ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
  1152. SSP_IMSC(pl022->virtbase));
  1153. }
  1154. /*
  1155. * Since all transactions must write as much as shall be read,
  1156. * we can conclude the entire transaction once RX is complete.
  1157. * At this point, all TX will always be finished.
  1158. */
  1159. if (pl022->rx >= pl022->rx_end) {
  1160. writew(DISABLE_ALL_INTERRUPTS,
  1161. SSP_IMSC(pl022->virtbase));
  1162. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  1163. if (unlikely(pl022->rx > pl022->rx_end)) {
  1164. dev_warn(&pl022->adev->dev, "read %u surplus "
  1165. "bytes (did you request an odd "
  1166. "number of bytes on a 16bit bus?)\n",
  1167. (u32) (pl022->rx - pl022->rx_end));
  1168. }
  1169. /* Update total bytes transferred */
  1170. msg->actual_length += pl022->cur_transfer->len;
  1171. if (pl022->cur_transfer->cs_change)
  1172. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  1173. /* Move to next transfer */
  1174. msg->state = next_transfer(pl022);
  1175. tasklet_schedule(&pl022->pump_transfers);
  1176. return IRQ_HANDLED;
  1177. }
  1178. return IRQ_HANDLED;
  1179. }
  1180. /**
  1181. * This sets up the pointers to memory for the next message to
  1182. * send out on the SPI bus.
  1183. */
  1184. static int set_up_next_transfer(struct pl022 *pl022,
  1185. struct spi_transfer *transfer)
  1186. {
  1187. int residue;
  1188. /* Sanity check the message for this bus width */
  1189. residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
  1190. if (unlikely(residue != 0)) {
  1191. dev_err(&pl022->adev->dev,
  1192. "message of %u bytes to transmit but the current "
  1193. "chip bus has a data width of %u bytes!\n",
  1194. pl022->cur_transfer->len,
  1195. pl022->cur_chip->n_bytes);
  1196. dev_err(&pl022->adev->dev, "skipping this message\n");
  1197. return -EIO;
  1198. }
  1199. pl022->tx = (void *)transfer->tx_buf;
  1200. pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
  1201. pl022->rx = (void *)transfer->rx_buf;
  1202. pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
  1203. pl022->write =
  1204. pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
  1205. pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
  1206. return 0;
  1207. }
  1208. /**
  1209. * pump_transfers - Tasklet function which schedules next transfer
  1210. * when running in interrupt or DMA transfer mode.
  1211. * @data: SSP driver private data structure
  1212. *
  1213. */
  1214. static void pump_transfers(unsigned long data)
  1215. {
  1216. struct pl022 *pl022 = (struct pl022 *) data;
  1217. struct spi_message *message = NULL;
  1218. struct spi_transfer *transfer = NULL;
  1219. struct spi_transfer *previous = NULL;
  1220. /* Get current state information */
  1221. message = pl022->cur_msg;
  1222. transfer = pl022->cur_transfer;
  1223. /* Handle for abort */
  1224. if (message->state == STATE_ERROR) {
  1225. message->status = -EIO;
  1226. giveback(pl022);
  1227. return;
  1228. }
  1229. /* Handle end of message */
  1230. if (message->state == STATE_DONE) {
  1231. message->status = 0;
  1232. giveback(pl022);
  1233. return;
  1234. }
  1235. /* Delay if requested at end of transfer before CS change */
  1236. if (message->state == STATE_RUNNING) {
  1237. previous = list_entry(transfer->transfer_list.prev,
  1238. struct spi_transfer,
  1239. transfer_list);
  1240. if (previous->delay_usecs)
  1241. /*
  1242. * FIXME: This runs in interrupt context.
  1243. * Is this really smart?
  1244. */
  1245. udelay(previous->delay_usecs);
  1246. /* Reselect chip select only if cs_change was requested */
  1247. if (previous->cs_change)
  1248. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1249. } else {
  1250. /* STATE_START */
  1251. message->state = STATE_RUNNING;
  1252. }
  1253. if (set_up_next_transfer(pl022, transfer)) {
  1254. message->state = STATE_ERROR;
  1255. message->status = -EIO;
  1256. giveback(pl022);
  1257. return;
  1258. }
  1259. /* Flush the FIFOs and let's go! */
  1260. flush(pl022);
  1261. if (pl022->cur_chip->enable_dma) {
  1262. if (configure_dma(pl022)) {
  1263. dev_dbg(&pl022->adev->dev,
  1264. "configuration of DMA failed, fall back to interrupt mode\n");
  1265. goto err_config_dma;
  1266. }
  1267. return;
  1268. }
  1269. err_config_dma:
  1270. /* enable all interrupts except RX */
  1271. writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
  1272. }
  1273. static void do_interrupt_dma_transfer(struct pl022 *pl022)
  1274. {
  1275. /*
  1276. * Default is to enable all interrupts except RX -
  1277. * this will be enabled once TX is complete
  1278. */
  1279. u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM;
  1280. /* Enable target chip, if not already active */
  1281. if (!pl022->next_msg_cs_active)
  1282. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1283. if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
  1284. /* Error path */
  1285. pl022->cur_msg->state = STATE_ERROR;
  1286. pl022->cur_msg->status = -EIO;
  1287. giveback(pl022);
  1288. return;
  1289. }
  1290. /* If we're using DMA, set up DMA here */
  1291. if (pl022->cur_chip->enable_dma) {
  1292. /* Configure DMA transfer */
  1293. if (configure_dma(pl022)) {
  1294. dev_dbg(&pl022->adev->dev,
  1295. "configuration of DMA failed, fall back to interrupt mode\n");
  1296. goto err_config_dma;
  1297. }
  1298. /* Disable interrupts in DMA mode, IRQ from DMA controller */
  1299. irqflags = DISABLE_ALL_INTERRUPTS;
  1300. }
  1301. err_config_dma:
  1302. /* Enable SSP, turn on interrupts */
  1303. writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
  1304. SSP_CR1(pl022->virtbase));
  1305. writew(irqflags, SSP_IMSC(pl022->virtbase));
  1306. }
  1307. static void do_polling_transfer(struct pl022 *pl022)
  1308. {
  1309. struct spi_message *message = NULL;
  1310. struct spi_transfer *transfer = NULL;
  1311. struct spi_transfer *previous = NULL;
  1312. struct chip_data *chip;
  1313. unsigned long time, timeout;
  1314. chip = pl022->cur_chip;
  1315. message = pl022->cur_msg;
  1316. while (message->state != STATE_DONE) {
  1317. /* Handle for abort */
  1318. if (message->state == STATE_ERROR)
  1319. break;
  1320. transfer = pl022->cur_transfer;
  1321. /* Delay if requested at end of transfer */
  1322. if (message->state == STATE_RUNNING) {
  1323. previous =
  1324. list_entry(transfer->transfer_list.prev,
  1325. struct spi_transfer, transfer_list);
  1326. if (previous->delay_usecs)
  1327. udelay(previous->delay_usecs);
  1328. if (previous->cs_change)
  1329. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1330. } else {
  1331. /* STATE_START */
  1332. message->state = STATE_RUNNING;
  1333. if (!pl022->next_msg_cs_active)
  1334. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1335. }
  1336. /* Configuration Changing Per Transfer */
  1337. if (set_up_next_transfer(pl022, transfer)) {
  1338. /* Error path */
  1339. message->state = STATE_ERROR;
  1340. break;
  1341. }
  1342. /* Flush FIFOs and enable SSP */
  1343. flush(pl022);
  1344. writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
  1345. SSP_CR1(pl022->virtbase));
  1346. dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
  1347. timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
  1348. while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
  1349. time = jiffies;
  1350. readwriter(pl022);
  1351. if (time_after(time, timeout)) {
  1352. dev_warn(&pl022->adev->dev,
  1353. "%s: timeout!\n", __func__);
  1354. message->state = STATE_ERROR;
  1355. goto out;
  1356. }
  1357. cpu_relax();
  1358. }
  1359. /* Update total byte transferred */
  1360. message->actual_length += pl022->cur_transfer->len;
  1361. if (pl022->cur_transfer->cs_change)
  1362. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  1363. /* Move to next transfer */
  1364. message->state = next_transfer(pl022);
  1365. }
  1366. out:
  1367. /* Handle end of message */
  1368. if (message->state == STATE_DONE)
  1369. message->status = 0;
  1370. else
  1371. message->status = -EIO;
  1372. giveback(pl022);
  1373. return;
  1374. }
  1375. static int pl022_transfer_one_message(struct spi_master *master,
  1376. struct spi_message *msg)
  1377. {
  1378. struct pl022 *pl022 = spi_master_get_devdata(master);
  1379. /* Initial message state */
  1380. pl022->cur_msg = msg;
  1381. msg->state = STATE_START;
  1382. pl022->cur_transfer = list_entry(msg->transfers.next,
  1383. struct spi_transfer, transfer_list);
  1384. /* Setup the SPI using the per chip configuration */
  1385. pl022->cur_chip = spi_get_ctldata(msg->spi);
  1386. pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
  1387. restore_state(pl022);
  1388. flush(pl022);
  1389. if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
  1390. do_polling_transfer(pl022);
  1391. else
  1392. do_interrupt_dma_transfer(pl022);
  1393. return 0;
  1394. }
  1395. static int pl022_unprepare_transfer_hardware(struct spi_master *master)
  1396. {
  1397. struct pl022 *pl022 = spi_master_get_devdata(master);
  1398. /* nothing more to do - disable spi/ssp and power off */
  1399. writew((readw(SSP_CR1(pl022->virtbase)) &
  1400. (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
  1401. return 0;
  1402. }
  1403. static int verify_controller_parameters(struct pl022 *pl022,
  1404. struct pl022_config_chip const *chip_info)
  1405. {
  1406. if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
  1407. || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
  1408. dev_err(&pl022->adev->dev,
  1409. "interface is configured incorrectly\n");
  1410. return -EINVAL;
  1411. }
  1412. if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
  1413. (!pl022->vendor->unidir)) {
  1414. dev_err(&pl022->adev->dev,
  1415. "unidirectional mode not supported in this "
  1416. "hardware version\n");
  1417. return -EINVAL;
  1418. }
  1419. if ((chip_info->hierarchy != SSP_MASTER)
  1420. && (chip_info->hierarchy != SSP_SLAVE)) {
  1421. dev_err(&pl022->adev->dev,
  1422. "hierarchy is configured incorrectly\n");
  1423. return -EINVAL;
  1424. }
  1425. if ((chip_info->com_mode != INTERRUPT_TRANSFER)
  1426. && (chip_info->com_mode != DMA_TRANSFER)
  1427. && (chip_info->com_mode != POLLING_TRANSFER)) {
  1428. dev_err(&pl022->adev->dev,
  1429. "Communication mode is configured incorrectly\n");
  1430. return -EINVAL;
  1431. }
  1432. switch (chip_info->rx_lev_trig) {
  1433. case SSP_RX_1_OR_MORE_ELEM:
  1434. case SSP_RX_4_OR_MORE_ELEM:
  1435. case SSP_RX_8_OR_MORE_ELEM:
  1436. /* These are always OK, all variants can handle this */
  1437. break;
  1438. case SSP_RX_16_OR_MORE_ELEM:
  1439. if (pl022->vendor->fifodepth < 16) {
  1440. dev_err(&pl022->adev->dev,
  1441. "RX FIFO Trigger Level is configured incorrectly\n");
  1442. return -EINVAL;
  1443. }
  1444. break;
  1445. case SSP_RX_32_OR_MORE_ELEM:
  1446. if (pl022->vendor->fifodepth < 32) {
  1447. dev_err(&pl022->adev->dev,
  1448. "RX FIFO Trigger Level is configured incorrectly\n");
  1449. return -EINVAL;
  1450. }
  1451. break;
  1452. default:
  1453. dev_err(&pl022->adev->dev,
  1454. "RX FIFO Trigger Level is configured incorrectly\n");
  1455. return -EINVAL;
  1456. break;
  1457. }
  1458. switch (chip_info->tx_lev_trig) {
  1459. case SSP_TX_1_OR_MORE_EMPTY_LOC:
  1460. case SSP_TX_4_OR_MORE_EMPTY_LOC:
  1461. case SSP_TX_8_OR_MORE_EMPTY_LOC:
  1462. /* These are always OK, all variants can handle this */
  1463. break;
  1464. case SSP_TX_16_OR_MORE_EMPTY_LOC:
  1465. if (pl022->vendor->fifodepth < 16) {
  1466. dev_err(&pl022->adev->dev,
  1467. "TX FIFO Trigger Level is configured incorrectly\n");
  1468. return -EINVAL;
  1469. }
  1470. break;
  1471. case SSP_TX_32_OR_MORE_EMPTY_LOC:
  1472. if (pl022->vendor->fifodepth < 32) {
  1473. dev_err(&pl022->adev->dev,
  1474. "TX FIFO Trigger Level is configured incorrectly\n");
  1475. return -EINVAL;
  1476. }
  1477. break;
  1478. default:
  1479. dev_err(&pl022->adev->dev,
  1480. "TX FIFO Trigger Level is configured incorrectly\n");
  1481. return -EINVAL;
  1482. break;
  1483. }
  1484. if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
  1485. if ((chip_info->ctrl_len < SSP_BITS_4)
  1486. || (chip_info->ctrl_len > SSP_BITS_32)) {
  1487. dev_err(&pl022->adev->dev,
  1488. "CTRL LEN is configured incorrectly\n");
  1489. return -EINVAL;
  1490. }
  1491. if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
  1492. && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
  1493. dev_err(&pl022->adev->dev,
  1494. "Wait State is configured incorrectly\n");
  1495. return -EINVAL;
  1496. }
  1497. /* Half duplex is only available in the ST Micro version */
  1498. if (pl022->vendor->extended_cr) {
  1499. if ((chip_info->duplex !=
  1500. SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
  1501. && (chip_info->duplex !=
  1502. SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
  1503. dev_err(&pl022->adev->dev,
  1504. "Microwire duplex mode is configured incorrectly\n");
  1505. return -EINVAL;
  1506. }
  1507. } else {
  1508. if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
  1509. dev_err(&pl022->adev->dev,
  1510. "Microwire half duplex mode requested,"
  1511. " but this is only available in the"
  1512. " ST version of PL022\n");
  1513. return -EINVAL;
  1514. }
  1515. }
  1516. return 0;
  1517. }
  1518. static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
  1519. {
  1520. return rate / (cpsdvsr * (1 + scr));
  1521. }
  1522. static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
  1523. ssp_clock_params * clk_freq)
  1524. {
  1525. /* Lets calculate the frequency parameters */
  1526. u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
  1527. u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
  1528. best_scr = 0, tmp, found = 0;
  1529. rate = clk_get_rate(pl022->clk);
  1530. /* cpsdvscr = 2 & scr 0 */
  1531. max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
  1532. /* cpsdvsr = 254 & scr = 255 */
  1533. min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
  1534. if (freq > max_tclk)
  1535. dev_warn(&pl022->adev->dev,
  1536. "Max speed that can be programmed is %d Hz, you requested %d\n",
  1537. max_tclk, freq);
  1538. if (freq < min_tclk) {
  1539. dev_err(&pl022->adev->dev,
  1540. "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
  1541. freq, min_tclk);
  1542. return -EINVAL;
  1543. }
  1544. /*
  1545. * best_freq will give closest possible available rate (<= requested
  1546. * freq) for all values of scr & cpsdvsr.
  1547. */
  1548. while ((cpsdvsr <= CPSDVR_MAX) && !found) {
  1549. while (scr <= SCR_MAX) {
  1550. tmp = spi_rate(rate, cpsdvsr, scr);
  1551. if (tmp > freq) {
  1552. /* we need lower freq */
  1553. scr++;
  1554. continue;
  1555. }
  1556. /*
  1557. * If found exact value, mark found and break.
  1558. * If found more closer value, update and break.
  1559. */
  1560. if (tmp > best_freq) {
  1561. best_freq = tmp;
  1562. best_cpsdvsr = cpsdvsr;
  1563. best_scr = scr;
  1564. if (tmp == freq)
  1565. found = 1;
  1566. }
  1567. /*
  1568. * increased scr will give lower rates, which are not
  1569. * required
  1570. */
  1571. break;
  1572. }
  1573. cpsdvsr += 2;
  1574. scr = SCR_MIN;
  1575. }
  1576. WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
  1577. freq);
  1578. clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
  1579. clk_freq->scr = (u8) (best_scr & 0xFF);
  1580. dev_dbg(&pl022->adev->dev,
  1581. "SSP Target Frequency is: %u, Effective Frequency is %u\n",
  1582. freq, best_freq);
  1583. dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
  1584. clk_freq->cpsdvsr, clk_freq->scr);
  1585. return 0;
  1586. }
  1587. /*
  1588. * A piece of default chip info unless the platform
  1589. * supplies it.
  1590. */
  1591. static const struct pl022_config_chip pl022_default_chip_info = {
  1592. .com_mode = POLLING_TRANSFER,
  1593. .iface = SSP_INTERFACE_MOTOROLA_SPI,
  1594. .hierarchy = SSP_SLAVE,
  1595. .slave_tx_disable = DO_NOT_DRIVE_TX,
  1596. .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
  1597. .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
  1598. .ctrl_len = SSP_BITS_8,
  1599. .wait_state = SSP_MWIRE_WAIT_ZERO,
  1600. .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
  1601. .cs_control = null_cs_control,
  1602. };
  1603. /**
  1604. * pl022_setup - setup function registered to SPI master framework
  1605. * @spi: spi device which is requesting setup
  1606. *
  1607. * This function is registered to the SPI framework for this SPI master
  1608. * controller. If it is the first time when setup is called by this device,
  1609. * this function will initialize the runtime state for this chip and save
  1610. * the same in the device structure. Else it will update the runtime info
  1611. * with the updated chip info. Nothing is really being written to the
  1612. * controller hardware here, that is not done until the actual transfer
  1613. * commence.
  1614. */
  1615. static int pl022_setup(struct spi_device *spi)
  1616. {
  1617. struct pl022_config_chip const *chip_info;
  1618. struct pl022_config_chip chip_info_dt;
  1619. struct chip_data *chip;
  1620. struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
  1621. int status = 0;
  1622. struct pl022 *pl022 = spi_master_get_devdata(spi->master);
  1623. unsigned int bits = spi->bits_per_word;
  1624. u32 tmp;
  1625. struct device_node *np = spi->dev.of_node;
  1626. if (!spi->max_speed_hz)
  1627. return -EINVAL;
  1628. /* Get controller_state if one is supplied */
  1629. chip = spi_get_ctldata(spi);
  1630. if (chip == NULL) {
  1631. chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
  1632. if (!chip) {
  1633. dev_err(&spi->dev,
  1634. "cannot allocate controller state\n");
  1635. return -ENOMEM;
  1636. }
  1637. dev_dbg(&spi->dev,
  1638. "allocated memory for controller's runtime state\n");
  1639. }
  1640. /* Get controller data if one is supplied */
  1641. chip_info = spi->controller_data;
  1642. if (chip_info == NULL) {
  1643. if (np) {
  1644. chip_info_dt = pl022_default_chip_info;
  1645. chip_info_dt.hierarchy = SSP_MASTER;
  1646. of_property_read_u32(np, "pl022,interface",
  1647. &chip_info_dt.iface);
  1648. of_property_read_u32(np, "pl022,com-mode",
  1649. &chip_info_dt.com_mode);
  1650. of_property_read_u32(np, "pl022,rx-level-trig",
  1651. &chip_info_dt.rx_lev_trig);
  1652. of_property_read_u32(np, "pl022,tx-level-trig",
  1653. &chip_info_dt.tx_lev_trig);
  1654. of_property_read_u32(np, "pl022,ctrl-len",
  1655. &chip_info_dt.ctrl_len);
  1656. of_property_read_u32(np, "pl022,wait-state",
  1657. &chip_info_dt.wait_state);
  1658. of_property_read_u32(np, "pl022,duplex",
  1659. &chip_info_dt.duplex);
  1660. chip_info = &chip_info_dt;
  1661. } else {
  1662. chip_info = &pl022_default_chip_info;
  1663. /* spi_board_info.controller_data not is supplied */
  1664. dev_dbg(&spi->dev,
  1665. "using default controller_data settings\n");
  1666. }
  1667. } else
  1668. dev_dbg(&spi->dev,
  1669. "using user supplied controller_data settings\n");
  1670. /*
  1671. * We can override with custom divisors, else we use the board
  1672. * frequency setting
  1673. */
  1674. if ((0 == chip_info->clk_freq.cpsdvsr)
  1675. && (0 == chip_info->clk_freq.scr)) {
  1676. status = calculate_effective_freq(pl022,
  1677. spi->max_speed_hz,
  1678. &clk_freq);
  1679. if (status < 0)
  1680. goto err_config_params;
  1681. } else {
  1682. memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
  1683. if ((clk_freq.cpsdvsr % 2) != 0)
  1684. clk_freq.cpsdvsr =
  1685. clk_freq.cpsdvsr - 1;
  1686. }
  1687. if ((clk_freq.cpsdvsr < CPSDVR_MIN)
  1688. || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
  1689. status = -EINVAL;
  1690. dev_err(&spi->dev,
  1691. "cpsdvsr is configured incorrectly\n");
  1692. goto err_config_params;
  1693. }
  1694. status = verify_controller_parameters(pl022, chip_info);
  1695. if (status) {
  1696. dev_err(&spi->dev, "controller data is incorrect");
  1697. goto err_config_params;
  1698. }
  1699. pl022->rx_lev_trig = chip_info->rx_lev_trig;
  1700. pl022->tx_lev_trig = chip_info->tx_lev_trig;
  1701. /* Now set controller state based on controller data */
  1702. chip->xfer_type = chip_info->com_mode;
  1703. if (!chip_info->cs_control) {
  1704. chip->cs_control = null_cs_control;
  1705. if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
  1706. dev_warn(&spi->dev,
  1707. "invalid chip select\n");
  1708. } else
  1709. chip->cs_control = chip_info->cs_control;
  1710. /* Check bits per word with vendor specific range */
  1711. if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
  1712. status = -ENOTSUPP;
  1713. dev_err(&spi->dev, "illegal data size for this controller!\n");
  1714. dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
  1715. pl022->vendor->max_bpw);
  1716. goto err_config_params;
  1717. } else if (bits <= 8) {
  1718. dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
  1719. chip->n_bytes = 1;
  1720. chip->read = READING_U8;
  1721. chip->write = WRITING_U8;
  1722. } else if (bits <= 16) {
  1723. dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
  1724. chip->n_bytes = 2;
  1725. chip->read = READING_U16;
  1726. chip->write = WRITING_U16;
  1727. } else {
  1728. dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
  1729. chip->n_bytes = 4;
  1730. chip->read = READING_U32;
  1731. chip->write = WRITING_U32;
  1732. }
  1733. /* Now Initialize all register settings required for this chip */
  1734. chip->cr0 = 0;
  1735. chip->cr1 = 0;
  1736. chip->dmacr = 0;
  1737. chip->cpsr = 0;
  1738. if ((chip_info->com_mode == DMA_TRANSFER)
  1739. && ((pl022->master_info)->enable_dma)) {
  1740. chip->enable_dma = true;
  1741. dev_dbg(&spi->dev, "DMA mode set in controller state\n");
  1742. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
  1743. SSP_DMACR_MASK_RXDMAE, 0);
  1744. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
  1745. SSP_DMACR_MASK_TXDMAE, 1);
  1746. } else {
  1747. chip->enable_dma = false;
  1748. dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
  1749. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
  1750. SSP_DMACR_MASK_RXDMAE, 0);
  1751. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
  1752. SSP_DMACR_MASK_TXDMAE, 1);
  1753. }
  1754. chip->cpsr = clk_freq.cpsdvsr;
  1755. /* Special setup for the ST micro extended control registers */
  1756. if (pl022->vendor->extended_cr) {
  1757. u32 etx;
  1758. if (pl022->vendor->pl023) {
  1759. /* These bits are only in the PL023 */
  1760. SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
  1761. SSP_CR1_MASK_FBCLKDEL_ST, 13);
  1762. } else {
  1763. /* These bits are in the PL022 but not PL023 */
  1764. SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
  1765. SSP_CR0_MASK_HALFDUP_ST, 5);
  1766. SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
  1767. SSP_CR0_MASK_CSS_ST, 16);
  1768. SSP_WRITE_BITS(chip->cr0, chip_info->iface,
  1769. SSP_CR0_MASK_FRF_ST, 21);
  1770. SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
  1771. SSP_CR1_MASK_MWAIT_ST, 6);
  1772. }
  1773. SSP_WRITE_BITS(chip->cr0, bits - 1,
  1774. SSP_CR0_MASK_DSS_ST, 0);
  1775. if (spi->mode & SPI_LSB_FIRST) {
  1776. tmp = SSP_RX_LSB;
  1777. etx = SSP_TX_LSB;
  1778. } else {
  1779. tmp = SSP_RX_MSB;
  1780. etx = SSP_TX_MSB;
  1781. }
  1782. SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
  1783. SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
  1784. SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
  1785. SSP_CR1_MASK_RXIFLSEL_ST, 7);
  1786. SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
  1787. SSP_CR1_MASK_TXIFLSEL_ST, 10);
  1788. } else {
  1789. SSP_WRITE_BITS(chip->cr0, bits - 1,
  1790. SSP_CR0_MASK_DSS, 0);
  1791. SSP_WRITE_BITS(chip->cr0, chip_info->iface,
  1792. SSP_CR0_MASK_FRF, 4);
  1793. }
  1794. /* Stuff that is common for all versions */
  1795. if (spi->mode & SPI_CPOL)
  1796. tmp = SSP_CLK_POL_IDLE_HIGH;
  1797. else
  1798. tmp = SSP_CLK_POL_IDLE_LOW;
  1799. SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
  1800. if (spi->mode & SPI_CPHA)
  1801. tmp = SSP_CLK_SECOND_EDGE;
  1802. else
  1803. tmp = SSP_CLK_FIRST_EDGE;
  1804. SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
  1805. SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
  1806. /* Loopback is available on all versions except PL023 */
  1807. if (pl022->vendor->loopback) {
  1808. if (spi->mode & SPI_LOOP)
  1809. tmp = LOOPBACK_ENABLED;
  1810. else
  1811. tmp = LOOPBACK_DISABLED;
  1812. SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
  1813. }
  1814. SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
  1815. SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
  1816. SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
  1817. 3);
  1818. /* Save controller_state */
  1819. spi_set_ctldata(spi, chip);
  1820. return status;
  1821. err_config_params:
  1822. spi_set_ctldata(spi, NULL);
  1823. kfree(chip);
  1824. return status;
  1825. }
  1826. /**
  1827. * pl022_cleanup - cleanup function registered to SPI master framework
  1828. * @spi: spi device which is requesting cleanup
  1829. *
  1830. * This function is registered to the SPI framework for this SPI master
  1831. * controller. It will free the runtime state of chip.
  1832. */
  1833. static void pl022_cleanup(struct spi_device *spi)
  1834. {
  1835. struct chip_data *chip = spi_get_ctldata(spi);
  1836. spi_set_ctldata(spi, NULL);
  1837. kfree(chip);
  1838. }
  1839. static struct pl022_ssp_controller *
  1840. pl022_platform_data_dt_get(struct device *dev)
  1841. {
  1842. struct device_node *np = dev->of_node;
  1843. struct pl022_ssp_controller *pd;
  1844. u32 tmp;
  1845. if (!np) {
  1846. dev_err(dev, "no dt node defined\n");
  1847. return NULL;
  1848. }
  1849. pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
  1850. if (!pd) {
  1851. dev_err(dev, "cannot allocate platform data memory\n");
  1852. return NULL;
  1853. }
  1854. pd->bus_id = -1;
  1855. pd->enable_dma = 1;
  1856. of_property_read_u32(np, "num-cs", &tmp);
  1857. pd->num_chipselect = tmp;
  1858. of_property_read_u32(np, "pl022,autosuspend-delay",
  1859. &pd->autosuspend_delay);
  1860. pd->rt = of_property_read_bool(np, "pl022,rt");
  1861. return pd;
  1862. }
  1863. static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
  1864. {
  1865. struct device *dev = &adev->dev;
  1866. struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
  1867. struct spi_master *master;
  1868. struct pl022 *pl022 = NULL; /*Data for this driver */
  1869. struct device_node *np = adev->dev.of_node;
  1870. int status = 0, i, num_cs;
  1871. dev_info(&adev->dev,
  1872. "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
  1873. if (!platform_info && IS_ENABLED(CONFIG_OF))
  1874. platform_info = pl022_platform_data_dt_get(dev);
  1875. if (!platform_info) {
  1876. dev_err(dev, "probe: no platform data defined\n");
  1877. return -ENODEV;
  1878. }
  1879. if (platform_info->num_chipselect) {
  1880. num_cs = platform_info->num_chipselect;
  1881. } else {
  1882. dev_err(dev, "probe: no chip select defined\n");
  1883. return -ENODEV;
  1884. }
  1885. /* Allocate master with space for data */
  1886. master = spi_alloc_master(dev, sizeof(struct pl022));
  1887. if (master == NULL) {
  1888. dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
  1889. return -ENOMEM;
  1890. }
  1891. pl022 = spi_master_get_devdata(master);
  1892. pl022->master = master;
  1893. pl022->master_info = platform_info;
  1894. pl022->adev = adev;
  1895. pl022->vendor = id->data;
  1896. pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),
  1897. GFP_KERNEL);
  1898. pinctrl_pm_select_default_state(dev);
  1899. /*
  1900. * Bus Number Which has been Assigned to this SSP controller
  1901. * on this board
  1902. */
  1903. master->bus_num = platform_info->bus_id;
  1904. master->num_chipselect = num_cs;
  1905. master->cleanup = pl022_cleanup;
  1906. master->setup = pl022_setup;
  1907. master->auto_runtime_pm = true;
  1908. master->transfer_one_message = pl022_transfer_one_message;
  1909. master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
  1910. master->rt = platform_info->rt;
  1911. master->dev.of_node = dev->of_node;
  1912. if (platform_info->num_chipselect && platform_info->chipselects) {
  1913. for (i = 0; i < num_cs; i++)
  1914. pl022->chipselects[i] = platform_info->chipselects[i];
  1915. } else if (IS_ENABLED(CONFIG_OF)) {
  1916. for (i = 0; i < num_cs; i++) {
  1917. int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
  1918. if (cs_gpio == -EPROBE_DEFER) {
  1919. status = -EPROBE_DEFER;
  1920. goto err_no_gpio;
  1921. }
  1922. pl022->chipselects[i] = cs_gpio;
  1923. if (gpio_is_valid(cs_gpio)) {
  1924. if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
  1925. dev_err(&adev->dev,
  1926. "could not request %d gpio\n",
  1927. cs_gpio);
  1928. else if (gpio_direction_output(cs_gpio, 1))
  1929. dev_err(&adev->dev,
  1930. "could set gpio %d as output\n",
  1931. cs_gpio);
  1932. }
  1933. }
  1934. }
  1935. /*
  1936. * Supports mode 0-3, loopback, and active low CS. Transfers are
  1937. * always MS bit first on the original pl022.
  1938. */
  1939. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
  1940. if (pl022->vendor->extended_cr)
  1941. master->mode_bits |= SPI_LSB_FIRST;
  1942. dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
  1943. status = amba_request_regions(adev, NULL);
  1944. if (status)
  1945. goto err_no_ioregion;
  1946. pl022->phybase = adev->res.start;
  1947. pl022->virtbase = devm_ioremap(dev, adev->res.start,
  1948. resource_size(&adev->res));
  1949. if (pl022->virtbase == NULL) {
  1950. status = -ENOMEM;
  1951. goto err_no_ioremap;
  1952. }
  1953. printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
  1954. adev->res.start, pl022->virtbase);
  1955. pl022->clk = devm_clk_get(&adev->dev, NULL);
  1956. if (IS_ERR(pl022->clk)) {
  1957. status = PTR_ERR(pl022->clk);
  1958. dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
  1959. goto err_no_clk;
  1960. }
  1961. status = clk_prepare(pl022->clk);
  1962. if (status) {
  1963. dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n");
  1964. goto err_clk_prep;
  1965. }
  1966. status = clk_enable(pl022->clk);
  1967. if (status) {
  1968. dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
  1969. goto err_no_clk_en;
  1970. }
  1971. /* Initialize transfer pump */
  1972. tasklet_init(&pl022->pump_transfers, pump_transfers,
  1973. (unsigned long)pl022);
  1974. /* Disable SSP */
  1975. writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
  1976. SSP_CR1(pl022->virtbase));
  1977. load_ssp_default_config(pl022);
  1978. status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
  1979. 0, "pl022", pl022);
  1980. if (status < 0) {
  1981. dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
  1982. goto err_no_irq;
  1983. }
  1984. /* Get DMA channels, try autoconfiguration first */
  1985. status = pl022_dma_autoprobe(pl022);
  1986. /* If that failed, use channels from platform_info */
  1987. if (status == 0)
  1988. platform_info->enable_dma = 1;
  1989. else if (platform_info->enable_dma) {
  1990. status = pl022_dma_probe(pl022);
  1991. if (status != 0)
  1992. platform_info->enable_dma = 0;
  1993. }
  1994. /* Register with the SPI framework */
  1995. amba_set_drvdata(adev, pl022);
  1996. status = spi_register_master(master);
  1997. if (status != 0) {
  1998. dev_err(&adev->dev,
  1999. "probe - problem registering spi master\n");
  2000. goto err_spi_register;
  2001. }
  2002. dev_dbg(dev, "probe succeeded\n");
  2003. /* let runtime pm put suspend */
  2004. if (platform_info->autosuspend_delay > 0) {
  2005. dev_info(&adev->dev,
  2006. "will use autosuspend for runtime pm, delay %dms\n",
  2007. platform_info->autosuspend_delay);
  2008. pm_runtime_set_autosuspend_delay(dev,
  2009. platform_info->autosuspend_delay);
  2010. pm_runtime_use_autosuspend(dev);
  2011. }
  2012. pm_runtime_put(dev);
  2013. return 0;
  2014. err_spi_register:
  2015. if (platform_info->enable_dma)
  2016. pl022_dma_remove(pl022);
  2017. err_no_irq:
  2018. clk_disable(pl022->clk);
  2019. err_no_clk_en:
  2020. clk_unprepare(pl022->clk);
  2021. err_clk_prep:
  2022. err_no_clk:
  2023. err_no_ioremap:
  2024. amba_release_regions(adev);
  2025. err_no_ioregion:
  2026. err_no_gpio:
  2027. spi_master_put(master);
  2028. return status;
  2029. }
  2030. static int
  2031. pl022_remove(struct amba_device *adev)
  2032. {
  2033. struct pl022 *pl022 = amba_get_drvdata(adev);
  2034. if (!pl022)
  2035. return 0;
  2036. /*
  2037. * undo pm_runtime_put() in probe. I assume that we're not
  2038. * accessing the primecell here.
  2039. */
  2040. pm_runtime_get_noresume(&adev->dev);
  2041. load_ssp_default_config(pl022);
  2042. if (pl022->master_info->enable_dma)
  2043. pl022_dma_remove(pl022);
  2044. clk_disable(pl022->clk);
  2045. clk_unprepare(pl022->clk);
  2046. amba_release_regions(adev);
  2047. tasklet_disable(&pl022->pump_transfers);
  2048. spi_unregister_master(pl022->master);
  2049. amba_set_drvdata(adev, NULL);
  2050. return 0;
  2051. }
  2052. #if defined(CONFIG_SUSPEND) || defined(CONFIG_PM_RUNTIME)
  2053. /*
  2054. * These two functions are used from both suspend/resume and
  2055. * the runtime counterparts to handle external resources like
  2056. * clocks, pins and regulators when going to sleep.
  2057. */
  2058. static void pl022_suspend_resources(struct pl022 *pl022, bool runtime)
  2059. {
  2060. clk_disable(pl022->clk);
  2061. if (runtime)
  2062. pinctrl_pm_select_idle_state(&pl022->adev->dev);
  2063. else
  2064. pinctrl_pm_select_sleep_state(&pl022->adev->dev);
  2065. }
  2066. static void pl022_resume_resources(struct pl022 *pl022, bool runtime)
  2067. {
  2068. /* First go to the default state */
  2069. pinctrl_pm_select_default_state(&pl022->adev->dev);
  2070. if (!runtime)
  2071. /* Then let's idle the pins until the next transfer happens */
  2072. pinctrl_pm_select_idle_state(&pl022->adev->dev);
  2073. clk_enable(pl022->clk);
  2074. }
  2075. #endif
  2076. #ifdef CONFIG_SUSPEND
  2077. static int pl022_suspend(struct device *dev)
  2078. {
  2079. struct pl022 *pl022 = dev_get_drvdata(dev);
  2080. int ret;
  2081. ret = spi_master_suspend(pl022->master);
  2082. if (ret) {
  2083. dev_warn(dev, "cannot suspend master\n");
  2084. return ret;
  2085. }
  2086. pm_runtime_get_sync(dev);
  2087. pl022_suspend_resources(pl022, false);
  2088. dev_dbg(dev, "suspended\n");
  2089. return 0;
  2090. }
  2091. static int pl022_resume(struct device *dev)
  2092. {
  2093. struct pl022 *pl022 = dev_get_drvdata(dev);
  2094. int ret;
  2095. pl022_resume_resources(pl022, false);
  2096. pm_runtime_put(dev);
  2097. /* Start the queue running */
  2098. ret = spi_master_resume(pl022->master);
  2099. if (ret)
  2100. dev_err(dev, "problem starting queue (%d)\n", ret);
  2101. else
  2102. dev_dbg(dev, "resumed\n");
  2103. return ret;
  2104. }
  2105. #endif /* CONFIG_PM */
  2106. #ifdef CONFIG_PM_RUNTIME
  2107. static int pl022_runtime_suspend(struct device *dev)
  2108. {
  2109. struct pl022 *pl022 = dev_get_drvdata(dev);
  2110. pl022_suspend_resources(pl022, true);
  2111. return 0;
  2112. }
  2113. static int pl022_runtime_resume(struct device *dev)
  2114. {
  2115. struct pl022 *pl022 = dev_get_drvdata(dev);
  2116. pl022_resume_resources(pl022, true);
  2117. return 0;
  2118. }
  2119. #endif
  2120. static const struct dev_pm_ops pl022_dev_pm_ops = {
  2121. SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
  2122. SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
  2123. };
  2124. static struct vendor_data vendor_arm = {
  2125. .fifodepth = 8,
  2126. .max_bpw = 16,
  2127. .unidir = false,
  2128. .extended_cr = false,
  2129. .pl023 = false,
  2130. .loopback = true,
  2131. };
  2132. static struct vendor_data vendor_st = {
  2133. .fifodepth = 32,
  2134. .max_bpw = 32,
  2135. .unidir = false,
  2136. .extended_cr = true,
  2137. .pl023 = false,
  2138. .loopback = true,
  2139. };
  2140. static struct vendor_data vendor_st_pl023 = {
  2141. .fifodepth = 32,
  2142. .max_bpw = 32,
  2143. .unidir = false,
  2144. .extended_cr = true,
  2145. .pl023 = true,
  2146. .loopback = false,
  2147. };
  2148. static struct amba_id pl022_ids[] = {
  2149. {
  2150. /*
  2151. * ARM PL022 variant, this has a 16bit wide
  2152. * and 8 locations deep TX/RX FIFO
  2153. */
  2154. .id = 0x00041022,
  2155. .mask = 0x000fffff,
  2156. .data = &vendor_arm,
  2157. },
  2158. {
  2159. /*
  2160. * ST Micro derivative, this has 32bit wide
  2161. * and 32 locations deep TX/RX FIFO
  2162. */
  2163. .id = 0x01080022,
  2164. .mask = 0xffffffff,
  2165. .data = &vendor_st,
  2166. },
  2167. {
  2168. /*
  2169. * ST-Ericsson derivative "PL023" (this is not
  2170. * an official ARM number), this is a PL022 SSP block
  2171. * stripped to SPI mode only, it has 32bit wide
  2172. * and 32 locations deep TX/RX FIFO but no extended
  2173. * CR0/CR1 register
  2174. */
  2175. .id = 0x00080023,
  2176. .mask = 0xffffffff,
  2177. .data = &vendor_st_pl023,
  2178. },
  2179. { 0, 0 },
  2180. };
  2181. MODULE_DEVICE_TABLE(amba, pl022_ids);
  2182. static struct amba_driver pl022_driver = {
  2183. .drv = {
  2184. .name = "ssp-pl022",
  2185. .pm = &pl022_dev_pm_ops,
  2186. },
  2187. .id_table = pl022_ids,
  2188. .probe = pl022_probe,
  2189. .remove = pl022_remove,
  2190. };
  2191. static int __init pl022_init(void)
  2192. {
  2193. return amba_driver_register(&pl022_driver);
  2194. }
  2195. subsys_initcall(pl022_init);
  2196. static void __exit pl022_exit(void)
  2197. {
  2198. amba_driver_unregister(&pl022_driver);
  2199. }
  2200. module_exit(pl022_exit);
  2201. MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
  2202. MODULE_DESCRIPTION("PL022 SSP Controller Driver");
  2203. MODULE_LICENSE("GPL");