dmar.h 5.0 KB

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  1. /*
  2. * Copyright (c) 2006, Intel Corporation.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along with
  14. * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15. * Place - Suite 330, Boston, MA 02111-1307 USA.
  16. *
  17. * Copyright (C) Ashok Raj <ashok.raj@intel.com>
  18. * Copyright (C) Shaohua Li <shaohua.li@intel.com>
  19. */
  20. #ifndef __DMAR_H__
  21. #define __DMAR_H__
  22. #include <linux/acpi.h>
  23. #include <linux/types.h>
  24. #include <linux/msi.h>
  25. #include <linux/irqreturn.h>
  26. struct intel_iommu;
  27. #if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
  28. struct dmar_drhd_unit {
  29. struct list_head list; /* list of drhd units */
  30. struct acpi_dmar_header *hdr; /* ACPI header */
  31. u64 reg_base_addr; /* register base address*/
  32. struct pci_dev **devices; /* target device array */
  33. int devices_cnt; /* target device count */
  34. u8 ignored:1; /* ignore drhd */
  35. u8 include_all:1;
  36. struct intel_iommu *iommu;
  37. };
  38. extern struct list_head dmar_drhd_units;
  39. #define for_each_drhd_unit(drhd) \
  40. list_for_each_entry(drhd, &dmar_drhd_units, list)
  41. extern int dmar_table_init(void);
  42. extern int dmar_dev_scope_init(void);
  43. /* Intel IOMMU detection */
  44. extern void detect_intel_iommu(void);
  45. extern int enable_drhd_fault_handling(void);
  46. extern int parse_ioapics_under_ir(void);
  47. extern int alloc_iommu(struct dmar_drhd_unit *);
  48. #else
  49. static inline void detect_intel_iommu(void)
  50. {
  51. return;
  52. }
  53. static inline int dmar_table_init(void)
  54. {
  55. return -ENODEV;
  56. }
  57. static inline int enable_drhd_fault_handling(void)
  58. {
  59. return -1;
  60. }
  61. #endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
  62. struct irte {
  63. union {
  64. struct {
  65. __u64 present : 1,
  66. fpd : 1,
  67. dst_mode : 1,
  68. redir_hint : 1,
  69. trigger_mode : 1,
  70. dlvry_mode : 3,
  71. avail : 4,
  72. __reserved_1 : 4,
  73. vector : 8,
  74. __reserved_2 : 8,
  75. dest_id : 32;
  76. };
  77. __u64 low;
  78. };
  79. union {
  80. struct {
  81. __u64 sid : 16,
  82. sq : 2,
  83. svt : 2,
  84. __reserved_3 : 44;
  85. };
  86. __u64 high;
  87. };
  88. };
  89. #ifdef CONFIG_INTR_REMAP
  90. extern int intr_remapping_enabled;
  91. extern int enable_intr_remapping(int);
  92. extern int get_irte(int irq, struct irte *entry);
  93. extern int modify_irte(int irq, struct irte *irte_modified);
  94. extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
  95. extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
  96. u16 sub_handle);
  97. extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
  98. extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index);
  99. extern int flush_irte(int irq);
  100. extern int free_irte(int irq);
  101. extern int irq_remapped(int irq);
  102. extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
  103. extern struct intel_iommu *map_ioapic_to_ir(int apic);
  104. #else
  105. static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
  106. {
  107. return -1;
  108. }
  109. static inline int modify_irte(int irq, struct irte *irte_modified)
  110. {
  111. return -1;
  112. }
  113. static inline int free_irte(int irq)
  114. {
  115. return -1;
  116. }
  117. static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
  118. {
  119. return -1;
  120. }
  121. static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
  122. u16 sub_handle)
  123. {
  124. return -1;
  125. }
  126. static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
  127. {
  128. return NULL;
  129. }
  130. static inline struct intel_iommu *map_ioapic_to_ir(int apic)
  131. {
  132. return NULL;
  133. }
  134. #define irq_remapped(irq) (0)
  135. #define enable_intr_remapping(mode) (-1)
  136. #define intr_remapping_enabled (0)
  137. #endif
  138. /* Can't use the common MSI interrupt functions
  139. * since DMAR is not a pci device
  140. */
  141. extern void dmar_msi_unmask(unsigned int irq);
  142. extern void dmar_msi_mask(unsigned int irq);
  143. extern void dmar_msi_read(int irq, struct msi_msg *msg);
  144. extern void dmar_msi_write(int irq, struct msi_msg *msg);
  145. extern int dmar_set_interrupt(struct intel_iommu *iommu);
  146. extern irqreturn_t dmar_fault(int irq, void *dev_id);
  147. extern int arch_setup_dmar_msi(unsigned int irq);
  148. #ifdef CONFIG_DMAR
  149. extern int iommu_detected, no_iommu;
  150. extern struct list_head dmar_rmrr_units;
  151. struct dmar_rmrr_unit {
  152. struct list_head list; /* list of rmrr units */
  153. struct acpi_dmar_header *hdr; /* ACPI header */
  154. u64 base_address; /* reserved base address*/
  155. u64 end_address; /* reserved end address */
  156. struct pci_dev **devices; /* target devices */
  157. int devices_cnt; /* target device count */
  158. };
  159. #define for_each_rmrr_units(rmrr) \
  160. list_for_each_entry(rmrr, &dmar_rmrr_units, list)
  161. /* Intel DMAR initialization functions */
  162. extern int intel_iommu_init(void);
  163. #else
  164. static inline int intel_iommu_init(void)
  165. {
  166. #ifdef CONFIG_INTR_REMAP
  167. return dmar_dev_scope_init();
  168. #else
  169. return -ENODEV;
  170. #endif
  171. }
  172. #endif /* !CONFIG_DMAR */
  173. #endif /* __DMAR_H__ */