netxen_nic_init.c 39 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. #define NETXEN_MAX_CRB_XFORM 60
  43. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  44. #define NETXEN_ADDR_ERROR (0xffffffff)
  45. #define crb_addr_transform(name) \
  46. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  47. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  48. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  49. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  50. uint32_t ctx, uint32_t ringid);
  51. #if 0
  52. static void netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  53. unsigned long off, int *data)
  54. {
  55. void __iomem *addr = pci_base_offset(adapter, off);
  56. writel(*data, addr);
  57. }
  58. #endif /* 0 */
  59. static void crb_addr_transform_setup(void)
  60. {
  61. crb_addr_transform(XDMA);
  62. crb_addr_transform(TIMR);
  63. crb_addr_transform(SRE);
  64. crb_addr_transform(SQN3);
  65. crb_addr_transform(SQN2);
  66. crb_addr_transform(SQN1);
  67. crb_addr_transform(SQN0);
  68. crb_addr_transform(SQS3);
  69. crb_addr_transform(SQS2);
  70. crb_addr_transform(SQS1);
  71. crb_addr_transform(SQS0);
  72. crb_addr_transform(RPMX7);
  73. crb_addr_transform(RPMX6);
  74. crb_addr_transform(RPMX5);
  75. crb_addr_transform(RPMX4);
  76. crb_addr_transform(RPMX3);
  77. crb_addr_transform(RPMX2);
  78. crb_addr_transform(RPMX1);
  79. crb_addr_transform(RPMX0);
  80. crb_addr_transform(ROMUSB);
  81. crb_addr_transform(SN);
  82. crb_addr_transform(QMN);
  83. crb_addr_transform(QMS);
  84. crb_addr_transform(PGNI);
  85. crb_addr_transform(PGND);
  86. crb_addr_transform(PGN3);
  87. crb_addr_transform(PGN2);
  88. crb_addr_transform(PGN1);
  89. crb_addr_transform(PGN0);
  90. crb_addr_transform(PGSI);
  91. crb_addr_transform(PGSD);
  92. crb_addr_transform(PGS3);
  93. crb_addr_transform(PGS2);
  94. crb_addr_transform(PGS1);
  95. crb_addr_transform(PGS0);
  96. crb_addr_transform(PS);
  97. crb_addr_transform(PH);
  98. crb_addr_transform(NIU);
  99. crb_addr_transform(I2Q);
  100. crb_addr_transform(EG);
  101. crb_addr_transform(MN);
  102. crb_addr_transform(MS);
  103. crb_addr_transform(CAS2);
  104. crb_addr_transform(CAS1);
  105. crb_addr_transform(CAS0);
  106. crb_addr_transform(CAM);
  107. crb_addr_transform(C2C1);
  108. crb_addr_transform(C2C0);
  109. crb_addr_transform(SMB);
  110. crb_addr_transform(OCM0);
  111. crb_addr_transform(I2C0);
  112. }
  113. int netxen_init_firmware(struct netxen_adapter *adapter)
  114. {
  115. u32 state = 0, loops = 0, err = 0;
  116. /* Window 1 call */
  117. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  118. if (state == PHAN_INITIALIZE_ACK)
  119. return 0;
  120. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  121. msleep(1);
  122. /* Window 1 call */
  123. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  124. loops++;
  125. }
  126. if (loops >= 2000) {
  127. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  128. state);
  129. err = -EIO;
  130. return err;
  131. }
  132. /* Window 1 call */
  133. adapter->pci_write_normalize(adapter,
  134. CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  135. adapter->pci_write_normalize(adapter,
  136. CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  137. adapter->pci_write_normalize(adapter,
  138. CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  139. adapter->pci_write_normalize(adapter,
  140. CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  141. return err;
  142. }
  143. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  144. {
  145. struct netxen_recv_context *recv_ctx;
  146. struct netxen_rcv_desc_ctx *rcv_desc;
  147. struct netxen_rx_buffer *rx_buf;
  148. int i, ctxid, ring;
  149. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  150. recv_ctx = &adapter->recv_ctx[ctxid];
  151. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  152. rcv_desc = &recv_ctx->rcv_desc[ring];
  153. for (i = 0; i < rcv_desc->max_rx_desc_count; ++i) {
  154. rx_buf = &(rcv_desc->rx_buf_arr[i]);
  155. if (rx_buf->state == NETXEN_BUFFER_FREE)
  156. continue;
  157. pci_unmap_single(adapter->pdev,
  158. rx_buf->dma,
  159. rcv_desc->dma_size,
  160. PCI_DMA_FROMDEVICE);
  161. if (rx_buf->skb != NULL)
  162. dev_kfree_skb_any(rx_buf->skb);
  163. }
  164. }
  165. }
  166. }
  167. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  168. {
  169. struct netxen_cmd_buffer *cmd_buf;
  170. struct netxen_skb_frag *buffrag;
  171. int i, j;
  172. cmd_buf = adapter->cmd_buf_arr;
  173. for (i = 0; i < adapter->max_tx_desc_count; i++) {
  174. buffrag = cmd_buf->frag_array;
  175. if (buffrag->dma) {
  176. pci_unmap_single(adapter->pdev, buffrag->dma,
  177. buffrag->length, PCI_DMA_TODEVICE);
  178. buffrag->dma = 0ULL;
  179. }
  180. for (j = 0; j < cmd_buf->frag_count; j++) {
  181. buffrag++;
  182. if (buffrag->dma) {
  183. pci_unmap_page(adapter->pdev, buffrag->dma,
  184. buffrag->length,
  185. PCI_DMA_TODEVICE);
  186. buffrag->dma = 0ULL;
  187. }
  188. }
  189. /* Free the skb we received in netxen_nic_xmit_frame */
  190. if (cmd_buf->skb) {
  191. dev_kfree_skb_any(cmd_buf->skb);
  192. cmd_buf->skb = NULL;
  193. }
  194. cmd_buf++;
  195. }
  196. }
  197. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  198. {
  199. struct netxen_recv_context *recv_ctx;
  200. struct netxen_rcv_desc_ctx *rcv_desc;
  201. int ctx, ring;
  202. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  203. recv_ctx = &adapter->recv_ctx[ctx];
  204. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  205. rcv_desc = &recv_ctx->rcv_desc[ring];
  206. if (rcv_desc->rx_buf_arr) {
  207. vfree(rcv_desc->rx_buf_arr);
  208. rcv_desc->rx_buf_arr = NULL;
  209. }
  210. }
  211. }
  212. if (adapter->cmd_buf_arr)
  213. vfree(adapter->cmd_buf_arr);
  214. return;
  215. }
  216. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  217. {
  218. struct netxen_recv_context *recv_ctx;
  219. struct netxen_rcv_desc_ctx *rcv_desc;
  220. struct netxen_rx_buffer *rx_buf;
  221. int ctx, ring, i, num_rx_bufs;
  222. struct netxen_cmd_buffer *cmd_buf_arr;
  223. struct net_device *netdev = adapter->netdev;
  224. cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
  225. if (cmd_buf_arr == NULL) {
  226. printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n",
  227. netdev->name);
  228. return -ENOMEM;
  229. }
  230. memset(cmd_buf_arr, 0, TX_RINGSIZE);
  231. adapter->cmd_buf_arr = cmd_buf_arr;
  232. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  233. recv_ctx = &adapter->recv_ctx[ctx];
  234. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  235. rcv_desc = &recv_ctx->rcv_desc[ring];
  236. switch (RCV_DESC_TYPE(ring)) {
  237. case RCV_DESC_NORMAL:
  238. rcv_desc->max_rx_desc_count =
  239. adapter->max_rx_desc_count;
  240. rcv_desc->flags = RCV_DESC_NORMAL;
  241. rcv_desc->dma_size = RX_DMA_MAP_LEN;
  242. rcv_desc->skb_size = MAX_RX_BUFFER_LENGTH;
  243. break;
  244. case RCV_DESC_JUMBO:
  245. rcv_desc->max_rx_desc_count =
  246. adapter->max_jumbo_rx_desc_count;
  247. rcv_desc->flags = RCV_DESC_JUMBO;
  248. rcv_desc->dma_size = RX_JUMBO_DMA_MAP_LEN;
  249. rcv_desc->skb_size =
  250. MAX_RX_JUMBO_BUFFER_LENGTH;
  251. break;
  252. case RCV_RING_LRO:
  253. rcv_desc->max_rx_desc_count =
  254. adapter->max_lro_rx_desc_count;
  255. rcv_desc->flags = RCV_DESC_LRO;
  256. rcv_desc->dma_size = RX_LRO_DMA_MAP_LEN;
  257. rcv_desc->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  258. break;
  259. }
  260. rcv_desc->rx_buf_arr = (struct netxen_rx_buffer *)
  261. vmalloc(RCV_BUFFSIZE);
  262. if (rcv_desc->rx_buf_arr == NULL) {
  263. printk(KERN_ERR "%s: Failed to allocate "
  264. "rx buffer ring %d\n",
  265. netdev->name, ring);
  266. /* free whatever was already allocated */
  267. goto err_out;
  268. }
  269. memset(rcv_desc->rx_buf_arr, 0, RCV_BUFFSIZE);
  270. rcv_desc->begin_alloc = 0;
  271. /*
  272. * Now go through all of them, set reference handles
  273. * and put them in the queues.
  274. */
  275. num_rx_bufs = rcv_desc->max_rx_desc_count;
  276. rx_buf = rcv_desc->rx_buf_arr;
  277. for (i = 0; i < num_rx_bufs; i++) {
  278. rx_buf->ref_handle = i;
  279. rx_buf->state = NETXEN_BUFFER_FREE;
  280. rx_buf++;
  281. }
  282. }
  283. }
  284. return 0;
  285. err_out:
  286. netxen_free_sw_resources(adapter);
  287. return -ENOMEM;
  288. }
  289. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  290. {
  291. switch (adapter->ahw.board_type) {
  292. case NETXEN_NIC_GBE:
  293. adapter->enable_phy_interrupts =
  294. netxen_niu_gbe_enable_phy_interrupts;
  295. adapter->disable_phy_interrupts =
  296. netxen_niu_gbe_disable_phy_interrupts;
  297. adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
  298. adapter->macaddr_set = netxen_niu_macaddr_set;
  299. adapter->set_mtu = netxen_nic_set_mtu_gb;
  300. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  301. adapter->phy_read = netxen_niu_gbe_phy_read;
  302. adapter->phy_write = netxen_niu_gbe_phy_write;
  303. adapter->init_niu = netxen_nic_init_niu_gb;
  304. adapter->stop_port = netxen_niu_disable_gbe_port;
  305. break;
  306. case NETXEN_NIC_XGBE:
  307. adapter->enable_phy_interrupts =
  308. netxen_niu_xgbe_enable_phy_interrupts;
  309. adapter->disable_phy_interrupts =
  310. netxen_niu_xgbe_disable_phy_interrupts;
  311. adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
  312. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  313. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  314. adapter->init_port = netxen_niu_xg_init_port;
  315. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  316. adapter->stop_port = netxen_niu_disable_xg_port;
  317. break;
  318. default:
  319. break;
  320. }
  321. }
  322. /*
  323. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  324. * address to external PCI CRB address.
  325. */
  326. static u32 netxen_decode_crb_addr(u32 addr)
  327. {
  328. int i;
  329. u32 base_addr, offset, pci_base;
  330. crb_addr_transform_setup();
  331. pci_base = NETXEN_ADDR_ERROR;
  332. base_addr = addr & 0xfff00000;
  333. offset = addr & 0x000fffff;
  334. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  335. if (crb_addr_xform[i] == base_addr) {
  336. pci_base = i << 20;
  337. break;
  338. }
  339. }
  340. if (pci_base == NETXEN_ADDR_ERROR)
  341. return pci_base;
  342. else
  343. return (pci_base + offset);
  344. }
  345. static long rom_max_timeout = 100;
  346. static long rom_lock_timeout = 10000;
  347. #if 0
  348. static long rom_write_timeout = 700;
  349. #endif
  350. static int rom_lock(struct netxen_adapter *adapter)
  351. {
  352. int iter;
  353. u32 done = 0;
  354. int timeout = 0;
  355. while (!done) {
  356. /* acquire semaphore2 from PCI HW block */
  357. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  358. &done);
  359. if (done == 1)
  360. break;
  361. if (timeout >= rom_lock_timeout)
  362. return -EIO;
  363. timeout++;
  364. /*
  365. * Yield CPU
  366. */
  367. if (!in_atomic())
  368. schedule();
  369. else {
  370. for (iter = 0; iter < 20; iter++)
  371. cpu_relax(); /*This a nop instr on i386 */
  372. }
  373. }
  374. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  375. return 0;
  376. }
  377. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  378. {
  379. long timeout = 0;
  380. long done = 0;
  381. while (done == 0) {
  382. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  383. done &= 2;
  384. timeout++;
  385. if (timeout >= rom_max_timeout) {
  386. printk("Timeout reached waiting for rom done");
  387. return -EIO;
  388. }
  389. }
  390. return 0;
  391. }
  392. #if 0
  393. static int netxen_rom_wren(struct netxen_adapter *adapter)
  394. {
  395. /* Set write enable latch in ROM status register */
  396. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  397. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  398. M25P_INSTR_WREN);
  399. if (netxen_wait_rom_done(adapter)) {
  400. return -1;
  401. }
  402. return 0;
  403. }
  404. static unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  405. unsigned int addr)
  406. {
  407. unsigned int data = 0xdeaddead;
  408. data = netxen_nic_reg_read(adapter, addr);
  409. return data;
  410. }
  411. static int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  412. {
  413. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  414. M25P_INSTR_RDSR);
  415. if (netxen_wait_rom_done(adapter)) {
  416. return -1;
  417. }
  418. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  419. }
  420. #endif
  421. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  422. {
  423. u32 val;
  424. /* release semaphore2 */
  425. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  426. }
  427. #if 0
  428. static int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  429. {
  430. long timeout = 0;
  431. long wip = 1;
  432. int val;
  433. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  434. while (wip != 0) {
  435. val = netxen_do_rom_rdsr(adapter);
  436. wip = val & 1;
  437. timeout++;
  438. if (timeout > rom_max_timeout) {
  439. return -1;
  440. }
  441. }
  442. return 0;
  443. }
  444. static int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  445. int data)
  446. {
  447. if (netxen_rom_wren(adapter)) {
  448. return -1;
  449. }
  450. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  451. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  452. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  453. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  454. M25P_INSTR_PP);
  455. if (netxen_wait_rom_done(adapter)) {
  456. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  457. return -1;
  458. }
  459. return netxen_rom_wip_poll(adapter);
  460. }
  461. #endif
  462. static int do_rom_fast_read(struct netxen_adapter *adapter,
  463. int addr, int *valp)
  464. {
  465. cond_resched();
  466. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  467. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  468. udelay(100); /* prevent bursting on CRB */
  469. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  470. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  471. if (netxen_wait_rom_done(adapter)) {
  472. printk("Error waiting for rom done\n");
  473. return -EIO;
  474. }
  475. /* reset abyte_cnt and dummy_byte_cnt */
  476. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  477. udelay(100); /* prevent bursting on CRB */
  478. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  479. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  480. return 0;
  481. }
  482. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  483. u8 *bytes, size_t size)
  484. {
  485. int addridx;
  486. int ret = 0;
  487. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  488. int v;
  489. ret = do_rom_fast_read(adapter, addridx, &v);
  490. if (ret != 0)
  491. break;
  492. *(__le32 *)bytes = cpu_to_le32(v);
  493. bytes += 4;
  494. }
  495. return ret;
  496. }
  497. int
  498. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  499. u8 *bytes, size_t size)
  500. {
  501. int ret;
  502. ret = rom_lock(adapter);
  503. if (ret < 0)
  504. return ret;
  505. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  506. netxen_rom_unlock(adapter);
  507. return ret;
  508. }
  509. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  510. {
  511. int ret;
  512. if (rom_lock(adapter) != 0)
  513. return -EIO;
  514. ret = do_rom_fast_read(adapter, addr, valp);
  515. netxen_rom_unlock(adapter);
  516. return ret;
  517. }
  518. #if 0
  519. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  520. {
  521. int ret = 0;
  522. if (rom_lock(adapter) != 0) {
  523. return -1;
  524. }
  525. ret = do_rom_fast_write(adapter, addr, data);
  526. netxen_rom_unlock(adapter);
  527. return ret;
  528. }
  529. static int do_rom_fast_write_words(struct netxen_adapter *adapter,
  530. int addr, u8 *bytes, size_t size)
  531. {
  532. int addridx = addr;
  533. int ret = 0;
  534. while (addridx < (addr + size)) {
  535. int last_attempt = 0;
  536. int timeout = 0;
  537. int data;
  538. data = le32_to_cpu((*(__le32*)bytes));
  539. ret = do_rom_fast_write(adapter, addridx, data);
  540. if (ret < 0)
  541. return ret;
  542. while(1) {
  543. int data1;
  544. ret = do_rom_fast_read(adapter, addridx, &data1);
  545. if (ret < 0)
  546. return ret;
  547. if (data1 == data)
  548. break;
  549. if (timeout++ >= rom_write_timeout) {
  550. if (last_attempt++ < 4) {
  551. ret = do_rom_fast_write(adapter,
  552. addridx, data);
  553. if (ret < 0)
  554. return ret;
  555. }
  556. else {
  557. printk(KERN_INFO "Data write did not "
  558. "succeed at address 0x%x\n", addridx);
  559. break;
  560. }
  561. }
  562. }
  563. bytes += 4;
  564. addridx += 4;
  565. }
  566. return ret;
  567. }
  568. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  569. u8 *bytes, size_t size)
  570. {
  571. int ret = 0;
  572. ret = rom_lock(adapter);
  573. if (ret < 0)
  574. return ret;
  575. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  576. netxen_rom_unlock(adapter);
  577. return ret;
  578. }
  579. static int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  580. {
  581. int ret;
  582. ret = netxen_rom_wren(adapter);
  583. if (ret < 0)
  584. return ret;
  585. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  586. netxen_crb_writelit_adapter(adapter,
  587. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  588. ret = netxen_wait_rom_done(adapter);
  589. if (ret < 0)
  590. return ret;
  591. return netxen_rom_wip_poll(adapter);
  592. }
  593. static int netxen_rom_rdsr(struct netxen_adapter *adapter)
  594. {
  595. int ret;
  596. ret = rom_lock(adapter);
  597. if (ret < 0)
  598. return ret;
  599. ret = netxen_do_rom_rdsr(adapter);
  600. netxen_rom_unlock(adapter);
  601. return ret;
  602. }
  603. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  604. {
  605. int ret = FLASH_SUCCESS;
  606. int val;
  607. char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL);
  608. if (!buffer)
  609. return -ENOMEM;
  610. /* unlock sector 63 */
  611. val = netxen_rom_rdsr(adapter);
  612. val = val & 0xe3;
  613. ret = netxen_rom_wrsr(adapter, val);
  614. if (ret != FLASH_SUCCESS)
  615. goto out_kfree;
  616. ret = netxen_rom_wip_poll(adapter);
  617. if (ret != FLASH_SUCCESS)
  618. goto out_kfree;
  619. /* copy sector 0 to sector 63 */
  620. ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START,
  621. buffer, NETXEN_FLASH_SECTOR_SIZE);
  622. if (ret != FLASH_SUCCESS)
  623. goto out_kfree;
  624. ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START,
  625. buffer, NETXEN_FLASH_SECTOR_SIZE);
  626. if (ret != FLASH_SUCCESS)
  627. goto out_kfree;
  628. /* lock sector 63 */
  629. val = netxen_rom_rdsr(adapter);
  630. if (!(val & 0x8)) {
  631. val |= (0x1 << 2);
  632. /* lock sector 63 */
  633. if (netxen_rom_wrsr(adapter, val) == 0) {
  634. ret = netxen_rom_wip_poll(adapter);
  635. if (ret != FLASH_SUCCESS)
  636. goto out_kfree;
  637. /* lock SR writes */
  638. ret = netxen_rom_wip_poll(adapter);
  639. if (ret != FLASH_SUCCESS)
  640. goto out_kfree;
  641. }
  642. }
  643. out_kfree:
  644. kfree(buffer);
  645. return ret;
  646. }
  647. static int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  648. {
  649. netxen_rom_wren(adapter);
  650. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  651. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  652. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  653. M25P_INSTR_SE);
  654. if (netxen_wait_rom_done(adapter)) {
  655. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  656. return -1;
  657. }
  658. return netxen_rom_wip_poll(adapter);
  659. }
  660. static void check_erased_flash(struct netxen_adapter *adapter, int addr)
  661. {
  662. int i;
  663. int val;
  664. int count = 0, erased_errors = 0;
  665. int range;
  666. range = (addr == NETXEN_USER_START) ?
  667. NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE;
  668. for (i = addr; i < range; i += 4) {
  669. netxen_rom_fast_read(adapter, i, &val);
  670. if (val != 0xffffffff)
  671. erased_errors++;
  672. count++;
  673. }
  674. if (erased_errors)
  675. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  676. "for sector address: %x\n", erased_errors, count, addr);
  677. }
  678. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  679. {
  680. int ret = 0;
  681. if (rom_lock(adapter) != 0) {
  682. return -1;
  683. }
  684. ret = netxen_do_rom_se(adapter, addr);
  685. netxen_rom_unlock(adapter);
  686. msleep(30);
  687. check_erased_flash(adapter, addr);
  688. return ret;
  689. }
  690. static int netxen_flash_erase_sections(struct netxen_adapter *adapter,
  691. int start, int end)
  692. {
  693. int ret = FLASH_SUCCESS;
  694. int i;
  695. for (i = start; i < end; i++) {
  696. ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE);
  697. if (ret)
  698. break;
  699. ret = netxen_rom_wip_poll(adapter);
  700. if (ret < 0)
  701. return ret;
  702. }
  703. return ret;
  704. }
  705. int
  706. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  707. {
  708. int ret = FLASH_SUCCESS;
  709. int start, end;
  710. start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  711. end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE;
  712. ret = netxen_flash_erase_sections(adapter, start, end);
  713. return ret;
  714. }
  715. int
  716. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  717. {
  718. int ret = FLASH_SUCCESS;
  719. int start, end;
  720. start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE;
  721. end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  722. ret = netxen_flash_erase_sections(adapter, start, end);
  723. return ret;
  724. }
  725. void netxen_halt_pegs(struct netxen_adapter *adapter)
  726. {
  727. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  728. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  729. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  730. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  731. }
  732. int netxen_flash_unlock(struct netxen_adapter *adapter)
  733. {
  734. int ret = 0;
  735. ret = netxen_rom_wrsr(adapter, 0);
  736. if (ret < 0)
  737. return ret;
  738. ret = netxen_rom_wren(adapter);
  739. if (ret < 0)
  740. return ret;
  741. return ret;
  742. }
  743. #endif /* 0 */
  744. #define NETXEN_BOARDTYPE 0x4008
  745. #define NETXEN_BOARDNUM 0x400c
  746. #define NETXEN_CHIPNUM 0x4010
  747. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  748. {
  749. int addr, val;
  750. int i, init_delay = 0;
  751. struct crb_addr_pair *buf;
  752. unsigned offset, n;
  753. u32 off;
  754. /* resetall */
  755. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  756. 0xffffffff);
  757. if (verbose) {
  758. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  759. printk("P2 ROM board type: 0x%08x\n", val);
  760. else
  761. printk("Could not read board type\n");
  762. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  763. printk("P2 ROM board num: 0x%08x\n", val);
  764. else
  765. printk("Could not read board number\n");
  766. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  767. printk("P2 ROM chip num: 0x%08x\n", val);
  768. else
  769. printk("Could not read chip number\n");
  770. }
  771. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  772. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  773. (n != 0xcafecafeUL) ||
  774. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  775. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  776. "n: %08x\n", netxen_nic_driver_name, n);
  777. return -EIO;
  778. }
  779. offset = n & 0xffffU;
  780. n = (n >> 16) & 0xffffU;
  781. } else {
  782. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  783. !(n & 0x80000000)) {
  784. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  785. "n: %08x\n", netxen_nic_driver_name, n);
  786. return -EIO;
  787. }
  788. offset = 1;
  789. n &= ~0x80000000;
  790. }
  791. if (n < 1024) {
  792. if (verbose)
  793. printk(KERN_DEBUG "%s: %d CRB init values found"
  794. " in ROM.\n", netxen_nic_driver_name, n);
  795. } else {
  796. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  797. " initialized.\n", __func__, n);
  798. return -EIO;
  799. }
  800. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  801. if (buf == NULL) {
  802. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  803. netxen_nic_driver_name);
  804. return -ENOMEM;
  805. }
  806. for (i = 0; i < n; i++) {
  807. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  808. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0)
  809. return -EIO;
  810. buf[i].addr = addr;
  811. buf[i].data = val;
  812. if (verbose)
  813. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  814. netxen_nic_driver_name,
  815. (u32)netxen_decode_crb_addr(addr), val);
  816. }
  817. for (i = 0; i < n; i++) {
  818. off = netxen_decode_crb_addr(buf[i].addr);
  819. if (off == NETXEN_ADDR_ERROR) {
  820. printk(KERN_ERR"CRB init value out of range %x\n",
  821. buf[i].addr);
  822. continue;
  823. }
  824. off += NETXEN_PCI_CRBSPACE;
  825. /* skipping cold reboot MAGIC */
  826. if (off == NETXEN_CAM_RAM(0x1fc))
  827. continue;
  828. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  829. /* do not reset PCI */
  830. if (off == (ROMUSB_GLB + 0xbc))
  831. continue;
  832. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  833. buf[i].data = 0x1020;
  834. /* skip the function enable register */
  835. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  836. continue;
  837. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  838. continue;
  839. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  840. continue;
  841. }
  842. if (off == NETXEN_ADDR_ERROR) {
  843. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  844. netxen_nic_driver_name, buf[i].addr);
  845. continue;
  846. }
  847. /* After writing this register, HW needs time for CRB */
  848. /* to quiet down (else crb_window returns 0xffffffff) */
  849. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  850. init_delay = 1;
  851. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  852. /* hold xdma in reset also */
  853. buf[i].data = NETXEN_NIC_XDMA_RESET;
  854. }
  855. }
  856. adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
  857. if (init_delay == 1) {
  858. msleep(1000);
  859. init_delay = 0;
  860. }
  861. msleep(1);
  862. }
  863. kfree(buf);
  864. /* disable_peg_cache_all */
  865. /* unreset_net_cache */
  866. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  867. adapter->hw_read_wx(adapter,
  868. NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
  869. netxen_crb_writelit_adapter(adapter,
  870. NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  871. }
  872. /* p2dn replyCount */
  873. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  874. /* disable_peg_cache 0 */
  875. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  876. /* disable_peg_cache 1 */
  877. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  878. /* peg_clr_all */
  879. /* peg_clr 0 */
  880. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  881. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  882. /* peg_clr 1 */
  883. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  884. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  885. /* peg_clr 2 */
  886. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  887. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  888. /* peg_clr 3 */
  889. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  890. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  891. return 0;
  892. }
  893. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  894. {
  895. uint64_t addr;
  896. uint32_t hi;
  897. uint32_t lo;
  898. adapter->dummy_dma.addr =
  899. pci_alloc_consistent(adapter->pdev,
  900. NETXEN_HOST_DUMMY_DMA_SIZE,
  901. &adapter->dummy_dma.phys_addr);
  902. if (adapter->dummy_dma.addr == NULL) {
  903. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  904. __func__);
  905. return -ENOMEM;
  906. }
  907. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  908. hi = (addr >> 32) & 0xffffffff;
  909. lo = addr & 0xffffffff;
  910. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  911. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  912. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  913. uint32_t temp = 0;
  914. adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
  915. }
  916. return 0;
  917. }
  918. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  919. {
  920. int i;
  921. if (adapter->dummy_dma.addr) {
  922. i = 100;
  923. do {
  924. if (dma_watchdog_shutdown_request(adapter) == 1)
  925. break;
  926. msleep(50);
  927. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  928. break;
  929. } while (--i);
  930. if (i) {
  931. pci_free_consistent(adapter->pdev,
  932. NETXEN_HOST_DUMMY_DMA_SIZE,
  933. adapter->dummy_dma.addr,
  934. adapter->dummy_dma.phys_addr);
  935. adapter->dummy_dma.addr = NULL;
  936. } else {
  937. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  938. adapter->netdev->name);
  939. }
  940. }
  941. }
  942. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  943. {
  944. u32 val = 0;
  945. int retries = 60;
  946. if (!pegtune_val) {
  947. do {
  948. val = adapter->pci_read_normalize(adapter,
  949. CRB_CMDPEG_STATE);
  950. if (val == PHAN_INITIALIZE_COMPLETE ||
  951. val == PHAN_INITIALIZE_ACK)
  952. return 0;
  953. msleep(500);
  954. } while (--retries);
  955. if (!retries) {
  956. pegtune_val = adapter->pci_read_normalize(adapter,
  957. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  958. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  959. "pegtune_val=%x\n", pegtune_val);
  960. return -1;
  961. }
  962. }
  963. return 0;
  964. }
  965. int netxen_receive_peg_ready(struct netxen_adapter *adapter)
  966. {
  967. u32 val = 0;
  968. int retries = 2000;
  969. do {
  970. val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
  971. if (val == PHAN_PEG_RCV_INITIALIZED)
  972. return 0;
  973. msleep(10);
  974. } while (--retries);
  975. if (!retries) {
  976. printk(KERN_ERR "Receive Peg initialization not "
  977. "complete, state: 0x%x.\n", val);
  978. return -EIO;
  979. }
  980. return 0;
  981. }
  982. static int netxen_nic_check_temp(struct netxen_adapter *adapter)
  983. {
  984. struct net_device *netdev = adapter->netdev;
  985. uint32_t temp, temp_state, temp_val;
  986. int rv = 0;
  987. temp = adapter->pci_read_normalize(adapter, CRB_TEMP_STATE);
  988. temp_state = nx_get_temp_state(temp);
  989. temp_val = nx_get_temp_val(temp);
  990. if (temp_state == NX_TEMP_PANIC) {
  991. printk(KERN_ALERT
  992. "%s: Device temperature %d degrees C exceeds"
  993. " maximum allowed. Hardware has been shut down.\n",
  994. netxen_nic_driver_name, temp_val);
  995. netif_carrier_off(netdev);
  996. netif_stop_queue(netdev);
  997. rv = 1;
  998. } else if (temp_state == NX_TEMP_WARN) {
  999. if (adapter->temp == NX_TEMP_NORMAL) {
  1000. printk(KERN_ALERT
  1001. "%s: Device temperature %d degrees C "
  1002. "exceeds operating range."
  1003. " Immediate action needed.\n",
  1004. netxen_nic_driver_name, temp_val);
  1005. }
  1006. } else {
  1007. if (adapter->temp == NX_TEMP_WARN) {
  1008. printk(KERN_INFO
  1009. "%s: Device temperature is now %d degrees C"
  1010. " in normal range.\n", netxen_nic_driver_name,
  1011. temp_val);
  1012. }
  1013. }
  1014. adapter->temp = temp_state;
  1015. return rv;
  1016. }
  1017. void netxen_watchdog_task(struct work_struct *work)
  1018. {
  1019. struct netxen_adapter *adapter =
  1020. container_of(work, struct netxen_adapter, watchdog_task);
  1021. if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter))
  1022. return;
  1023. if (adapter->handle_phy_intr)
  1024. adapter->handle_phy_intr(adapter);
  1025. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  1026. }
  1027. /*
  1028. * netxen_process_rcv() send the received packet to the protocol stack.
  1029. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  1030. * invoke the routine to send more rx buffers to the Phantom...
  1031. */
  1032. static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  1033. struct status_desc *desc)
  1034. {
  1035. struct pci_dev *pdev = adapter->pdev;
  1036. struct net_device *netdev = adapter->netdev;
  1037. u64 sts_data = le64_to_cpu(desc->status_desc_data);
  1038. int index = netxen_get_sts_refhandle(sts_data);
  1039. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1040. struct netxen_rx_buffer *buffer;
  1041. struct sk_buff *skb;
  1042. u32 length = netxen_get_sts_totallength(sts_data);
  1043. u32 desc_ctx;
  1044. struct netxen_rcv_desc_ctx *rcv_desc;
  1045. int ret;
  1046. desc_ctx = netxen_get_sts_type(sts_data);
  1047. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  1048. printk("%s: %s Bad Rcv descriptor ring\n",
  1049. netxen_nic_driver_name, netdev->name);
  1050. return;
  1051. }
  1052. rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
  1053. if (unlikely(index > rcv_desc->max_rx_desc_count)) {
  1054. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  1055. index, rcv_desc->max_rx_desc_count);
  1056. return;
  1057. }
  1058. buffer = &rcv_desc->rx_buf_arr[index];
  1059. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1060. buffer->lro_current_frags++;
  1061. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  1062. buffer->lro_expected_frags =
  1063. netxen_get_sts_desc_lro_cnt(desc);
  1064. buffer->lro_length = length;
  1065. }
  1066. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  1067. if (buffer->lro_expected_frags != 0) {
  1068. printk("LRO: (refhandle:%x) recv frag. "
  1069. "wait for last. flags: %x expected:%d "
  1070. "have:%d\n", index,
  1071. netxen_get_sts_desc_lro_last_frag(desc),
  1072. buffer->lro_expected_frags,
  1073. buffer->lro_current_frags);
  1074. }
  1075. return;
  1076. }
  1077. }
  1078. pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
  1079. PCI_DMA_FROMDEVICE);
  1080. skb = (struct sk_buff *)buffer->skb;
  1081. if (likely(adapter->rx_csum &&
  1082. netxen_get_sts_status(sts_data) == STATUS_CKSUM_OK)) {
  1083. adapter->stats.csummed++;
  1084. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1085. } else
  1086. skb->ip_summed = CHECKSUM_NONE;
  1087. skb->dev = netdev;
  1088. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1089. /* True length was only available on the last pkt */
  1090. skb_put(skb, buffer->lro_length);
  1091. } else {
  1092. skb_put(skb, length);
  1093. }
  1094. skb->protocol = eth_type_trans(skb, netdev);
  1095. ret = netif_receive_skb(skb);
  1096. netdev->last_rx = jiffies;
  1097. /*
  1098. * We just consumed one buffer so post a buffer.
  1099. */
  1100. buffer->skb = NULL;
  1101. buffer->state = NETXEN_BUFFER_FREE;
  1102. buffer->lro_current_frags = 0;
  1103. buffer->lro_expected_frags = 0;
  1104. adapter->stats.no_rcv++;
  1105. adapter->stats.rxbytes += length;
  1106. }
  1107. /* Process Receive status ring */
  1108. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1109. {
  1110. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1111. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1112. struct status_desc *desc; /* used to read status desc here */
  1113. u32 consumer = recv_ctx->status_rx_consumer;
  1114. int count = 0, ring;
  1115. while (count < max) {
  1116. desc = &desc_head[consumer];
  1117. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1118. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1119. netxen_get_sts_owner(desc));
  1120. break;
  1121. }
  1122. netxen_process_rcv(adapter, ctxid, desc);
  1123. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1124. consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
  1125. count++;
  1126. }
  1127. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++)
  1128. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1129. /* update the consumer index in phantom */
  1130. if (count) {
  1131. recv_ctx->status_rx_consumer = consumer;
  1132. /* Window = 1 */
  1133. adapter->pci_write_normalize(adapter,
  1134. recv_ctx->crb_sts_consumer, consumer);
  1135. }
  1136. return count;
  1137. }
  1138. /* Process Command status ring */
  1139. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1140. {
  1141. u32 last_consumer, consumer;
  1142. int count = 0, i;
  1143. struct netxen_cmd_buffer *buffer;
  1144. struct pci_dev *pdev = adapter->pdev;
  1145. struct net_device *netdev = adapter->netdev;
  1146. struct netxen_skb_frag *frag;
  1147. int done = 0;
  1148. last_consumer = adapter->last_cmd_consumer;
  1149. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1150. while (last_consumer != consumer) {
  1151. buffer = &adapter->cmd_buf_arr[last_consumer];
  1152. if (buffer->skb) {
  1153. frag = &buffer->frag_array[0];
  1154. pci_unmap_single(pdev, frag->dma, frag->length,
  1155. PCI_DMA_TODEVICE);
  1156. frag->dma = 0ULL;
  1157. for (i = 1; i < buffer->frag_count; i++) {
  1158. frag++; /* Get the next frag */
  1159. pci_unmap_page(pdev, frag->dma, frag->length,
  1160. PCI_DMA_TODEVICE);
  1161. frag->dma = 0ULL;
  1162. }
  1163. adapter->stats.xmitfinished++;
  1164. dev_kfree_skb_any(buffer->skb);
  1165. buffer->skb = NULL;
  1166. }
  1167. last_consumer = get_next_index(last_consumer,
  1168. adapter->max_tx_desc_count);
  1169. if (++count >= MAX_STATUS_HANDLE)
  1170. break;
  1171. }
  1172. if (count) {
  1173. adapter->last_cmd_consumer = last_consumer;
  1174. smp_mb();
  1175. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  1176. netif_tx_lock(netdev);
  1177. netif_wake_queue(netdev);
  1178. smp_mb();
  1179. netif_tx_unlock(netdev);
  1180. }
  1181. }
  1182. /*
  1183. * If everything is freed up to consumer then check if the ring is full
  1184. * If the ring is full then check if more needs to be freed and
  1185. * schedule the call back again.
  1186. *
  1187. * This happens when there are 2 CPUs. One could be freeing and the
  1188. * other filling it. If the ring is full when we get out of here and
  1189. * the card has already interrupted the host then the host can miss the
  1190. * interrupt.
  1191. *
  1192. * There is still a possible race condition and the host could miss an
  1193. * interrupt. The card has to take care of this.
  1194. */
  1195. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1196. done = (last_consumer == consumer);
  1197. return (done);
  1198. }
  1199. /*
  1200. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1201. */
  1202. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1203. {
  1204. struct pci_dev *pdev = adapter->pdev;
  1205. struct sk_buff *skb;
  1206. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1207. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1208. uint producer;
  1209. struct rcv_desc *pdesc;
  1210. struct netxen_rx_buffer *buffer;
  1211. int count = 0;
  1212. int index = 0;
  1213. netxen_ctx_msg msg = 0;
  1214. dma_addr_t dma;
  1215. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1216. producer = rcv_desc->producer;
  1217. index = rcv_desc->begin_alloc;
  1218. buffer = &rcv_desc->rx_buf_arr[index];
  1219. /* We can start writing rx descriptors into the phantom memory. */
  1220. while (buffer->state == NETXEN_BUFFER_FREE) {
  1221. skb = dev_alloc_skb(rcv_desc->skb_size);
  1222. if (unlikely(!skb)) {
  1223. /*
  1224. * TODO
  1225. * We need to schedule the posting of buffers to the pegs.
  1226. */
  1227. rcv_desc->begin_alloc = index;
  1228. DPRINTK(ERR, "netxen_post_rx_buffers: "
  1229. " allocated only %d buffers\n", count);
  1230. break;
  1231. }
  1232. count++; /* now there should be no failure */
  1233. pdesc = &rcv_desc->desc_head[producer];
  1234. #if defined(XGB_DEBUG)
  1235. *(unsigned long *)(skb->head) = 0xc0debabe;
  1236. if (skb_is_nonlinear(skb)) {
  1237. printk("Allocated SKB @%p is nonlinear\n");
  1238. }
  1239. #endif
  1240. skb_reserve(skb, 2);
  1241. /* This will be setup when we receive the
  1242. * buffer after it has been filled FSL TBD TBD
  1243. * skb->dev = netdev;
  1244. */
  1245. dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
  1246. PCI_DMA_FROMDEVICE);
  1247. pdesc->addr_buffer = cpu_to_le64(dma);
  1248. buffer->skb = skb;
  1249. buffer->state = NETXEN_BUFFER_BUSY;
  1250. buffer->dma = dma;
  1251. /* make a rcv descriptor */
  1252. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1253. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1254. DPRINTK(INFO, "done writing descripter\n");
  1255. producer =
  1256. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1257. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1258. buffer = &rcv_desc->rx_buf_arr[index];
  1259. }
  1260. /* if we did allocate buffers, then write the count to Phantom */
  1261. if (count) {
  1262. rcv_desc->begin_alloc = index;
  1263. rcv_desc->producer = producer;
  1264. /* Window = 1 */
  1265. adapter->pci_write_normalize(adapter,
  1266. rcv_desc->crb_rcv_producer,
  1267. (producer-1) & (rcv_desc->max_rx_desc_count-1));
  1268. /*
  1269. * Write a doorbell msg to tell phanmon of change in
  1270. * receive ring producer
  1271. */
  1272. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1273. netxen_set_msg_privid(msg);
  1274. netxen_set_msg_count(msg,
  1275. ((producer -
  1276. 1) & (rcv_desc->
  1277. max_rx_desc_count - 1)));
  1278. netxen_set_msg_ctxid(msg, adapter->portnum);
  1279. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1280. writel(msg,
  1281. DB_NORMALIZE(adapter,
  1282. NETXEN_RCV_PRODUCER_OFFSET));
  1283. }
  1284. }
  1285. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1286. uint32_t ctx, uint32_t ringid)
  1287. {
  1288. struct pci_dev *pdev = adapter->pdev;
  1289. struct sk_buff *skb;
  1290. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1291. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1292. u32 producer;
  1293. struct rcv_desc *pdesc;
  1294. struct netxen_rx_buffer *buffer;
  1295. int count = 0;
  1296. int index = 0;
  1297. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1298. producer = rcv_desc->producer;
  1299. index = rcv_desc->begin_alloc;
  1300. buffer = &rcv_desc->rx_buf_arr[index];
  1301. /* We can start writing rx descriptors into the phantom memory. */
  1302. while (buffer->state == NETXEN_BUFFER_FREE) {
  1303. skb = dev_alloc_skb(rcv_desc->skb_size);
  1304. if (unlikely(!skb)) {
  1305. /*
  1306. * We need to schedule the posting of buffers to the pegs.
  1307. */
  1308. rcv_desc->begin_alloc = index;
  1309. DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
  1310. " allocated only %d buffers\n", count);
  1311. break;
  1312. }
  1313. count++; /* now there should be no failure */
  1314. pdesc = &rcv_desc->desc_head[producer];
  1315. skb_reserve(skb, 2);
  1316. /*
  1317. * This will be setup when we receive the
  1318. * buffer after it has been filled
  1319. * skb->dev = netdev;
  1320. */
  1321. buffer->skb = skb;
  1322. buffer->state = NETXEN_BUFFER_BUSY;
  1323. buffer->dma = pci_map_single(pdev, skb->data,
  1324. rcv_desc->dma_size,
  1325. PCI_DMA_FROMDEVICE);
  1326. /* make a rcv descriptor */
  1327. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1328. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1329. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1330. producer =
  1331. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1332. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1333. buffer = &rcv_desc->rx_buf_arr[index];
  1334. }
  1335. /* if we did allocate buffers, then write the count to Phantom */
  1336. if (count) {
  1337. rcv_desc->begin_alloc = index;
  1338. rcv_desc->producer = producer;
  1339. /* Window = 1 */
  1340. adapter->pci_write_normalize(adapter,
  1341. rcv_desc->crb_rcv_producer,
  1342. (producer-1) & (rcv_desc->max_rx_desc_count-1));
  1343. wmb();
  1344. }
  1345. }
  1346. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1347. {
  1348. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1349. return;
  1350. }