davinci-mcasp.c 34 KB

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  1. /*
  2. * ALSA SoC McASP Audio Layer for TI DAVINCI processor
  3. *
  4. * Multi-channel Audio Serial Port Driver
  5. *
  6. * Author: Nirmal Pandey <n-pandey@ti.com>,
  7. * Suresh Rajashekara <suresh.r@ti.com>
  8. * Steve Chen <schen@.mvista.com>
  9. *
  10. * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
  11. * Copyright: (C) 2009 Texas Instruments, India
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License version 2 as
  15. * published by the Free Software Foundation.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/module.h>
  19. #include <linux/device.h>
  20. #include <linux/slab.h>
  21. #include <linux/delay.h>
  22. #include <linux/io.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/of.h>
  25. #include <linux/of_platform.h>
  26. #include <linux/of_device.h>
  27. #include <sound/core.h>
  28. #include <sound/pcm.h>
  29. #include <sound/pcm_params.h>
  30. #include <sound/initval.h>
  31. #include <sound/soc.h>
  32. #include "davinci-pcm.h"
  33. #include "davinci-mcasp.h"
  34. /*
  35. * McASP register definitions
  36. */
  37. #define DAVINCI_MCASP_PID_REG 0x00
  38. #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
  39. #define DAVINCI_MCASP_PFUNC_REG 0x10
  40. #define DAVINCI_MCASP_PDIR_REG 0x14
  41. #define DAVINCI_MCASP_PDOUT_REG 0x18
  42. #define DAVINCI_MCASP_PDSET_REG 0x1c
  43. #define DAVINCI_MCASP_PDCLR_REG 0x20
  44. #define DAVINCI_MCASP_TLGC_REG 0x30
  45. #define DAVINCI_MCASP_TLMR_REG 0x34
  46. #define DAVINCI_MCASP_GBLCTL_REG 0x44
  47. #define DAVINCI_MCASP_AMUTE_REG 0x48
  48. #define DAVINCI_MCASP_LBCTL_REG 0x4c
  49. #define DAVINCI_MCASP_TXDITCTL_REG 0x50
  50. #define DAVINCI_MCASP_GBLCTLR_REG 0x60
  51. #define DAVINCI_MCASP_RXMASK_REG 0x64
  52. #define DAVINCI_MCASP_RXFMT_REG 0x68
  53. #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
  54. #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
  55. #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
  56. #define DAVINCI_MCASP_RXTDM_REG 0x78
  57. #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
  58. #define DAVINCI_MCASP_RXSTAT_REG 0x80
  59. #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
  60. #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
  61. #define DAVINCI_MCASP_REVTCTL_REG 0x8c
  62. #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
  63. #define DAVINCI_MCASP_TXMASK_REG 0xa4
  64. #define DAVINCI_MCASP_TXFMT_REG 0xa8
  65. #define DAVINCI_MCASP_TXFMCTL_REG 0xac
  66. #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
  67. #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
  68. #define DAVINCI_MCASP_TXTDM_REG 0xb8
  69. #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
  70. #define DAVINCI_MCASP_TXSTAT_REG 0xc0
  71. #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
  72. #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
  73. #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
  74. /* Left(even TDM Slot) Channel Status Register File */
  75. #define DAVINCI_MCASP_DITCSRA_REG 0x100
  76. /* Right(odd TDM slot) Channel Status Register File */
  77. #define DAVINCI_MCASP_DITCSRB_REG 0x118
  78. /* Left(even TDM slot) User Data Register File */
  79. #define DAVINCI_MCASP_DITUDRA_REG 0x130
  80. /* Right(odd TDM Slot) User Data Register File */
  81. #define DAVINCI_MCASP_DITUDRB_REG 0x148
  82. /* Serializer n Control Register */
  83. #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
  84. #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
  85. (n << 2))
  86. /* Transmit Buffer for Serializer n */
  87. #define DAVINCI_MCASP_TXBUF_REG 0x200
  88. /* Receive Buffer for Serializer n */
  89. #define DAVINCI_MCASP_RXBUF_REG 0x280
  90. /* McASP FIFO Registers */
  91. #define DAVINCI_MCASP_WFIFOCTL (0x1010)
  92. #define DAVINCI_MCASP_WFIFOSTS (0x1014)
  93. #define DAVINCI_MCASP_RFIFOCTL (0x1018)
  94. #define DAVINCI_MCASP_RFIFOSTS (0x101C)
  95. #define MCASP_VER3_WFIFOCTL (0x1000)
  96. #define MCASP_VER3_WFIFOSTS (0x1004)
  97. #define MCASP_VER3_RFIFOCTL (0x1008)
  98. #define MCASP_VER3_RFIFOSTS (0x100C)
  99. /*
  100. * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
  101. * Register Bits
  102. */
  103. #define MCASP_FREE BIT(0)
  104. #define MCASP_SOFT BIT(1)
  105. /*
  106. * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
  107. */
  108. #define AXR(n) (1<<n)
  109. #define PFUNC_AMUTE BIT(25)
  110. #define ACLKX BIT(26)
  111. #define AHCLKX BIT(27)
  112. #define AFSX BIT(28)
  113. #define ACLKR BIT(29)
  114. #define AHCLKR BIT(30)
  115. #define AFSR BIT(31)
  116. /*
  117. * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
  118. */
  119. #define AXR(n) (1<<n)
  120. #define PDIR_AMUTE BIT(25)
  121. #define ACLKX BIT(26)
  122. #define AHCLKX BIT(27)
  123. #define AFSX BIT(28)
  124. #define ACLKR BIT(29)
  125. #define AHCLKR BIT(30)
  126. #define AFSR BIT(31)
  127. /*
  128. * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
  129. */
  130. #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
  131. #define VA BIT(2)
  132. #define VB BIT(3)
  133. /*
  134. * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
  135. */
  136. #define TXROT(val) (val)
  137. #define TXSEL BIT(3)
  138. #define TXSSZ(val) (val<<4)
  139. #define TXPBIT(val) (val<<8)
  140. #define TXPAD(val) (val<<13)
  141. #define TXORD BIT(15)
  142. #define FSXDLY(val) (val<<16)
  143. /*
  144. * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
  145. */
  146. #define RXROT(val) (val)
  147. #define RXSEL BIT(3)
  148. #define RXSSZ(val) (val<<4)
  149. #define RXPBIT(val) (val<<8)
  150. #define RXPAD(val) (val<<13)
  151. #define RXORD BIT(15)
  152. #define FSRDLY(val) (val<<16)
  153. /*
  154. * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
  155. */
  156. #define FSXPOL BIT(0)
  157. #define AFSXE BIT(1)
  158. #define FSXDUR BIT(4)
  159. #define FSXMOD(val) (val<<7)
  160. /*
  161. * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
  162. */
  163. #define FSRPOL BIT(0)
  164. #define AFSRE BIT(1)
  165. #define FSRDUR BIT(4)
  166. #define FSRMOD(val) (val<<7)
  167. /*
  168. * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
  169. */
  170. #define ACLKXDIV(val) (val)
  171. #define ACLKXE BIT(5)
  172. #define TX_ASYNC BIT(6)
  173. #define ACLKXPOL BIT(7)
  174. #define ACLKXDIV_MASK 0x1f
  175. /*
  176. * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
  177. */
  178. #define ACLKRDIV(val) (val)
  179. #define ACLKRE BIT(5)
  180. #define RX_ASYNC BIT(6)
  181. #define ACLKRPOL BIT(7)
  182. #define ACLKRDIV_MASK 0x1f
  183. /*
  184. * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
  185. * Register Bits
  186. */
  187. #define AHCLKXDIV(val) (val)
  188. #define AHCLKXPOL BIT(14)
  189. #define AHCLKXE BIT(15)
  190. #define AHCLKXDIV_MASK 0xfff
  191. /*
  192. * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
  193. * Register Bits
  194. */
  195. #define AHCLKRDIV(val) (val)
  196. #define AHCLKRPOL BIT(14)
  197. #define AHCLKRE BIT(15)
  198. #define AHCLKRDIV_MASK 0xfff
  199. /*
  200. * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
  201. */
  202. #define MODE(val) (val)
  203. #define DISMOD (val)(val<<2)
  204. #define TXSTATE BIT(4)
  205. #define RXSTATE BIT(5)
  206. #define SRMOD_MASK 3
  207. #define SRMOD_INACTIVE 0
  208. #define SRMOD_TX 1
  209. #define SRMOD_RX 2
  210. /*
  211. * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
  212. */
  213. #define LBEN BIT(0)
  214. #define LBORD BIT(1)
  215. #define LBGENMODE(val) (val<<2)
  216. /*
  217. * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
  218. */
  219. #define TXTDMS(n) (1<<n)
  220. /*
  221. * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
  222. */
  223. #define RXTDMS(n) (1<<n)
  224. /*
  225. * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
  226. */
  227. #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
  228. #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
  229. #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
  230. #define RXSMRST BIT(3) /* Receiver State Machine Reset */
  231. #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
  232. #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
  233. #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
  234. #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
  235. #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
  236. #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
  237. /*
  238. * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
  239. */
  240. #define MUTENA(val) (val)
  241. #define MUTEINPOL BIT(2)
  242. #define MUTEINENA BIT(3)
  243. #define MUTEIN BIT(4)
  244. #define MUTER BIT(5)
  245. #define MUTEX BIT(6)
  246. #define MUTEFSR BIT(7)
  247. #define MUTEFSX BIT(8)
  248. #define MUTEBADCLKR BIT(9)
  249. #define MUTEBADCLKX BIT(10)
  250. #define MUTERXDMAERR BIT(11)
  251. #define MUTETXDMAERR BIT(12)
  252. /*
  253. * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
  254. */
  255. #define RXDATADMADIS BIT(0)
  256. /*
  257. * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
  258. */
  259. #define TXDATADMADIS BIT(0)
  260. /*
  261. * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
  262. */
  263. #define FIFO_ENABLE BIT(16)
  264. #define NUMEVT_MASK (0xFF << 8)
  265. #define NUMDMA_MASK (0xFF)
  266. #define DAVINCI_MCASP_NUM_SERIALIZER 16
  267. static inline void mcasp_set_bits(void __iomem *reg, u32 val)
  268. {
  269. __raw_writel(__raw_readl(reg) | val, reg);
  270. }
  271. static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
  272. {
  273. __raw_writel((__raw_readl(reg) & ~(val)), reg);
  274. }
  275. static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
  276. {
  277. __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
  278. }
  279. static inline void mcasp_set_reg(void __iomem *reg, u32 val)
  280. {
  281. __raw_writel(val, reg);
  282. }
  283. static inline u32 mcasp_get_reg(void __iomem *reg)
  284. {
  285. return (unsigned int)__raw_readl(reg);
  286. }
  287. static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
  288. {
  289. int i = 0;
  290. mcasp_set_bits(regs, val);
  291. /* programming GBLCTL needs to read back from GBLCTL and verfiy */
  292. /* loop count is to avoid the lock-up */
  293. for (i = 0; i < 1000; i++) {
  294. if ((mcasp_get_reg(regs) & val) == val)
  295. break;
  296. }
  297. if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
  298. printk(KERN_ERR "GBLCTL write error\n");
  299. }
  300. static void mcasp_start_rx(struct davinci_audio_dev *dev)
  301. {
  302. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
  303. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
  304. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
  305. mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
  306. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
  307. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
  308. mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
  309. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
  310. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
  311. }
  312. static void mcasp_start_tx(struct davinci_audio_dev *dev)
  313. {
  314. u8 offset = 0, i;
  315. u32 cnt;
  316. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
  317. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
  318. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
  319. mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
  320. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
  321. mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
  322. mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
  323. for (i = 0; i < dev->num_serializer; i++) {
  324. if (dev->serial_dir[i] == TX_MODE) {
  325. offset = i;
  326. break;
  327. }
  328. }
  329. /* wait for TX ready */
  330. cnt = 0;
  331. while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
  332. TXSTATE) && (cnt < 100000))
  333. cnt++;
  334. mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
  335. }
  336. static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
  337. {
  338. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  339. if (dev->txnumevt) { /* enable FIFO */
  340. switch (dev->version) {
  341. case MCASP_VERSION_3:
  342. mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
  343. FIFO_ENABLE);
  344. mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
  345. FIFO_ENABLE);
  346. break;
  347. default:
  348. mcasp_clr_bits(dev->base +
  349. DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
  350. mcasp_set_bits(dev->base +
  351. DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
  352. }
  353. }
  354. mcasp_start_tx(dev);
  355. } else {
  356. if (dev->rxnumevt) { /* enable FIFO */
  357. switch (dev->version) {
  358. case MCASP_VERSION_3:
  359. mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
  360. FIFO_ENABLE);
  361. mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
  362. FIFO_ENABLE);
  363. break;
  364. default:
  365. mcasp_clr_bits(dev->base +
  366. DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
  367. mcasp_set_bits(dev->base +
  368. DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
  369. }
  370. }
  371. mcasp_start_rx(dev);
  372. }
  373. }
  374. static void mcasp_stop_rx(struct davinci_audio_dev *dev)
  375. {
  376. mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
  377. mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
  378. }
  379. static void mcasp_stop_tx(struct davinci_audio_dev *dev)
  380. {
  381. mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
  382. mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
  383. }
  384. static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
  385. {
  386. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  387. if (dev->txnumevt) { /* disable FIFO */
  388. switch (dev->version) {
  389. case MCASP_VERSION_3:
  390. mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
  391. FIFO_ENABLE);
  392. break;
  393. default:
  394. mcasp_clr_bits(dev->base +
  395. DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
  396. }
  397. }
  398. mcasp_stop_tx(dev);
  399. } else {
  400. if (dev->rxnumevt) { /* disable FIFO */
  401. switch (dev->version) {
  402. case MCASP_VERSION_3:
  403. mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
  404. FIFO_ENABLE);
  405. break;
  406. default:
  407. mcasp_clr_bits(dev->base +
  408. DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
  409. }
  410. }
  411. mcasp_stop_rx(dev);
  412. }
  413. }
  414. static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  415. unsigned int fmt)
  416. {
  417. struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
  418. void __iomem *base = dev->base;
  419. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  420. case SND_SOC_DAIFMT_DSP_B:
  421. case SND_SOC_DAIFMT_AC97:
  422. mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
  423. mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
  424. break;
  425. default:
  426. /* configure a full-word SYNC pulse (LRCLK) */
  427. mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
  428. mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
  429. /* make 1st data bit occur one ACLK cycle after the frame sync */
  430. mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
  431. mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
  432. break;
  433. }
  434. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  435. case SND_SOC_DAIFMT_CBS_CFS:
  436. /* codec is clock and frame slave */
  437. mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
  438. mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
  439. mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
  440. mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
  441. mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, ACLKX | AFSX);
  442. break;
  443. case SND_SOC_DAIFMT_CBM_CFS:
  444. /* codec is clock master and frame slave */
  445. mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
  446. mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
  447. mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
  448. mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
  449. mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
  450. ACLKX | ACLKR);
  451. mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
  452. AFSX | AFSR);
  453. break;
  454. case SND_SOC_DAIFMT_CBM_CFM:
  455. /* codec is clock and frame master */
  456. mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
  457. mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
  458. mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
  459. mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
  460. mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
  461. ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
  462. break;
  463. default:
  464. return -EINVAL;
  465. }
  466. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  467. case SND_SOC_DAIFMT_IB_NF:
  468. mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
  469. mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
  470. mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
  471. mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
  472. break;
  473. case SND_SOC_DAIFMT_NB_IF:
  474. mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
  475. mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
  476. mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
  477. mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
  478. break;
  479. case SND_SOC_DAIFMT_IB_IF:
  480. mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
  481. mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
  482. mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
  483. mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
  484. break;
  485. case SND_SOC_DAIFMT_NB_NF:
  486. mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
  487. mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
  488. mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
  489. mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
  490. break;
  491. default:
  492. return -EINVAL;
  493. }
  494. return 0;
  495. }
  496. static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
  497. {
  498. struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
  499. switch (div_id) {
  500. case 0: /* MCLK divider */
  501. mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
  502. AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
  503. mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
  504. AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
  505. break;
  506. case 1: /* BCLK divider */
  507. mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
  508. ACLKXDIV(div - 1), ACLKXDIV_MASK);
  509. mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
  510. ACLKRDIV(div - 1), ACLKRDIV_MASK);
  511. break;
  512. case 2: /* BCLK/LRCLK ratio */
  513. dev->bclk_lrclk_ratio = div;
  514. break;
  515. default:
  516. return -EINVAL;
  517. }
  518. return 0;
  519. }
  520. static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  521. unsigned int freq, int dir)
  522. {
  523. struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
  524. if (dir == SND_SOC_CLOCK_OUT) {
  525. mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
  526. mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
  527. mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
  528. } else {
  529. mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
  530. mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
  531. mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
  532. }
  533. return 0;
  534. }
  535. static int davinci_config_channel_size(struct davinci_audio_dev *dev,
  536. int word_length)
  537. {
  538. u32 fmt;
  539. u32 rotate = (word_length / 4) & 0x7;
  540. u32 mask = (1ULL << word_length) - 1;
  541. /*
  542. * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
  543. * callback, take it into account here. That allows us to for example
  544. * send 32 bits per channel to the codec, while only 16 of them carry
  545. * audio payload.
  546. * The clock ratio is given for a full period of data (both left and
  547. * right channels), so it has to be divided by 2.
  548. */
  549. if (dev->bclk_lrclk_ratio)
  550. word_length = dev->bclk_lrclk_ratio / 2;
  551. /* mapping of the XSSZ bit-field as described in the datasheet */
  552. fmt = (word_length >> 1) - 1;
  553. mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
  554. RXSSZ(fmt), RXSSZ(0x0F));
  555. mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
  556. TXSSZ(fmt), TXSSZ(0x0F));
  557. mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
  558. TXROT(7));
  559. mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
  560. RXROT(7));
  561. mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
  562. mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
  563. return 0;
  564. }
  565. static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream,
  566. int channels)
  567. {
  568. int i;
  569. u8 tx_ser = 0;
  570. u8 rx_ser = 0;
  571. u8 ser;
  572. u8 slots = dev->tdm_slots;
  573. u8 max_active_serializers = (channels + slots - 1) / slots;
  574. /* Default configuration */
  575. mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
  576. /* All PINS as McASP */
  577. mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
  578. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  579. mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
  580. mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
  581. TXDATADMADIS);
  582. } else {
  583. mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
  584. mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
  585. RXDATADMADIS);
  586. }
  587. for (i = 0; i < dev->num_serializer; i++) {
  588. if (dev->serial_dir[i] == TX_MODE)
  589. tx_ser++;
  590. if (dev->serial_dir[i] == RX_MODE)
  591. rx_ser++;
  592. }
  593. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  594. ser = tx_ser;
  595. else
  596. ser = rx_ser;
  597. if (ser < max_active_serializers) {
  598. dev_warn(dev->dev, "stream has more channels (%d) than are "
  599. "enabled in mcasp (%d)\n", channels, ser * slots);
  600. return -EINVAL;
  601. }
  602. tx_ser = 0;
  603. rx_ser = 0;
  604. for (i = 0; i < dev->num_serializer; i++) {
  605. mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
  606. dev->serial_dir[i]);
  607. if (dev->serial_dir[i] == TX_MODE &&
  608. tx_ser < max_active_serializers) {
  609. mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
  610. AXR(i));
  611. tx_ser++;
  612. } else if (dev->serial_dir[i] == RX_MODE &&
  613. rx_ser < max_active_serializers) {
  614. mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
  615. AXR(i));
  616. rx_ser++;
  617. } else {
  618. mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
  619. SRMOD_INACTIVE, SRMOD_MASK);
  620. }
  621. }
  622. if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
  623. if (dev->txnumevt * tx_ser > 64)
  624. dev->txnumevt = 1;
  625. switch (dev->version) {
  626. case MCASP_VERSION_3:
  627. mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
  628. NUMDMA_MASK);
  629. mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
  630. ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
  631. break;
  632. default:
  633. mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
  634. tx_ser, NUMDMA_MASK);
  635. mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
  636. ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
  637. }
  638. }
  639. if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
  640. if (dev->rxnumevt * rx_ser > 64)
  641. dev->rxnumevt = 1;
  642. switch (dev->version) {
  643. case MCASP_VERSION_3:
  644. mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
  645. NUMDMA_MASK);
  646. mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
  647. ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
  648. break;
  649. default:
  650. mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
  651. rx_ser, NUMDMA_MASK);
  652. mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
  653. ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
  654. }
  655. }
  656. return 0;
  657. }
  658. static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
  659. {
  660. int i, active_slots;
  661. u32 mask = 0;
  662. active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
  663. for (i = 0; i < active_slots; i++)
  664. mask |= (1 << i);
  665. mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
  666. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  667. /* bit stream is MSB first with no delay */
  668. /* DSP_B mode */
  669. mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
  670. mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
  671. if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
  672. mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
  673. FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
  674. else
  675. printk(KERN_ERR "playback tdm slot %d not supported\n",
  676. dev->tdm_slots);
  677. } else {
  678. /* bit stream is MSB first with no delay */
  679. /* DSP_B mode */
  680. mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
  681. mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
  682. if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
  683. mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
  684. FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
  685. else
  686. printk(KERN_ERR "capture tdm slot %d not supported\n",
  687. dev->tdm_slots);
  688. }
  689. }
  690. /* S/PDIF */
  691. static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
  692. {
  693. /* Set the PDIR for Serialiser as output */
  694. mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
  695. /* TXMASK for 24 bits */
  696. mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
  697. /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
  698. and LSB first */
  699. mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
  700. TXROT(6) | TXSSZ(15));
  701. /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
  702. mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
  703. AFSXE | FSXMOD(0x180));
  704. /* Set the TX tdm : for all the slots */
  705. mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
  706. /* Set the TX clock controls : div = 1 and internal */
  707. mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
  708. ACLKXE | TX_ASYNC);
  709. mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
  710. /* Only 44100 and 48000 are valid, both have the same setting */
  711. mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
  712. /* Enable the DIT */
  713. mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
  714. }
  715. static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
  716. struct snd_pcm_hw_params *params,
  717. struct snd_soc_dai *cpu_dai)
  718. {
  719. struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
  720. struct davinci_pcm_dma_params *dma_params =
  721. &dev->dma_params[substream->stream];
  722. int word_length;
  723. u8 fifo_level;
  724. u8 slots = dev->tdm_slots;
  725. int channels;
  726. struct snd_interval *pcm_channels = hw_param_interval(params,
  727. SNDRV_PCM_HW_PARAM_CHANNELS);
  728. channels = pcm_channels->min;
  729. if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL)
  730. return -EINVAL;
  731. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  732. fifo_level = dev->txnumevt;
  733. else
  734. fifo_level = dev->rxnumevt;
  735. if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
  736. davinci_hw_dit_param(dev);
  737. else
  738. davinci_hw_param(dev, substream->stream);
  739. switch (params_format(params)) {
  740. case SNDRV_PCM_FORMAT_U8:
  741. case SNDRV_PCM_FORMAT_S8:
  742. dma_params->data_type = 1;
  743. word_length = 8;
  744. break;
  745. case SNDRV_PCM_FORMAT_U16_LE:
  746. case SNDRV_PCM_FORMAT_S16_LE:
  747. dma_params->data_type = 2;
  748. word_length = 16;
  749. break;
  750. case SNDRV_PCM_FORMAT_U24_3LE:
  751. case SNDRV_PCM_FORMAT_S24_3LE:
  752. dma_params->data_type = 3;
  753. word_length = 24;
  754. break;
  755. case SNDRV_PCM_FORMAT_U24_LE:
  756. case SNDRV_PCM_FORMAT_S24_LE:
  757. case SNDRV_PCM_FORMAT_U32_LE:
  758. case SNDRV_PCM_FORMAT_S32_LE:
  759. dma_params->data_type = 4;
  760. word_length = 32;
  761. break;
  762. default:
  763. printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
  764. return -EINVAL;
  765. }
  766. if (dev->version == MCASP_VERSION_2 && !fifo_level)
  767. dma_params->acnt = 4;
  768. else
  769. dma_params->acnt = dma_params->data_type;
  770. dma_params->fifo_level = fifo_level;
  771. dma_params->active_serializers = (channels + slots - 1) / slots;
  772. davinci_config_channel_size(dev, word_length);
  773. return 0;
  774. }
  775. static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
  776. int cmd, struct snd_soc_dai *cpu_dai)
  777. {
  778. struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
  779. int ret = 0;
  780. switch (cmd) {
  781. case SNDRV_PCM_TRIGGER_RESUME:
  782. case SNDRV_PCM_TRIGGER_START:
  783. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  784. ret = pm_runtime_get_sync(dev->dev);
  785. if (IS_ERR_VALUE(ret))
  786. dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
  787. davinci_mcasp_start(dev, substream->stream);
  788. break;
  789. case SNDRV_PCM_TRIGGER_SUSPEND:
  790. davinci_mcasp_stop(dev, substream->stream);
  791. ret = pm_runtime_put_sync(dev->dev);
  792. if (IS_ERR_VALUE(ret))
  793. dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
  794. break;
  795. case SNDRV_PCM_TRIGGER_STOP:
  796. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  797. davinci_mcasp_stop(dev, substream->stream);
  798. break;
  799. default:
  800. ret = -EINVAL;
  801. }
  802. return ret;
  803. }
  804. static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
  805. struct snd_soc_dai *dai)
  806. {
  807. struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
  808. snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
  809. return 0;
  810. }
  811. static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
  812. .startup = davinci_mcasp_startup,
  813. .trigger = davinci_mcasp_trigger,
  814. .hw_params = davinci_mcasp_hw_params,
  815. .set_fmt = davinci_mcasp_set_dai_fmt,
  816. .set_clkdiv = davinci_mcasp_set_clkdiv,
  817. .set_sysclk = davinci_mcasp_set_sysclk,
  818. };
  819. #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
  820. SNDRV_PCM_FMTBIT_U8 | \
  821. SNDRV_PCM_FMTBIT_S16_LE | \
  822. SNDRV_PCM_FMTBIT_U16_LE | \
  823. SNDRV_PCM_FMTBIT_S24_LE | \
  824. SNDRV_PCM_FMTBIT_U24_LE | \
  825. SNDRV_PCM_FMTBIT_S24_3LE | \
  826. SNDRV_PCM_FMTBIT_U24_3LE | \
  827. SNDRV_PCM_FMTBIT_S32_LE | \
  828. SNDRV_PCM_FMTBIT_U32_LE)
  829. static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
  830. {
  831. .name = "davinci-mcasp.0",
  832. .playback = {
  833. .channels_min = 2,
  834. .channels_max = 32 * 16,
  835. .rates = DAVINCI_MCASP_RATES,
  836. .formats = DAVINCI_MCASP_PCM_FMTS,
  837. },
  838. .capture = {
  839. .channels_min = 2,
  840. .channels_max = 32 * 16,
  841. .rates = DAVINCI_MCASP_RATES,
  842. .formats = DAVINCI_MCASP_PCM_FMTS,
  843. },
  844. .ops = &davinci_mcasp_dai_ops,
  845. },
  846. {
  847. "davinci-mcasp.1",
  848. .playback = {
  849. .channels_min = 1,
  850. .channels_max = 384,
  851. .rates = DAVINCI_MCASP_RATES,
  852. .formats = DAVINCI_MCASP_PCM_FMTS,
  853. },
  854. .ops = &davinci_mcasp_dai_ops,
  855. },
  856. };
  857. static const struct of_device_id mcasp_dt_ids[] = {
  858. {
  859. .compatible = "ti,dm646x-mcasp-audio",
  860. .data = (void *)MCASP_VERSION_1,
  861. },
  862. {
  863. .compatible = "ti,da830-mcasp-audio",
  864. .data = (void *)MCASP_VERSION_2,
  865. },
  866. {
  867. .compatible = "ti,omap2-mcasp-audio",
  868. .data = (void *)MCASP_VERSION_3,
  869. },
  870. { /* sentinel */ }
  871. };
  872. MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
  873. static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
  874. struct platform_device *pdev)
  875. {
  876. struct device_node *np = pdev->dev.of_node;
  877. struct snd_platform_data *pdata = NULL;
  878. const struct of_device_id *match =
  879. of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev);
  880. const u32 *of_serial_dir32;
  881. u8 *of_serial_dir;
  882. u32 val;
  883. int i, ret = 0;
  884. if (pdev->dev.platform_data) {
  885. pdata = pdev->dev.platform_data;
  886. return pdata;
  887. } else if (match) {
  888. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  889. if (!pdata) {
  890. ret = -ENOMEM;
  891. goto nodata;
  892. }
  893. } else {
  894. /* control shouldn't reach here. something is wrong */
  895. ret = -EINVAL;
  896. goto nodata;
  897. }
  898. if (match->data)
  899. pdata->version = (u8)((int)match->data);
  900. ret = of_property_read_u32(np, "op-mode", &val);
  901. if (ret >= 0)
  902. pdata->op_mode = val;
  903. ret = of_property_read_u32(np, "tdm-slots", &val);
  904. if (ret >= 0) {
  905. if (val < 2 || val > 32) {
  906. dev_err(&pdev->dev,
  907. "tdm-slots must be in rage [2-32]\n");
  908. ret = -EINVAL;
  909. goto nodata;
  910. }
  911. pdata->tdm_slots = val;
  912. }
  913. ret = of_property_read_u32(np, "num-serializer", &val);
  914. if (ret >= 0)
  915. pdata->num_serializer = val;
  916. of_serial_dir32 = of_get_property(np, "serial-dir", &val);
  917. val /= sizeof(u32);
  918. if (val != pdata->num_serializer) {
  919. dev_err(&pdev->dev,
  920. "num-serializer(%d) != serial-dir size(%d)\n",
  921. pdata->num_serializer, val);
  922. ret = -EINVAL;
  923. goto nodata;
  924. }
  925. if (of_serial_dir32) {
  926. of_serial_dir = devm_kzalloc(&pdev->dev,
  927. (sizeof(*of_serial_dir) * val),
  928. GFP_KERNEL);
  929. if (!of_serial_dir) {
  930. ret = -ENOMEM;
  931. goto nodata;
  932. }
  933. for (i = 0; i < pdata->num_serializer; i++)
  934. of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
  935. pdata->serial_dir = of_serial_dir;
  936. }
  937. ret = of_property_read_u32(np, "tx-num-evt", &val);
  938. if (ret >= 0)
  939. pdata->txnumevt = val;
  940. ret = of_property_read_u32(np, "rx-num-evt", &val);
  941. if (ret >= 0)
  942. pdata->rxnumevt = val;
  943. ret = of_property_read_u32(np, "sram-size-playback", &val);
  944. if (ret >= 0)
  945. pdata->sram_size_playback = val;
  946. ret = of_property_read_u32(np, "sram-size-capture", &val);
  947. if (ret >= 0)
  948. pdata->sram_size_capture = val;
  949. return pdata;
  950. nodata:
  951. if (ret < 0) {
  952. dev_err(&pdev->dev, "Error populating platform data, err %d\n",
  953. ret);
  954. pdata = NULL;
  955. }
  956. return pdata;
  957. }
  958. static int davinci_mcasp_probe(struct platform_device *pdev)
  959. {
  960. struct davinci_pcm_dma_params *dma_data;
  961. struct resource *mem, *ioarea, *res;
  962. struct snd_platform_data *pdata;
  963. struct davinci_audio_dev *dev;
  964. int ret;
  965. if (!pdev->dev.platform_data && !pdev->dev.of_node) {
  966. dev_err(&pdev->dev, "No platform data supplied\n");
  967. return -EINVAL;
  968. }
  969. dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
  970. GFP_KERNEL);
  971. if (!dev)
  972. return -ENOMEM;
  973. pdata = davinci_mcasp_set_pdata_from_of(pdev);
  974. if (!pdata) {
  975. dev_err(&pdev->dev, "no platform data\n");
  976. return -EINVAL;
  977. }
  978. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  979. if (!mem) {
  980. dev_err(&pdev->dev, "no mem resource?\n");
  981. return -ENODEV;
  982. }
  983. ioarea = devm_request_mem_region(&pdev->dev, mem->start,
  984. resource_size(mem), pdev->name);
  985. if (!ioarea) {
  986. dev_err(&pdev->dev, "Audio region already claimed\n");
  987. return -EBUSY;
  988. }
  989. pm_runtime_enable(&pdev->dev);
  990. ret = pm_runtime_get_sync(&pdev->dev);
  991. if (IS_ERR_VALUE(ret)) {
  992. dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
  993. return ret;
  994. }
  995. dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
  996. if (!dev->base) {
  997. dev_err(&pdev->dev, "ioremap failed\n");
  998. ret = -ENOMEM;
  999. goto err_release_clk;
  1000. }
  1001. dev->op_mode = pdata->op_mode;
  1002. dev->tdm_slots = pdata->tdm_slots;
  1003. dev->num_serializer = pdata->num_serializer;
  1004. dev->serial_dir = pdata->serial_dir;
  1005. dev->version = pdata->version;
  1006. dev->txnumevt = pdata->txnumevt;
  1007. dev->rxnumevt = pdata->rxnumevt;
  1008. dev->dev = &pdev->dev;
  1009. dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
  1010. dma_data->asp_chan_q = pdata->asp_chan_q;
  1011. dma_data->ram_chan_q = pdata->ram_chan_q;
  1012. dma_data->sram_pool = pdata->sram_pool;
  1013. dma_data->sram_size = pdata->sram_size_playback;
  1014. dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
  1015. mem->start);
  1016. /* first TX, then RX */
  1017. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  1018. if (!res) {
  1019. dev_err(&pdev->dev, "no DMA resource\n");
  1020. ret = -ENODEV;
  1021. goto err_release_clk;
  1022. }
  1023. dma_data->channel = res->start;
  1024. dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
  1025. dma_data->asp_chan_q = pdata->asp_chan_q;
  1026. dma_data->ram_chan_q = pdata->ram_chan_q;
  1027. dma_data->sram_pool = pdata->sram_pool;
  1028. dma_data->sram_size = pdata->sram_size_capture;
  1029. dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
  1030. mem->start);
  1031. res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  1032. if (!res) {
  1033. dev_err(&pdev->dev, "no DMA resource\n");
  1034. ret = -ENODEV;
  1035. goto err_release_clk;
  1036. }
  1037. dma_data->channel = res->start;
  1038. dev_set_drvdata(&pdev->dev, dev);
  1039. ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
  1040. if (ret != 0)
  1041. goto err_release_clk;
  1042. ret = davinci_soc_platform_register(&pdev->dev);
  1043. if (ret) {
  1044. dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
  1045. goto err_unregister_dai;
  1046. }
  1047. return 0;
  1048. err_unregister_dai:
  1049. snd_soc_unregister_dai(&pdev->dev);
  1050. err_release_clk:
  1051. pm_runtime_put_sync(&pdev->dev);
  1052. pm_runtime_disable(&pdev->dev);
  1053. return ret;
  1054. }
  1055. static int davinci_mcasp_remove(struct platform_device *pdev)
  1056. {
  1057. snd_soc_unregister_dai(&pdev->dev);
  1058. davinci_soc_platform_unregister(&pdev->dev);
  1059. pm_runtime_put_sync(&pdev->dev);
  1060. pm_runtime_disable(&pdev->dev);
  1061. return 0;
  1062. }
  1063. static struct platform_driver davinci_mcasp_driver = {
  1064. .probe = davinci_mcasp_probe,
  1065. .remove = davinci_mcasp_remove,
  1066. .driver = {
  1067. .name = "davinci-mcasp",
  1068. .owner = THIS_MODULE,
  1069. .of_match_table = of_match_ptr(mcasp_dt_ids),
  1070. },
  1071. };
  1072. module_platform_driver(davinci_mcasp_driver);
  1073. MODULE_AUTHOR("Steve Chen");
  1074. MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
  1075. MODULE_LICENSE("GPL");