intel_display.c 222 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/module.h>
  27. #include <linux/input.h>
  28. #include <linux/i2c.h>
  29. #include <linux/kernel.h>
  30. #include <linux/slab.h>
  31. #include <linux/vgaarb.h>
  32. #include "drmP.h"
  33. #include "intel_drv.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36. #include "i915_trace.h"
  37. #include "drm_dp_helper.h"
  38. #include "drm_crtc_helper.h"
  39. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40. bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  41. static void intel_update_watermarks(struct drm_device *dev);
  42. static void intel_increase_pllclock(struct drm_crtc *crtc);
  43. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  44. typedef struct {
  45. /* given values */
  46. int n;
  47. int m1, m2;
  48. int p1, p2;
  49. /* derived values */
  50. int dot;
  51. int vco;
  52. int m;
  53. int p;
  54. } intel_clock_t;
  55. typedef struct {
  56. int min, max;
  57. } intel_range_t;
  58. typedef struct {
  59. int dot_limit;
  60. int p2_slow, p2_fast;
  61. } intel_p2_t;
  62. #define INTEL_P2_NUM 2
  63. typedef struct intel_limit intel_limit_t;
  64. struct intel_limit {
  65. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  66. intel_p2_t p2;
  67. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  68. int, int, intel_clock_t *);
  69. };
  70. /* FDI */
  71. #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
  72. static bool
  73. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  74. int target, int refclk, intel_clock_t *best_clock);
  75. static bool
  76. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  77. int target, int refclk, intel_clock_t *best_clock);
  78. static bool
  79. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  80. int target, int refclk, intel_clock_t *best_clock);
  81. static bool
  82. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  83. int target, int refclk, intel_clock_t *best_clock);
  84. static inline u32 /* units of 100MHz */
  85. intel_fdi_link_freq(struct drm_device *dev)
  86. {
  87. if (IS_GEN5(dev)) {
  88. struct drm_i915_private *dev_priv = dev->dev_private;
  89. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  90. } else
  91. return 27;
  92. }
  93. static const intel_limit_t intel_limits_i8xx_dvo = {
  94. .dot = { .min = 25000, .max = 350000 },
  95. .vco = { .min = 930000, .max = 1400000 },
  96. .n = { .min = 3, .max = 16 },
  97. .m = { .min = 96, .max = 140 },
  98. .m1 = { .min = 18, .max = 26 },
  99. .m2 = { .min = 6, .max = 16 },
  100. .p = { .min = 4, .max = 128 },
  101. .p1 = { .min = 2, .max = 33 },
  102. .p2 = { .dot_limit = 165000,
  103. .p2_slow = 4, .p2_fast = 2 },
  104. .find_pll = intel_find_best_PLL,
  105. };
  106. static const intel_limit_t intel_limits_i8xx_lvds = {
  107. .dot = { .min = 25000, .max = 350000 },
  108. .vco = { .min = 930000, .max = 1400000 },
  109. .n = { .min = 3, .max = 16 },
  110. .m = { .min = 96, .max = 140 },
  111. .m1 = { .min = 18, .max = 26 },
  112. .m2 = { .min = 6, .max = 16 },
  113. .p = { .min = 4, .max = 128 },
  114. .p1 = { .min = 1, .max = 6 },
  115. .p2 = { .dot_limit = 165000,
  116. .p2_slow = 14, .p2_fast = 7 },
  117. .find_pll = intel_find_best_PLL,
  118. };
  119. static const intel_limit_t intel_limits_i9xx_sdvo = {
  120. .dot = { .min = 20000, .max = 400000 },
  121. .vco = { .min = 1400000, .max = 2800000 },
  122. .n = { .min = 1, .max = 6 },
  123. .m = { .min = 70, .max = 120 },
  124. .m1 = { .min = 10, .max = 22 },
  125. .m2 = { .min = 5, .max = 9 },
  126. .p = { .min = 5, .max = 80 },
  127. .p1 = { .min = 1, .max = 8 },
  128. .p2 = { .dot_limit = 200000,
  129. .p2_slow = 10, .p2_fast = 5 },
  130. .find_pll = intel_find_best_PLL,
  131. };
  132. static const intel_limit_t intel_limits_i9xx_lvds = {
  133. .dot = { .min = 20000, .max = 400000 },
  134. .vco = { .min = 1400000, .max = 2800000 },
  135. .n = { .min = 1, .max = 6 },
  136. .m = { .min = 70, .max = 120 },
  137. .m1 = { .min = 10, .max = 22 },
  138. .m2 = { .min = 5, .max = 9 },
  139. .p = { .min = 7, .max = 98 },
  140. .p1 = { .min = 1, .max = 8 },
  141. .p2 = { .dot_limit = 112000,
  142. .p2_slow = 14, .p2_fast = 7 },
  143. .find_pll = intel_find_best_PLL,
  144. };
  145. static const intel_limit_t intel_limits_g4x_sdvo = {
  146. .dot = { .min = 25000, .max = 270000 },
  147. .vco = { .min = 1750000, .max = 3500000},
  148. .n = { .min = 1, .max = 4 },
  149. .m = { .min = 104, .max = 138 },
  150. .m1 = { .min = 17, .max = 23 },
  151. .m2 = { .min = 5, .max = 11 },
  152. .p = { .min = 10, .max = 30 },
  153. .p1 = { .min = 1, .max = 3},
  154. .p2 = { .dot_limit = 270000,
  155. .p2_slow = 10,
  156. .p2_fast = 10
  157. },
  158. .find_pll = intel_g4x_find_best_PLL,
  159. };
  160. static const intel_limit_t intel_limits_g4x_hdmi = {
  161. .dot = { .min = 22000, .max = 400000 },
  162. .vco = { .min = 1750000, .max = 3500000},
  163. .n = { .min = 1, .max = 4 },
  164. .m = { .min = 104, .max = 138 },
  165. .m1 = { .min = 16, .max = 23 },
  166. .m2 = { .min = 5, .max = 11 },
  167. .p = { .min = 5, .max = 80 },
  168. .p1 = { .min = 1, .max = 8},
  169. .p2 = { .dot_limit = 165000,
  170. .p2_slow = 10, .p2_fast = 5 },
  171. .find_pll = intel_g4x_find_best_PLL,
  172. };
  173. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  174. .dot = { .min = 20000, .max = 115000 },
  175. .vco = { .min = 1750000, .max = 3500000 },
  176. .n = { .min = 1, .max = 3 },
  177. .m = { .min = 104, .max = 138 },
  178. .m1 = { .min = 17, .max = 23 },
  179. .m2 = { .min = 5, .max = 11 },
  180. .p = { .min = 28, .max = 112 },
  181. .p1 = { .min = 2, .max = 8 },
  182. .p2 = { .dot_limit = 0,
  183. .p2_slow = 14, .p2_fast = 14
  184. },
  185. .find_pll = intel_g4x_find_best_PLL,
  186. };
  187. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  188. .dot = { .min = 80000, .max = 224000 },
  189. .vco = { .min = 1750000, .max = 3500000 },
  190. .n = { .min = 1, .max = 3 },
  191. .m = { .min = 104, .max = 138 },
  192. .m1 = { .min = 17, .max = 23 },
  193. .m2 = { .min = 5, .max = 11 },
  194. .p = { .min = 14, .max = 42 },
  195. .p1 = { .min = 2, .max = 6 },
  196. .p2 = { .dot_limit = 0,
  197. .p2_slow = 7, .p2_fast = 7
  198. },
  199. .find_pll = intel_g4x_find_best_PLL,
  200. };
  201. static const intel_limit_t intel_limits_g4x_display_port = {
  202. .dot = { .min = 161670, .max = 227000 },
  203. .vco = { .min = 1750000, .max = 3500000},
  204. .n = { .min = 1, .max = 2 },
  205. .m = { .min = 97, .max = 108 },
  206. .m1 = { .min = 0x10, .max = 0x12 },
  207. .m2 = { .min = 0x05, .max = 0x06 },
  208. .p = { .min = 10, .max = 20 },
  209. .p1 = { .min = 1, .max = 2},
  210. .p2 = { .dot_limit = 0,
  211. .p2_slow = 10, .p2_fast = 10 },
  212. .find_pll = intel_find_pll_g4x_dp,
  213. };
  214. static const intel_limit_t intel_limits_pineview_sdvo = {
  215. .dot = { .min = 20000, .max = 400000},
  216. .vco = { .min = 1700000, .max = 3500000 },
  217. /* Pineview's Ncounter is a ring counter */
  218. .n = { .min = 3, .max = 6 },
  219. .m = { .min = 2, .max = 256 },
  220. /* Pineview only has one combined m divider, which we treat as m2. */
  221. .m1 = { .min = 0, .max = 0 },
  222. .m2 = { .min = 0, .max = 254 },
  223. .p = { .min = 5, .max = 80 },
  224. .p1 = { .min = 1, .max = 8 },
  225. .p2 = { .dot_limit = 200000,
  226. .p2_slow = 10, .p2_fast = 5 },
  227. .find_pll = intel_find_best_PLL,
  228. };
  229. static const intel_limit_t intel_limits_pineview_lvds = {
  230. .dot = { .min = 20000, .max = 400000 },
  231. .vco = { .min = 1700000, .max = 3500000 },
  232. .n = { .min = 3, .max = 6 },
  233. .m = { .min = 2, .max = 256 },
  234. .m1 = { .min = 0, .max = 0 },
  235. .m2 = { .min = 0, .max = 254 },
  236. .p = { .min = 7, .max = 112 },
  237. .p1 = { .min = 1, .max = 8 },
  238. .p2 = { .dot_limit = 112000,
  239. .p2_slow = 14, .p2_fast = 14 },
  240. .find_pll = intel_find_best_PLL,
  241. };
  242. /* Ironlake / Sandybridge
  243. *
  244. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  245. * the range value for them is (actual_value - 2).
  246. */
  247. static const intel_limit_t intel_limits_ironlake_dac = {
  248. .dot = { .min = 25000, .max = 350000 },
  249. .vco = { .min = 1760000, .max = 3510000 },
  250. .n = { .min = 1, .max = 5 },
  251. .m = { .min = 79, .max = 127 },
  252. .m1 = { .min = 12, .max = 22 },
  253. .m2 = { .min = 5, .max = 9 },
  254. .p = { .min = 5, .max = 80 },
  255. .p1 = { .min = 1, .max = 8 },
  256. .p2 = { .dot_limit = 225000,
  257. .p2_slow = 10, .p2_fast = 5 },
  258. .find_pll = intel_g4x_find_best_PLL,
  259. };
  260. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  261. .dot = { .min = 25000, .max = 350000 },
  262. .vco = { .min = 1760000, .max = 3510000 },
  263. .n = { .min = 1, .max = 3 },
  264. .m = { .min = 79, .max = 118 },
  265. .m1 = { .min = 12, .max = 22 },
  266. .m2 = { .min = 5, .max = 9 },
  267. .p = { .min = 28, .max = 112 },
  268. .p1 = { .min = 2, .max = 8 },
  269. .p2 = { .dot_limit = 225000,
  270. .p2_slow = 14, .p2_fast = 14 },
  271. .find_pll = intel_g4x_find_best_PLL,
  272. };
  273. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  274. .dot = { .min = 25000, .max = 350000 },
  275. .vco = { .min = 1760000, .max = 3510000 },
  276. .n = { .min = 1, .max = 3 },
  277. .m = { .min = 79, .max = 127 },
  278. .m1 = { .min = 12, .max = 22 },
  279. .m2 = { .min = 5, .max = 9 },
  280. .p = { .min = 14, .max = 56 },
  281. .p1 = { .min = 2, .max = 8 },
  282. .p2 = { .dot_limit = 225000,
  283. .p2_slow = 7, .p2_fast = 7 },
  284. .find_pll = intel_g4x_find_best_PLL,
  285. };
  286. /* LVDS 100mhz refclk limits. */
  287. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  288. .dot = { .min = 25000, .max = 350000 },
  289. .vco = { .min = 1760000, .max = 3510000 },
  290. .n = { .min = 1, .max = 2 },
  291. .m = { .min = 79, .max = 126 },
  292. .m1 = { .min = 12, .max = 22 },
  293. .m2 = { .min = 5, .max = 9 },
  294. .p = { .min = 28, .max = 112 },
  295. .p1 = { .min = 2,.max = 8 },
  296. .p2 = { .dot_limit = 225000,
  297. .p2_slow = 14, .p2_fast = 14 },
  298. .find_pll = intel_g4x_find_best_PLL,
  299. };
  300. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  301. .dot = { .min = 25000, .max = 350000 },
  302. .vco = { .min = 1760000, .max = 3510000 },
  303. .n = { .min = 1, .max = 3 },
  304. .m = { .min = 79, .max = 126 },
  305. .m1 = { .min = 12, .max = 22 },
  306. .m2 = { .min = 5, .max = 9 },
  307. .p = { .min = 14, .max = 42 },
  308. .p1 = { .min = 2,.max = 6 },
  309. .p2 = { .dot_limit = 225000,
  310. .p2_slow = 7, .p2_fast = 7 },
  311. .find_pll = intel_g4x_find_best_PLL,
  312. };
  313. static const intel_limit_t intel_limits_ironlake_display_port = {
  314. .dot = { .min = 25000, .max = 350000 },
  315. .vco = { .min = 1760000, .max = 3510000},
  316. .n = { .min = 1, .max = 2 },
  317. .m = { .min = 81, .max = 90 },
  318. .m1 = { .min = 12, .max = 22 },
  319. .m2 = { .min = 5, .max = 9 },
  320. .p = { .min = 10, .max = 20 },
  321. .p1 = { .min = 1, .max = 2},
  322. .p2 = { .dot_limit = 0,
  323. .p2_slow = 10, .p2_fast = 10 },
  324. .find_pll = intel_find_pll_ironlake_dp,
  325. };
  326. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  327. int refclk)
  328. {
  329. struct drm_device *dev = crtc->dev;
  330. struct drm_i915_private *dev_priv = dev->dev_private;
  331. const intel_limit_t *limit;
  332. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  333. if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
  334. LVDS_CLKB_POWER_UP) {
  335. /* LVDS dual channel */
  336. if (refclk == 100000)
  337. limit = &intel_limits_ironlake_dual_lvds_100m;
  338. else
  339. limit = &intel_limits_ironlake_dual_lvds;
  340. } else {
  341. if (refclk == 100000)
  342. limit = &intel_limits_ironlake_single_lvds_100m;
  343. else
  344. limit = &intel_limits_ironlake_single_lvds;
  345. }
  346. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  347. HAS_eDP)
  348. limit = &intel_limits_ironlake_display_port;
  349. else
  350. limit = &intel_limits_ironlake_dac;
  351. return limit;
  352. }
  353. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  354. {
  355. struct drm_device *dev = crtc->dev;
  356. struct drm_i915_private *dev_priv = dev->dev_private;
  357. const intel_limit_t *limit;
  358. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  359. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  360. LVDS_CLKB_POWER_UP)
  361. /* LVDS with dual channel */
  362. limit = &intel_limits_g4x_dual_channel_lvds;
  363. else
  364. /* LVDS with dual channel */
  365. limit = &intel_limits_g4x_single_channel_lvds;
  366. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  367. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  368. limit = &intel_limits_g4x_hdmi;
  369. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  370. limit = &intel_limits_g4x_sdvo;
  371. } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  372. limit = &intel_limits_g4x_display_port;
  373. } else /* The option is for other outputs */
  374. limit = &intel_limits_i9xx_sdvo;
  375. return limit;
  376. }
  377. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  378. {
  379. struct drm_device *dev = crtc->dev;
  380. const intel_limit_t *limit;
  381. if (HAS_PCH_SPLIT(dev))
  382. limit = intel_ironlake_limit(crtc, refclk);
  383. else if (IS_G4X(dev)) {
  384. limit = intel_g4x_limit(crtc);
  385. } else if (IS_PINEVIEW(dev)) {
  386. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  387. limit = &intel_limits_pineview_lvds;
  388. else
  389. limit = &intel_limits_pineview_sdvo;
  390. } else if (!IS_GEN2(dev)) {
  391. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  392. limit = &intel_limits_i9xx_lvds;
  393. else
  394. limit = &intel_limits_i9xx_sdvo;
  395. } else {
  396. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  397. limit = &intel_limits_i8xx_lvds;
  398. else
  399. limit = &intel_limits_i8xx_dvo;
  400. }
  401. return limit;
  402. }
  403. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  404. static void pineview_clock(int refclk, intel_clock_t *clock)
  405. {
  406. clock->m = clock->m2 + 2;
  407. clock->p = clock->p1 * clock->p2;
  408. clock->vco = refclk * clock->m / clock->n;
  409. clock->dot = clock->vco / clock->p;
  410. }
  411. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  412. {
  413. if (IS_PINEVIEW(dev)) {
  414. pineview_clock(refclk, clock);
  415. return;
  416. }
  417. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  418. clock->p = clock->p1 * clock->p2;
  419. clock->vco = refclk * clock->m / (clock->n + 2);
  420. clock->dot = clock->vco / clock->p;
  421. }
  422. /**
  423. * Returns whether any output on the specified pipe is of the specified type
  424. */
  425. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  426. {
  427. struct drm_device *dev = crtc->dev;
  428. struct drm_mode_config *mode_config = &dev->mode_config;
  429. struct intel_encoder *encoder;
  430. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  431. if (encoder->base.crtc == crtc && encoder->type == type)
  432. return true;
  433. return false;
  434. }
  435. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  436. /**
  437. * Returns whether the given set of divisors are valid for a given refclk with
  438. * the given connectors.
  439. */
  440. static bool intel_PLL_is_valid(struct drm_device *dev,
  441. const intel_limit_t *limit,
  442. const intel_clock_t *clock)
  443. {
  444. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  445. INTELPllInvalid ("p1 out of range\n");
  446. if (clock->p < limit->p.min || limit->p.max < clock->p)
  447. INTELPllInvalid ("p out of range\n");
  448. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  449. INTELPllInvalid ("m2 out of range\n");
  450. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  451. INTELPllInvalid ("m1 out of range\n");
  452. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  453. INTELPllInvalid ("m1 <= m2\n");
  454. if (clock->m < limit->m.min || limit->m.max < clock->m)
  455. INTELPllInvalid ("m out of range\n");
  456. if (clock->n < limit->n.min || limit->n.max < clock->n)
  457. INTELPllInvalid ("n out of range\n");
  458. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  459. INTELPllInvalid ("vco out of range\n");
  460. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  461. * connector, etc., rather than just a single range.
  462. */
  463. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  464. INTELPllInvalid ("dot out of range\n");
  465. return true;
  466. }
  467. static bool
  468. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  469. int target, int refclk, intel_clock_t *best_clock)
  470. {
  471. struct drm_device *dev = crtc->dev;
  472. struct drm_i915_private *dev_priv = dev->dev_private;
  473. intel_clock_t clock;
  474. int err = target;
  475. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  476. (I915_READ(LVDS)) != 0) {
  477. /*
  478. * For LVDS, if the panel is on, just rely on its current
  479. * settings for dual-channel. We haven't figured out how to
  480. * reliably set up different single/dual channel state, if we
  481. * even can.
  482. */
  483. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  484. LVDS_CLKB_POWER_UP)
  485. clock.p2 = limit->p2.p2_fast;
  486. else
  487. clock.p2 = limit->p2.p2_slow;
  488. } else {
  489. if (target < limit->p2.dot_limit)
  490. clock.p2 = limit->p2.p2_slow;
  491. else
  492. clock.p2 = limit->p2.p2_fast;
  493. }
  494. memset (best_clock, 0, sizeof (*best_clock));
  495. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  496. clock.m1++) {
  497. for (clock.m2 = limit->m2.min;
  498. clock.m2 <= limit->m2.max; clock.m2++) {
  499. /* m1 is always 0 in Pineview */
  500. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  501. break;
  502. for (clock.n = limit->n.min;
  503. clock.n <= limit->n.max; clock.n++) {
  504. for (clock.p1 = limit->p1.min;
  505. clock.p1 <= limit->p1.max; clock.p1++) {
  506. int this_err;
  507. intel_clock(dev, refclk, &clock);
  508. if (!intel_PLL_is_valid(dev, limit,
  509. &clock))
  510. continue;
  511. this_err = abs(clock.dot - target);
  512. if (this_err < err) {
  513. *best_clock = clock;
  514. err = this_err;
  515. }
  516. }
  517. }
  518. }
  519. }
  520. return (err != target);
  521. }
  522. static bool
  523. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  524. int target, int refclk, intel_clock_t *best_clock)
  525. {
  526. struct drm_device *dev = crtc->dev;
  527. struct drm_i915_private *dev_priv = dev->dev_private;
  528. intel_clock_t clock;
  529. int max_n;
  530. bool found;
  531. /* approximately equals target * 0.00585 */
  532. int err_most = (target >> 8) + (target >> 9);
  533. found = false;
  534. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  535. int lvds_reg;
  536. if (HAS_PCH_SPLIT(dev))
  537. lvds_reg = PCH_LVDS;
  538. else
  539. lvds_reg = LVDS;
  540. if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
  541. LVDS_CLKB_POWER_UP)
  542. clock.p2 = limit->p2.p2_fast;
  543. else
  544. clock.p2 = limit->p2.p2_slow;
  545. } else {
  546. if (target < limit->p2.dot_limit)
  547. clock.p2 = limit->p2.p2_slow;
  548. else
  549. clock.p2 = limit->p2.p2_fast;
  550. }
  551. memset(best_clock, 0, sizeof(*best_clock));
  552. max_n = limit->n.max;
  553. /* based on hardware requirement, prefer smaller n to precision */
  554. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  555. /* based on hardware requirement, prefere larger m1,m2 */
  556. for (clock.m1 = limit->m1.max;
  557. clock.m1 >= limit->m1.min; clock.m1--) {
  558. for (clock.m2 = limit->m2.max;
  559. clock.m2 >= limit->m2.min; clock.m2--) {
  560. for (clock.p1 = limit->p1.max;
  561. clock.p1 >= limit->p1.min; clock.p1--) {
  562. int this_err;
  563. intel_clock(dev, refclk, &clock);
  564. if (!intel_PLL_is_valid(dev, limit,
  565. &clock))
  566. continue;
  567. this_err = abs(clock.dot - target);
  568. if (this_err < err_most) {
  569. *best_clock = clock;
  570. err_most = this_err;
  571. max_n = clock.n;
  572. found = true;
  573. }
  574. }
  575. }
  576. }
  577. }
  578. return found;
  579. }
  580. static bool
  581. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  582. int target, int refclk, intel_clock_t *best_clock)
  583. {
  584. struct drm_device *dev = crtc->dev;
  585. intel_clock_t clock;
  586. if (target < 200000) {
  587. clock.n = 1;
  588. clock.p1 = 2;
  589. clock.p2 = 10;
  590. clock.m1 = 12;
  591. clock.m2 = 9;
  592. } else {
  593. clock.n = 2;
  594. clock.p1 = 1;
  595. clock.p2 = 10;
  596. clock.m1 = 14;
  597. clock.m2 = 8;
  598. }
  599. intel_clock(dev, refclk, &clock);
  600. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  601. return true;
  602. }
  603. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  604. static bool
  605. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  606. int target, int refclk, intel_clock_t *best_clock)
  607. {
  608. intel_clock_t clock;
  609. if (target < 200000) {
  610. clock.p1 = 2;
  611. clock.p2 = 10;
  612. clock.n = 2;
  613. clock.m1 = 23;
  614. clock.m2 = 8;
  615. } else {
  616. clock.p1 = 1;
  617. clock.p2 = 10;
  618. clock.n = 1;
  619. clock.m1 = 14;
  620. clock.m2 = 2;
  621. }
  622. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  623. clock.p = (clock.p1 * clock.p2);
  624. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  625. clock.vco = 0;
  626. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  627. return true;
  628. }
  629. /**
  630. * intel_wait_for_vblank - wait for vblank on a given pipe
  631. * @dev: drm device
  632. * @pipe: pipe to wait for
  633. *
  634. * Wait for vblank to occur on a given pipe. Needed for various bits of
  635. * mode setting code.
  636. */
  637. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  638. {
  639. struct drm_i915_private *dev_priv = dev->dev_private;
  640. int pipestat_reg = PIPESTAT(pipe);
  641. /* Clear existing vblank status. Note this will clear any other
  642. * sticky status fields as well.
  643. *
  644. * This races with i915_driver_irq_handler() with the result
  645. * that either function could miss a vblank event. Here it is not
  646. * fatal, as we will either wait upon the next vblank interrupt or
  647. * timeout. Generally speaking intel_wait_for_vblank() is only
  648. * called during modeset at which time the GPU should be idle and
  649. * should *not* be performing page flips and thus not waiting on
  650. * vblanks...
  651. * Currently, the result of us stealing a vblank from the irq
  652. * handler is that a single frame will be skipped during swapbuffers.
  653. */
  654. I915_WRITE(pipestat_reg,
  655. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  656. /* Wait for vblank interrupt bit to set */
  657. if (wait_for(I915_READ(pipestat_reg) &
  658. PIPE_VBLANK_INTERRUPT_STATUS,
  659. 50))
  660. DRM_DEBUG_KMS("vblank wait timed out\n");
  661. }
  662. /*
  663. * intel_wait_for_pipe_off - wait for pipe to turn off
  664. * @dev: drm device
  665. * @pipe: pipe to wait for
  666. *
  667. * After disabling a pipe, we can't wait for vblank in the usual way,
  668. * spinning on the vblank interrupt status bit, since we won't actually
  669. * see an interrupt when the pipe is disabled.
  670. *
  671. * On Gen4 and above:
  672. * wait for the pipe register state bit to turn off
  673. *
  674. * Otherwise:
  675. * wait for the display line value to settle (it usually
  676. * ends up stopping at the start of the next frame).
  677. *
  678. */
  679. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  680. {
  681. struct drm_i915_private *dev_priv = dev->dev_private;
  682. if (INTEL_INFO(dev)->gen >= 4) {
  683. int reg = PIPECONF(pipe);
  684. /* Wait for the Pipe State to go off */
  685. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  686. 100))
  687. DRM_DEBUG_KMS("pipe_off wait timed out\n");
  688. } else {
  689. u32 last_line;
  690. int reg = PIPEDSL(pipe);
  691. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  692. /* Wait for the display line to settle */
  693. do {
  694. last_line = I915_READ(reg) & DSL_LINEMASK;
  695. mdelay(5);
  696. } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
  697. time_after(timeout, jiffies));
  698. if (time_after(jiffies, timeout))
  699. DRM_DEBUG_KMS("pipe_off wait timed out\n");
  700. }
  701. }
  702. static const char *state_string(bool enabled)
  703. {
  704. return enabled ? "on" : "off";
  705. }
  706. /* Only for pre-ILK configs */
  707. static void assert_pll(struct drm_i915_private *dev_priv,
  708. enum pipe pipe, bool state)
  709. {
  710. int reg;
  711. u32 val;
  712. bool cur_state;
  713. reg = DPLL(pipe);
  714. val = I915_READ(reg);
  715. cur_state = !!(val & DPLL_VCO_ENABLE);
  716. WARN(cur_state != state,
  717. "PLL state assertion failure (expected %s, current %s)\n",
  718. state_string(state), state_string(cur_state));
  719. }
  720. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  721. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  722. /* For ILK+ */
  723. static void assert_pch_pll(struct drm_i915_private *dev_priv,
  724. enum pipe pipe, bool state)
  725. {
  726. int reg;
  727. u32 val;
  728. bool cur_state;
  729. reg = PCH_DPLL(pipe);
  730. val = I915_READ(reg);
  731. cur_state = !!(val & DPLL_VCO_ENABLE);
  732. WARN(cur_state != state,
  733. "PCH PLL state assertion failure (expected %s, current %s)\n",
  734. state_string(state), state_string(cur_state));
  735. }
  736. #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
  737. #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
  738. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  739. enum pipe pipe, bool state)
  740. {
  741. int reg;
  742. u32 val;
  743. bool cur_state;
  744. reg = FDI_TX_CTL(pipe);
  745. val = I915_READ(reg);
  746. cur_state = !!(val & FDI_TX_ENABLE);
  747. WARN(cur_state != state,
  748. "FDI TX state assertion failure (expected %s, current %s)\n",
  749. state_string(state), state_string(cur_state));
  750. }
  751. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  752. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  753. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  754. enum pipe pipe, bool state)
  755. {
  756. int reg;
  757. u32 val;
  758. bool cur_state;
  759. reg = FDI_RX_CTL(pipe);
  760. val = I915_READ(reg);
  761. cur_state = !!(val & FDI_RX_ENABLE);
  762. WARN(cur_state != state,
  763. "FDI RX state assertion failure (expected %s, current %s)\n",
  764. state_string(state), state_string(cur_state));
  765. }
  766. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  767. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  768. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  769. enum pipe pipe)
  770. {
  771. int reg;
  772. u32 val;
  773. /* ILK FDI PLL is always enabled */
  774. if (dev_priv->info->gen == 5)
  775. return;
  776. reg = FDI_TX_CTL(pipe);
  777. val = I915_READ(reg);
  778. WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  779. }
  780. static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
  781. enum pipe pipe)
  782. {
  783. int reg;
  784. u32 val;
  785. reg = FDI_RX_CTL(pipe);
  786. val = I915_READ(reg);
  787. WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
  788. }
  789. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  790. enum pipe pipe)
  791. {
  792. int pp_reg, lvds_reg;
  793. u32 val;
  794. enum pipe panel_pipe = PIPE_A;
  795. bool locked = locked;
  796. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  797. pp_reg = PCH_PP_CONTROL;
  798. lvds_reg = PCH_LVDS;
  799. } else {
  800. pp_reg = PP_CONTROL;
  801. lvds_reg = LVDS;
  802. }
  803. val = I915_READ(pp_reg);
  804. if (!(val & PANEL_POWER_ON) ||
  805. ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  806. locked = false;
  807. if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  808. panel_pipe = PIPE_B;
  809. WARN(panel_pipe == pipe && locked,
  810. "panel assertion failure, pipe %c regs locked\n",
  811. pipe_name(pipe));
  812. }
  813. static void assert_pipe(struct drm_i915_private *dev_priv,
  814. enum pipe pipe, bool state)
  815. {
  816. int reg;
  817. u32 val;
  818. bool cur_state;
  819. reg = PIPECONF(pipe);
  820. val = I915_READ(reg);
  821. cur_state = !!(val & PIPECONF_ENABLE);
  822. WARN(cur_state != state,
  823. "pipe %c assertion failure (expected %s, current %s)\n",
  824. pipe_name(pipe), state_string(state), state_string(cur_state));
  825. }
  826. #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
  827. #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
  828. static void assert_plane_enabled(struct drm_i915_private *dev_priv,
  829. enum plane plane)
  830. {
  831. int reg;
  832. u32 val;
  833. reg = DSPCNTR(plane);
  834. val = I915_READ(reg);
  835. WARN(!(val & DISPLAY_PLANE_ENABLE),
  836. "plane %c assertion failure, should be active but is disabled\n",
  837. plane_name(plane));
  838. }
  839. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  840. enum pipe pipe)
  841. {
  842. int reg, i;
  843. u32 val;
  844. int cur_pipe;
  845. /* Planes are fixed to pipes on ILK+ */
  846. if (HAS_PCH_SPLIT(dev_priv->dev))
  847. return;
  848. /* Need to check both planes against the pipe */
  849. for (i = 0; i < 2; i++) {
  850. reg = DSPCNTR(i);
  851. val = I915_READ(reg);
  852. cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  853. DISPPLANE_SEL_PIPE_SHIFT;
  854. WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  855. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  856. plane_name(i), pipe_name(pipe));
  857. }
  858. }
  859. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  860. {
  861. u32 val;
  862. bool enabled;
  863. val = I915_READ(PCH_DREF_CONTROL);
  864. enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  865. DREF_SUPERSPREAD_SOURCE_MASK));
  866. WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  867. }
  868. static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
  869. enum pipe pipe)
  870. {
  871. int reg;
  872. u32 val;
  873. bool enabled;
  874. reg = TRANSCONF(pipe);
  875. val = I915_READ(reg);
  876. enabled = !!(val & TRANS_ENABLE);
  877. WARN(enabled,
  878. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  879. pipe_name(pipe));
  880. }
  881. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
  882. int reg, u32 port_sel, u32 val)
  883. {
  884. if ((val & DP_PORT_EN) == 0)
  885. return false;
  886. if (HAS_PCH_CPT(dev_priv->dev)) {
  887. u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  888. u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  889. if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  890. return false;
  891. } else {
  892. if ((val & DP_PIPE_MASK) != (pipe << 30))
  893. return false;
  894. }
  895. return true;
  896. }
  897. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  898. enum pipe pipe, int reg, u32 port_sel)
  899. {
  900. u32 val = I915_READ(reg);
  901. WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
  902. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  903. reg, pipe_name(pipe));
  904. }
  905. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  906. enum pipe pipe, int reg)
  907. {
  908. u32 val = I915_READ(reg);
  909. WARN(HDMI_PIPE_ENABLED(val, pipe),
  910. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  911. reg, pipe_name(pipe));
  912. }
  913. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  914. enum pipe pipe)
  915. {
  916. int reg;
  917. u32 val;
  918. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  919. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  920. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  921. reg = PCH_ADPA;
  922. val = I915_READ(reg);
  923. WARN(ADPA_PIPE_ENABLED(val, pipe),
  924. "PCH VGA enabled on transcoder %c, should be disabled\n",
  925. pipe_name(pipe));
  926. reg = PCH_LVDS;
  927. val = I915_READ(reg);
  928. WARN(LVDS_PIPE_ENABLED(val, pipe),
  929. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  930. pipe_name(pipe));
  931. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
  932. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
  933. assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
  934. }
  935. /**
  936. * intel_enable_pll - enable a PLL
  937. * @dev_priv: i915 private structure
  938. * @pipe: pipe PLL to enable
  939. *
  940. * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
  941. * make sure the PLL reg is writable first though, since the panel write
  942. * protect mechanism may be enabled.
  943. *
  944. * Note! This is for pre-ILK only.
  945. */
  946. static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  947. {
  948. int reg;
  949. u32 val;
  950. /* No really, not for ILK+ */
  951. BUG_ON(dev_priv->info->gen >= 5);
  952. /* PLL is protected by panel, make sure we can write it */
  953. if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  954. assert_panel_unlocked(dev_priv, pipe);
  955. reg = DPLL(pipe);
  956. val = I915_READ(reg);
  957. val |= DPLL_VCO_ENABLE;
  958. /* We do this three times for luck */
  959. I915_WRITE(reg, val);
  960. POSTING_READ(reg);
  961. udelay(150); /* wait for warmup */
  962. I915_WRITE(reg, val);
  963. POSTING_READ(reg);
  964. udelay(150); /* wait for warmup */
  965. I915_WRITE(reg, val);
  966. POSTING_READ(reg);
  967. udelay(150); /* wait for warmup */
  968. }
  969. /**
  970. * intel_disable_pll - disable a PLL
  971. * @dev_priv: i915 private structure
  972. * @pipe: pipe PLL to disable
  973. *
  974. * Disable the PLL for @pipe, making sure the pipe is off first.
  975. *
  976. * Note! This is for pre-ILK only.
  977. */
  978. static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  979. {
  980. int reg;
  981. u32 val;
  982. /* Don't disable pipe A or pipe A PLLs if needed */
  983. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  984. return;
  985. /* Make sure the pipe isn't still relying on us */
  986. assert_pipe_disabled(dev_priv, pipe);
  987. reg = DPLL(pipe);
  988. val = I915_READ(reg);
  989. val &= ~DPLL_VCO_ENABLE;
  990. I915_WRITE(reg, val);
  991. POSTING_READ(reg);
  992. }
  993. /**
  994. * intel_enable_pch_pll - enable PCH PLL
  995. * @dev_priv: i915 private structure
  996. * @pipe: pipe PLL to enable
  997. *
  998. * The PCH PLL needs to be enabled before the PCH transcoder, since it
  999. * drives the transcoder clock.
  1000. */
  1001. static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
  1002. enum pipe pipe)
  1003. {
  1004. int reg;
  1005. u32 val;
  1006. /* PCH only available on ILK+ */
  1007. BUG_ON(dev_priv->info->gen < 5);
  1008. /* PCH refclock must be enabled first */
  1009. assert_pch_refclk_enabled(dev_priv);
  1010. reg = PCH_DPLL(pipe);
  1011. val = I915_READ(reg);
  1012. val |= DPLL_VCO_ENABLE;
  1013. I915_WRITE(reg, val);
  1014. POSTING_READ(reg);
  1015. udelay(200);
  1016. }
  1017. static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
  1018. enum pipe pipe)
  1019. {
  1020. int reg;
  1021. u32 val;
  1022. /* PCH only available on ILK+ */
  1023. BUG_ON(dev_priv->info->gen < 5);
  1024. /* Make sure transcoder isn't still depending on us */
  1025. assert_transcoder_disabled(dev_priv, pipe);
  1026. reg = PCH_DPLL(pipe);
  1027. val = I915_READ(reg);
  1028. val &= ~DPLL_VCO_ENABLE;
  1029. I915_WRITE(reg, val);
  1030. POSTING_READ(reg);
  1031. udelay(200);
  1032. }
  1033. static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
  1034. enum pipe pipe)
  1035. {
  1036. int reg;
  1037. u32 val;
  1038. /* PCH only available on ILK+ */
  1039. BUG_ON(dev_priv->info->gen < 5);
  1040. /* Make sure PCH DPLL is enabled */
  1041. assert_pch_pll_enabled(dev_priv, pipe);
  1042. /* FDI must be feeding us bits for PCH ports */
  1043. assert_fdi_tx_enabled(dev_priv, pipe);
  1044. assert_fdi_rx_enabled(dev_priv, pipe);
  1045. reg = TRANSCONF(pipe);
  1046. val = I915_READ(reg);
  1047. /*
  1048. * make the BPC in transcoder be consistent with
  1049. * that in pipeconf reg.
  1050. */
  1051. val &= ~PIPE_BPC_MASK;
  1052. val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
  1053. I915_WRITE(reg, val | TRANS_ENABLE);
  1054. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1055. DRM_ERROR("failed to enable transcoder %d\n", pipe);
  1056. }
  1057. static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
  1058. enum pipe pipe)
  1059. {
  1060. int reg;
  1061. u32 val;
  1062. /* FDI relies on the transcoder */
  1063. assert_fdi_tx_disabled(dev_priv, pipe);
  1064. assert_fdi_rx_disabled(dev_priv, pipe);
  1065. /* Ports must be off as well */
  1066. assert_pch_ports_disabled(dev_priv, pipe);
  1067. reg = TRANSCONF(pipe);
  1068. val = I915_READ(reg);
  1069. val &= ~TRANS_ENABLE;
  1070. I915_WRITE(reg, val);
  1071. /* wait for PCH transcoder off, transcoder state */
  1072. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1073. DRM_ERROR("failed to disable transcoder\n");
  1074. }
  1075. /**
  1076. * intel_enable_pipe - enable a pipe, asserting requirements
  1077. * @dev_priv: i915 private structure
  1078. * @pipe: pipe to enable
  1079. * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1080. *
  1081. * Enable @pipe, making sure that various hardware specific requirements
  1082. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1083. *
  1084. * @pipe should be %PIPE_A or %PIPE_B.
  1085. *
  1086. * Will wait until the pipe is actually running (i.e. first vblank) before
  1087. * returning.
  1088. */
  1089. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1090. bool pch_port)
  1091. {
  1092. int reg;
  1093. u32 val;
  1094. /*
  1095. * A pipe without a PLL won't actually be able to drive bits from
  1096. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1097. * need the check.
  1098. */
  1099. if (!HAS_PCH_SPLIT(dev_priv->dev))
  1100. assert_pll_enabled(dev_priv, pipe);
  1101. else {
  1102. if (pch_port) {
  1103. /* if driving the PCH, we need FDI enabled */
  1104. assert_fdi_rx_pll_enabled(dev_priv, pipe);
  1105. assert_fdi_tx_pll_enabled(dev_priv, pipe);
  1106. }
  1107. /* FIXME: assert CPU port conditions for SNB+ */
  1108. }
  1109. reg = PIPECONF(pipe);
  1110. val = I915_READ(reg);
  1111. if (val & PIPECONF_ENABLE)
  1112. return;
  1113. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1114. intel_wait_for_vblank(dev_priv->dev, pipe);
  1115. }
  1116. /**
  1117. * intel_disable_pipe - disable a pipe, asserting requirements
  1118. * @dev_priv: i915 private structure
  1119. * @pipe: pipe to disable
  1120. *
  1121. * Disable @pipe, making sure that various hardware specific requirements
  1122. * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1123. *
  1124. * @pipe should be %PIPE_A or %PIPE_B.
  1125. *
  1126. * Will wait until the pipe has shut down before returning.
  1127. */
  1128. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1129. enum pipe pipe)
  1130. {
  1131. int reg;
  1132. u32 val;
  1133. /*
  1134. * Make sure planes won't keep trying to pump pixels to us,
  1135. * or we might hang the display.
  1136. */
  1137. assert_planes_disabled(dev_priv, pipe);
  1138. /* Don't disable pipe A or pipe A PLLs if needed */
  1139. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1140. return;
  1141. reg = PIPECONF(pipe);
  1142. val = I915_READ(reg);
  1143. if ((val & PIPECONF_ENABLE) == 0)
  1144. return;
  1145. I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1146. intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1147. }
  1148. /*
  1149. * Plane regs are double buffered, going from enabled->disabled needs a
  1150. * trigger in order to latch. The display address reg provides this.
  1151. */
  1152. static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1153. enum plane plane)
  1154. {
  1155. I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
  1156. I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
  1157. }
  1158. /**
  1159. * intel_enable_plane - enable a display plane on a given pipe
  1160. * @dev_priv: i915 private structure
  1161. * @plane: plane to enable
  1162. * @pipe: pipe being fed
  1163. *
  1164. * Enable @plane on @pipe, making sure that @pipe is running first.
  1165. */
  1166. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1167. enum plane plane, enum pipe pipe)
  1168. {
  1169. int reg;
  1170. u32 val;
  1171. /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1172. assert_pipe_enabled(dev_priv, pipe);
  1173. reg = DSPCNTR(plane);
  1174. val = I915_READ(reg);
  1175. if (val & DISPLAY_PLANE_ENABLE)
  1176. return;
  1177. I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1178. intel_flush_display_plane(dev_priv, plane);
  1179. intel_wait_for_vblank(dev_priv->dev, pipe);
  1180. }
  1181. /**
  1182. * intel_disable_plane - disable a display plane
  1183. * @dev_priv: i915 private structure
  1184. * @plane: plane to disable
  1185. * @pipe: pipe consuming the data
  1186. *
  1187. * Disable @plane; should be an independent operation.
  1188. */
  1189. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1190. enum plane plane, enum pipe pipe)
  1191. {
  1192. int reg;
  1193. u32 val;
  1194. reg = DSPCNTR(plane);
  1195. val = I915_READ(reg);
  1196. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1197. return;
  1198. I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1199. intel_flush_display_plane(dev_priv, plane);
  1200. intel_wait_for_vblank(dev_priv->dev, pipe);
  1201. }
  1202. static void disable_pch_dp(struct drm_i915_private *dev_priv,
  1203. enum pipe pipe, int reg, u32 port_sel)
  1204. {
  1205. u32 val = I915_READ(reg);
  1206. if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
  1207. DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
  1208. I915_WRITE(reg, val & ~DP_PORT_EN);
  1209. }
  1210. }
  1211. static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
  1212. enum pipe pipe, int reg)
  1213. {
  1214. u32 val = I915_READ(reg);
  1215. if (HDMI_PIPE_ENABLED(val, pipe)) {
  1216. DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
  1217. reg, pipe);
  1218. I915_WRITE(reg, val & ~PORT_ENABLE);
  1219. }
  1220. }
  1221. /* Disable any ports connected to this transcoder */
  1222. static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
  1223. enum pipe pipe)
  1224. {
  1225. u32 reg, val;
  1226. val = I915_READ(PCH_PP_CONTROL);
  1227. I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
  1228. disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1229. disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1230. disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1231. reg = PCH_ADPA;
  1232. val = I915_READ(reg);
  1233. if (ADPA_PIPE_ENABLED(val, pipe))
  1234. I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
  1235. reg = PCH_LVDS;
  1236. val = I915_READ(reg);
  1237. if (LVDS_PIPE_ENABLED(val, pipe)) {
  1238. I915_WRITE(reg, val & ~LVDS_PORT_EN);
  1239. POSTING_READ(reg);
  1240. udelay(100);
  1241. }
  1242. disable_pch_hdmi(dev_priv, pipe, HDMIB);
  1243. disable_pch_hdmi(dev_priv, pipe, HDMIC);
  1244. disable_pch_hdmi(dev_priv, pipe, HDMID);
  1245. }
  1246. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1247. {
  1248. struct drm_device *dev = crtc->dev;
  1249. struct drm_i915_private *dev_priv = dev->dev_private;
  1250. struct drm_framebuffer *fb = crtc->fb;
  1251. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1252. struct drm_i915_gem_object *obj = intel_fb->obj;
  1253. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1254. int plane, i;
  1255. u32 fbc_ctl, fbc_ctl2;
  1256. if (fb->pitch == dev_priv->cfb_pitch &&
  1257. obj->fence_reg == dev_priv->cfb_fence &&
  1258. intel_crtc->plane == dev_priv->cfb_plane &&
  1259. I915_READ(FBC_CONTROL) & FBC_CTL_EN)
  1260. return;
  1261. i8xx_disable_fbc(dev);
  1262. dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  1263. if (fb->pitch < dev_priv->cfb_pitch)
  1264. dev_priv->cfb_pitch = fb->pitch;
  1265. /* FBC_CTL wants 64B units */
  1266. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  1267. dev_priv->cfb_fence = obj->fence_reg;
  1268. dev_priv->cfb_plane = intel_crtc->plane;
  1269. plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  1270. /* Clear old tags */
  1271. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  1272. I915_WRITE(FBC_TAG + (i * 4), 0);
  1273. /* Set it up... */
  1274. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
  1275. if (obj->tiling_mode != I915_TILING_NONE)
  1276. fbc_ctl2 |= FBC_CTL_CPU_FENCE;
  1277. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  1278. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  1279. /* enable it... */
  1280. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  1281. if (IS_I945GM(dev))
  1282. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  1283. fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  1284. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  1285. if (obj->tiling_mode != I915_TILING_NONE)
  1286. fbc_ctl |= dev_priv->cfb_fence;
  1287. I915_WRITE(FBC_CONTROL, fbc_ctl);
  1288. DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
  1289. dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
  1290. }
  1291. void i8xx_disable_fbc(struct drm_device *dev)
  1292. {
  1293. struct drm_i915_private *dev_priv = dev->dev_private;
  1294. u32 fbc_ctl;
  1295. /* Disable compression */
  1296. fbc_ctl = I915_READ(FBC_CONTROL);
  1297. if ((fbc_ctl & FBC_CTL_EN) == 0)
  1298. return;
  1299. fbc_ctl &= ~FBC_CTL_EN;
  1300. I915_WRITE(FBC_CONTROL, fbc_ctl);
  1301. /* Wait for compressing bit to clear */
  1302. if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  1303. DRM_DEBUG_KMS("FBC idle timed out\n");
  1304. return;
  1305. }
  1306. DRM_DEBUG_KMS("disabled FBC\n");
  1307. }
  1308. static bool i8xx_fbc_enabled(struct drm_device *dev)
  1309. {
  1310. struct drm_i915_private *dev_priv = dev->dev_private;
  1311. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  1312. }
  1313. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1314. {
  1315. struct drm_device *dev = crtc->dev;
  1316. struct drm_i915_private *dev_priv = dev->dev_private;
  1317. struct drm_framebuffer *fb = crtc->fb;
  1318. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1319. struct drm_i915_gem_object *obj = intel_fb->obj;
  1320. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1321. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  1322. unsigned long stall_watermark = 200;
  1323. u32 dpfc_ctl;
  1324. dpfc_ctl = I915_READ(DPFC_CONTROL);
  1325. if (dpfc_ctl & DPFC_CTL_EN) {
  1326. if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
  1327. dev_priv->cfb_fence == obj->fence_reg &&
  1328. dev_priv->cfb_plane == intel_crtc->plane &&
  1329. dev_priv->cfb_y == crtc->y)
  1330. return;
  1331. I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
  1332. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1333. }
  1334. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  1335. dev_priv->cfb_fence = obj->fence_reg;
  1336. dev_priv->cfb_plane = intel_crtc->plane;
  1337. dev_priv->cfb_y = crtc->y;
  1338. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  1339. if (obj->tiling_mode != I915_TILING_NONE) {
  1340. dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
  1341. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  1342. } else {
  1343. I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  1344. }
  1345. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1346. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1347. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1348. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  1349. /* enable it... */
  1350. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  1351. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1352. }
  1353. void g4x_disable_fbc(struct drm_device *dev)
  1354. {
  1355. struct drm_i915_private *dev_priv = dev->dev_private;
  1356. u32 dpfc_ctl;
  1357. /* Disable compression */
  1358. dpfc_ctl = I915_READ(DPFC_CONTROL);
  1359. if (dpfc_ctl & DPFC_CTL_EN) {
  1360. dpfc_ctl &= ~DPFC_CTL_EN;
  1361. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  1362. DRM_DEBUG_KMS("disabled FBC\n");
  1363. }
  1364. }
  1365. static bool g4x_fbc_enabled(struct drm_device *dev)
  1366. {
  1367. struct drm_i915_private *dev_priv = dev->dev_private;
  1368. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  1369. }
  1370. static void sandybridge_blit_fbc_update(struct drm_device *dev)
  1371. {
  1372. struct drm_i915_private *dev_priv = dev->dev_private;
  1373. u32 blt_ecoskpd;
  1374. /* Make sure blitter notifies FBC of writes */
  1375. gen6_gt_force_wake_get(dev_priv);
  1376. blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
  1377. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
  1378. GEN6_BLITTER_LOCK_SHIFT;
  1379. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  1380. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
  1381. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  1382. blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
  1383. GEN6_BLITTER_LOCK_SHIFT);
  1384. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  1385. POSTING_READ(GEN6_BLITTER_ECOSKPD);
  1386. gen6_gt_force_wake_put(dev_priv);
  1387. }
  1388. static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1389. {
  1390. struct drm_device *dev = crtc->dev;
  1391. struct drm_i915_private *dev_priv = dev->dev_private;
  1392. struct drm_framebuffer *fb = crtc->fb;
  1393. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1394. struct drm_i915_gem_object *obj = intel_fb->obj;
  1395. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1396. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  1397. unsigned long stall_watermark = 200;
  1398. u32 dpfc_ctl;
  1399. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1400. if (dpfc_ctl & DPFC_CTL_EN) {
  1401. if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
  1402. dev_priv->cfb_fence == obj->fence_reg &&
  1403. dev_priv->cfb_plane == intel_crtc->plane &&
  1404. dev_priv->cfb_offset == obj->gtt_offset &&
  1405. dev_priv->cfb_y == crtc->y)
  1406. return;
  1407. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
  1408. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1409. }
  1410. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  1411. dev_priv->cfb_fence = obj->fence_reg;
  1412. dev_priv->cfb_plane = intel_crtc->plane;
  1413. dev_priv->cfb_offset = obj->gtt_offset;
  1414. dev_priv->cfb_y = crtc->y;
  1415. dpfc_ctl &= DPFC_RESERVED;
  1416. dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
  1417. if (obj->tiling_mode != I915_TILING_NONE) {
  1418. dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
  1419. I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
  1420. } else {
  1421. I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  1422. }
  1423. I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1424. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1425. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1426. I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
  1427. I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
  1428. /* enable it... */
  1429. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
  1430. if (IS_GEN6(dev)) {
  1431. I915_WRITE(SNB_DPFC_CTL_SA,
  1432. SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
  1433. I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  1434. sandybridge_blit_fbc_update(dev);
  1435. }
  1436. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1437. }
  1438. void ironlake_disable_fbc(struct drm_device *dev)
  1439. {
  1440. struct drm_i915_private *dev_priv = dev->dev_private;
  1441. u32 dpfc_ctl;
  1442. /* Disable compression */
  1443. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1444. if (dpfc_ctl & DPFC_CTL_EN) {
  1445. dpfc_ctl &= ~DPFC_CTL_EN;
  1446. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  1447. DRM_DEBUG_KMS("disabled FBC\n");
  1448. }
  1449. }
  1450. static bool ironlake_fbc_enabled(struct drm_device *dev)
  1451. {
  1452. struct drm_i915_private *dev_priv = dev->dev_private;
  1453. return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  1454. }
  1455. bool intel_fbc_enabled(struct drm_device *dev)
  1456. {
  1457. struct drm_i915_private *dev_priv = dev->dev_private;
  1458. if (!dev_priv->display.fbc_enabled)
  1459. return false;
  1460. return dev_priv->display.fbc_enabled(dev);
  1461. }
  1462. void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1463. {
  1464. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  1465. if (!dev_priv->display.enable_fbc)
  1466. return;
  1467. dev_priv->display.enable_fbc(crtc, interval);
  1468. }
  1469. void intel_disable_fbc(struct drm_device *dev)
  1470. {
  1471. struct drm_i915_private *dev_priv = dev->dev_private;
  1472. if (!dev_priv->display.disable_fbc)
  1473. return;
  1474. dev_priv->display.disable_fbc(dev);
  1475. }
  1476. /**
  1477. * intel_update_fbc - enable/disable FBC as needed
  1478. * @dev: the drm_device
  1479. *
  1480. * Set up the framebuffer compression hardware at mode set time. We
  1481. * enable it if possible:
  1482. * - plane A only (on pre-965)
  1483. * - no pixel mulitply/line duplication
  1484. * - no alpha buffer discard
  1485. * - no dual wide
  1486. * - framebuffer <= 2048 in width, 1536 in height
  1487. *
  1488. * We can't assume that any compression will take place (worst case),
  1489. * so the compressed buffer has to be the same size as the uncompressed
  1490. * one. It also must reside (along with the line length buffer) in
  1491. * stolen memory.
  1492. *
  1493. * We need to enable/disable FBC on a global basis.
  1494. */
  1495. static void intel_update_fbc(struct drm_device *dev)
  1496. {
  1497. struct drm_i915_private *dev_priv = dev->dev_private;
  1498. struct drm_crtc *crtc = NULL, *tmp_crtc;
  1499. struct intel_crtc *intel_crtc;
  1500. struct drm_framebuffer *fb;
  1501. struct intel_framebuffer *intel_fb;
  1502. struct drm_i915_gem_object *obj;
  1503. DRM_DEBUG_KMS("\n");
  1504. if (!i915_powersave)
  1505. return;
  1506. if (!I915_HAS_FBC(dev))
  1507. return;
  1508. /*
  1509. * If FBC is already on, we just have to verify that we can
  1510. * keep it that way...
  1511. * Need to disable if:
  1512. * - more than one pipe is active
  1513. * - changing FBC params (stride, fence, mode)
  1514. * - new fb is too large to fit in compressed buffer
  1515. * - going to an unsupported config (interlace, pixel multiply, etc.)
  1516. */
  1517. list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
  1518. if (tmp_crtc->enabled && tmp_crtc->fb) {
  1519. if (crtc) {
  1520. DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
  1521. dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
  1522. goto out_disable;
  1523. }
  1524. crtc = tmp_crtc;
  1525. }
  1526. }
  1527. if (!crtc || crtc->fb == NULL) {
  1528. DRM_DEBUG_KMS("no output, disabling\n");
  1529. dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
  1530. goto out_disable;
  1531. }
  1532. intel_crtc = to_intel_crtc(crtc);
  1533. fb = crtc->fb;
  1534. intel_fb = to_intel_framebuffer(fb);
  1535. obj = intel_fb->obj;
  1536. if (!i915_enable_fbc) {
  1537. DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
  1538. dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
  1539. goto out_disable;
  1540. }
  1541. if (intel_fb->obj->base.size > dev_priv->cfb_size) {
  1542. DRM_DEBUG_KMS("framebuffer too large, disabling "
  1543. "compression\n");
  1544. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1545. goto out_disable;
  1546. }
  1547. if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
  1548. (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
  1549. DRM_DEBUG_KMS("mode incompatible with compression, "
  1550. "disabling\n");
  1551. dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  1552. goto out_disable;
  1553. }
  1554. if ((crtc->mode.hdisplay > 2048) ||
  1555. (crtc->mode.vdisplay > 1536)) {
  1556. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  1557. dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  1558. goto out_disable;
  1559. }
  1560. if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
  1561. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  1562. dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  1563. goto out_disable;
  1564. }
  1565. if (obj->tiling_mode != I915_TILING_X) {
  1566. DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
  1567. dev_priv->no_fbc_reason = FBC_NOT_TILED;
  1568. goto out_disable;
  1569. }
  1570. /* If the kernel debugger is active, always disable compression */
  1571. if (in_dbg_master())
  1572. goto out_disable;
  1573. intel_enable_fbc(crtc, 500);
  1574. return;
  1575. out_disable:
  1576. /* Multiple disables should be harmless */
  1577. if (intel_fbc_enabled(dev)) {
  1578. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  1579. intel_disable_fbc(dev);
  1580. }
  1581. }
  1582. int
  1583. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1584. struct drm_i915_gem_object *obj,
  1585. struct intel_ring_buffer *pipelined)
  1586. {
  1587. struct drm_i915_private *dev_priv = dev->dev_private;
  1588. u32 alignment;
  1589. int ret;
  1590. switch (obj->tiling_mode) {
  1591. case I915_TILING_NONE:
  1592. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1593. alignment = 128 * 1024;
  1594. else if (INTEL_INFO(dev)->gen >= 4)
  1595. alignment = 4 * 1024;
  1596. else
  1597. alignment = 64 * 1024;
  1598. break;
  1599. case I915_TILING_X:
  1600. /* pin() will align the object as required by fence */
  1601. alignment = 0;
  1602. break;
  1603. case I915_TILING_Y:
  1604. /* FIXME: Is this true? */
  1605. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1606. return -EINVAL;
  1607. default:
  1608. BUG();
  1609. }
  1610. dev_priv->mm.interruptible = false;
  1611. ret = i915_gem_object_pin(obj, alignment, true);
  1612. if (ret)
  1613. goto err_interruptible;
  1614. ret = i915_gem_object_set_to_display_plane(obj, pipelined);
  1615. if (ret)
  1616. goto err_unpin;
  1617. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1618. * fence, whereas 965+ only requires a fence if using
  1619. * framebuffer compression. For simplicity, we always install
  1620. * a fence as the cost is not that onerous.
  1621. */
  1622. if (obj->tiling_mode != I915_TILING_NONE) {
  1623. ret = i915_gem_object_get_fence(obj, pipelined);
  1624. if (ret)
  1625. goto err_unpin;
  1626. }
  1627. dev_priv->mm.interruptible = true;
  1628. return 0;
  1629. err_unpin:
  1630. i915_gem_object_unpin(obj);
  1631. err_interruptible:
  1632. dev_priv->mm.interruptible = true;
  1633. return ret;
  1634. }
  1635. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1636. static int
  1637. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1638. int x, int y, enum mode_set_atomic state)
  1639. {
  1640. struct drm_device *dev = crtc->dev;
  1641. struct drm_i915_private *dev_priv = dev->dev_private;
  1642. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1643. struct intel_framebuffer *intel_fb;
  1644. struct drm_i915_gem_object *obj;
  1645. int plane = intel_crtc->plane;
  1646. unsigned long Start, Offset;
  1647. u32 dspcntr;
  1648. u32 reg;
  1649. switch (plane) {
  1650. case 0:
  1651. case 1:
  1652. break;
  1653. default:
  1654. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1655. return -EINVAL;
  1656. }
  1657. intel_fb = to_intel_framebuffer(fb);
  1658. obj = intel_fb->obj;
  1659. reg = DSPCNTR(plane);
  1660. dspcntr = I915_READ(reg);
  1661. /* Mask out pixel format bits in case we change it */
  1662. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1663. switch (fb->bits_per_pixel) {
  1664. case 8:
  1665. dspcntr |= DISPPLANE_8BPP;
  1666. break;
  1667. case 16:
  1668. if (fb->depth == 15)
  1669. dspcntr |= DISPPLANE_15_16BPP;
  1670. else
  1671. dspcntr |= DISPPLANE_16BPP;
  1672. break;
  1673. case 24:
  1674. case 32:
  1675. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1676. break;
  1677. default:
  1678. DRM_ERROR("Unknown color depth\n");
  1679. return -EINVAL;
  1680. }
  1681. if (INTEL_INFO(dev)->gen >= 4) {
  1682. if (obj->tiling_mode != I915_TILING_NONE)
  1683. dspcntr |= DISPPLANE_TILED;
  1684. else
  1685. dspcntr &= ~DISPPLANE_TILED;
  1686. }
  1687. if (HAS_PCH_SPLIT(dev))
  1688. /* must disable */
  1689. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1690. I915_WRITE(reg, dspcntr);
  1691. Start = obj->gtt_offset;
  1692. Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
  1693. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1694. Start, Offset, x, y, fb->pitch);
  1695. I915_WRITE(DSPSTRIDE(plane), fb->pitch);
  1696. if (INTEL_INFO(dev)->gen >= 4) {
  1697. I915_WRITE(DSPSURF(plane), Start);
  1698. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1699. I915_WRITE(DSPADDR(plane), Offset);
  1700. } else
  1701. I915_WRITE(DSPADDR(plane), Start + Offset);
  1702. POSTING_READ(reg);
  1703. intel_update_fbc(dev);
  1704. intel_increase_pllclock(crtc);
  1705. return 0;
  1706. }
  1707. static int
  1708. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1709. struct drm_framebuffer *old_fb)
  1710. {
  1711. struct drm_device *dev = crtc->dev;
  1712. struct drm_i915_master_private *master_priv;
  1713. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1714. int ret;
  1715. /* no fb bound */
  1716. if (!crtc->fb) {
  1717. DRM_ERROR("No FB bound\n");
  1718. return 0;
  1719. }
  1720. switch (intel_crtc->plane) {
  1721. case 0:
  1722. case 1:
  1723. break;
  1724. default:
  1725. DRM_ERROR("no plane for crtc\n");
  1726. return -EINVAL;
  1727. }
  1728. mutex_lock(&dev->struct_mutex);
  1729. ret = intel_pin_and_fence_fb_obj(dev,
  1730. to_intel_framebuffer(crtc->fb)->obj,
  1731. NULL);
  1732. if (ret != 0) {
  1733. mutex_unlock(&dev->struct_mutex);
  1734. DRM_ERROR("pin & fence failed\n");
  1735. return ret;
  1736. }
  1737. if (old_fb) {
  1738. struct drm_i915_private *dev_priv = dev->dev_private;
  1739. struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  1740. wait_event(dev_priv->pending_flip_queue,
  1741. atomic_read(&dev_priv->mm.wedged) ||
  1742. atomic_read(&obj->pending_flip) == 0);
  1743. /* Big Hammer, we also need to ensure that any pending
  1744. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  1745. * current scanout is retired before unpinning the old
  1746. * framebuffer.
  1747. *
  1748. * This should only fail upon a hung GPU, in which case we
  1749. * can safely continue.
  1750. */
  1751. ret = i915_gem_object_flush_gpu(obj);
  1752. (void) ret;
  1753. }
  1754. ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
  1755. LEAVE_ATOMIC_MODE_SET);
  1756. if (ret) {
  1757. i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
  1758. mutex_unlock(&dev->struct_mutex);
  1759. DRM_ERROR("failed to update base address\n");
  1760. return ret;
  1761. }
  1762. if (old_fb) {
  1763. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1764. i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
  1765. }
  1766. mutex_unlock(&dev->struct_mutex);
  1767. if (!dev->primary->master)
  1768. return 0;
  1769. master_priv = dev->primary->master->driver_priv;
  1770. if (!master_priv->sarea_priv)
  1771. return 0;
  1772. if (intel_crtc->pipe) {
  1773. master_priv->sarea_priv->pipeB_x = x;
  1774. master_priv->sarea_priv->pipeB_y = y;
  1775. } else {
  1776. master_priv->sarea_priv->pipeA_x = x;
  1777. master_priv->sarea_priv->pipeA_y = y;
  1778. }
  1779. return 0;
  1780. }
  1781. static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
  1782. {
  1783. struct drm_device *dev = crtc->dev;
  1784. struct drm_i915_private *dev_priv = dev->dev_private;
  1785. u32 dpa_ctl;
  1786. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  1787. dpa_ctl = I915_READ(DP_A);
  1788. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  1789. if (clock < 200000) {
  1790. u32 temp;
  1791. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  1792. /* workaround for 160Mhz:
  1793. 1) program 0x4600c bits 15:0 = 0x8124
  1794. 2) program 0x46010 bit 0 = 1
  1795. 3) program 0x46034 bit 24 = 1
  1796. 4) program 0x64000 bit 14 = 1
  1797. */
  1798. temp = I915_READ(0x4600c);
  1799. temp &= 0xffff0000;
  1800. I915_WRITE(0x4600c, temp | 0x8124);
  1801. temp = I915_READ(0x46010);
  1802. I915_WRITE(0x46010, temp | 1);
  1803. temp = I915_READ(0x46034);
  1804. I915_WRITE(0x46034, temp | (1 << 24));
  1805. } else {
  1806. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  1807. }
  1808. I915_WRITE(DP_A, dpa_ctl);
  1809. POSTING_READ(DP_A);
  1810. udelay(500);
  1811. }
  1812. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  1813. {
  1814. struct drm_device *dev = crtc->dev;
  1815. struct drm_i915_private *dev_priv = dev->dev_private;
  1816. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1817. int pipe = intel_crtc->pipe;
  1818. u32 reg, temp;
  1819. /* enable normal train */
  1820. reg = FDI_TX_CTL(pipe);
  1821. temp = I915_READ(reg);
  1822. if (IS_IVYBRIDGE(dev)) {
  1823. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  1824. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  1825. } else {
  1826. temp &= ~FDI_LINK_TRAIN_NONE;
  1827. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  1828. }
  1829. I915_WRITE(reg, temp);
  1830. reg = FDI_RX_CTL(pipe);
  1831. temp = I915_READ(reg);
  1832. if (HAS_PCH_CPT(dev)) {
  1833. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1834. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  1835. } else {
  1836. temp &= ~FDI_LINK_TRAIN_NONE;
  1837. temp |= FDI_LINK_TRAIN_NONE;
  1838. }
  1839. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  1840. /* wait one idle pattern time */
  1841. POSTING_READ(reg);
  1842. udelay(1000);
  1843. /* IVB wants error correction enabled */
  1844. if (IS_IVYBRIDGE(dev))
  1845. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  1846. FDI_FE_ERRC_ENABLE);
  1847. }
  1848. static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
  1849. {
  1850. struct drm_i915_private *dev_priv = dev->dev_private;
  1851. u32 flags = I915_READ(SOUTH_CHICKEN1);
  1852. flags |= FDI_PHASE_SYNC_OVR(pipe);
  1853. I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
  1854. flags |= FDI_PHASE_SYNC_EN(pipe);
  1855. I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
  1856. POSTING_READ(SOUTH_CHICKEN1);
  1857. }
  1858. /* The FDI link training functions for ILK/Ibexpeak. */
  1859. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  1860. {
  1861. struct drm_device *dev = crtc->dev;
  1862. struct drm_i915_private *dev_priv = dev->dev_private;
  1863. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1864. int pipe = intel_crtc->pipe;
  1865. int plane = intel_crtc->plane;
  1866. u32 reg, temp, tries;
  1867. /* FDI needs bits from pipe & plane first */
  1868. assert_pipe_enabled(dev_priv, pipe);
  1869. assert_plane_enabled(dev_priv, plane);
  1870. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1871. for train result */
  1872. reg = FDI_RX_IMR(pipe);
  1873. temp = I915_READ(reg);
  1874. temp &= ~FDI_RX_SYMBOL_LOCK;
  1875. temp &= ~FDI_RX_BIT_LOCK;
  1876. I915_WRITE(reg, temp);
  1877. I915_READ(reg);
  1878. udelay(150);
  1879. /* enable CPU FDI TX and PCH FDI RX */
  1880. reg = FDI_TX_CTL(pipe);
  1881. temp = I915_READ(reg);
  1882. temp &= ~(7 << 19);
  1883. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1884. temp &= ~FDI_LINK_TRAIN_NONE;
  1885. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1886. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  1887. reg = FDI_RX_CTL(pipe);
  1888. temp = I915_READ(reg);
  1889. temp &= ~FDI_LINK_TRAIN_NONE;
  1890. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1891. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  1892. POSTING_READ(reg);
  1893. udelay(150);
  1894. /* Ironlake workaround, enable clock pointer after FDI enable*/
  1895. if (HAS_PCH_IBX(dev)) {
  1896. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  1897. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  1898. FDI_RX_PHASE_SYNC_POINTER_EN);
  1899. }
  1900. reg = FDI_RX_IIR(pipe);
  1901. for (tries = 0; tries < 5; tries++) {
  1902. temp = I915_READ(reg);
  1903. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1904. if ((temp & FDI_RX_BIT_LOCK)) {
  1905. DRM_DEBUG_KMS("FDI train 1 done.\n");
  1906. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  1907. break;
  1908. }
  1909. }
  1910. if (tries == 5)
  1911. DRM_ERROR("FDI train 1 fail!\n");
  1912. /* Train 2 */
  1913. reg = FDI_TX_CTL(pipe);
  1914. temp = I915_READ(reg);
  1915. temp &= ~FDI_LINK_TRAIN_NONE;
  1916. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1917. I915_WRITE(reg, temp);
  1918. reg = FDI_RX_CTL(pipe);
  1919. temp = I915_READ(reg);
  1920. temp &= ~FDI_LINK_TRAIN_NONE;
  1921. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1922. I915_WRITE(reg, temp);
  1923. POSTING_READ(reg);
  1924. udelay(150);
  1925. reg = FDI_RX_IIR(pipe);
  1926. for (tries = 0; tries < 5; tries++) {
  1927. temp = I915_READ(reg);
  1928. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1929. if (temp & FDI_RX_SYMBOL_LOCK) {
  1930. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  1931. DRM_DEBUG_KMS("FDI train 2 done.\n");
  1932. break;
  1933. }
  1934. }
  1935. if (tries == 5)
  1936. DRM_ERROR("FDI train 2 fail!\n");
  1937. DRM_DEBUG_KMS("FDI train done\n");
  1938. }
  1939. static const int snb_b_fdi_train_param [] = {
  1940. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  1941. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  1942. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  1943. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  1944. };
  1945. /* The FDI link training functions for SNB/Cougarpoint. */
  1946. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  1947. {
  1948. struct drm_device *dev = crtc->dev;
  1949. struct drm_i915_private *dev_priv = dev->dev_private;
  1950. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1951. int pipe = intel_crtc->pipe;
  1952. u32 reg, temp, i;
  1953. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1954. for train result */
  1955. reg = FDI_RX_IMR(pipe);
  1956. temp = I915_READ(reg);
  1957. temp &= ~FDI_RX_SYMBOL_LOCK;
  1958. temp &= ~FDI_RX_BIT_LOCK;
  1959. I915_WRITE(reg, temp);
  1960. POSTING_READ(reg);
  1961. udelay(150);
  1962. /* enable CPU FDI TX and PCH FDI RX */
  1963. reg = FDI_TX_CTL(pipe);
  1964. temp = I915_READ(reg);
  1965. temp &= ~(7 << 19);
  1966. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1967. temp &= ~FDI_LINK_TRAIN_NONE;
  1968. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1969. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1970. /* SNB-B */
  1971. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  1972. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  1973. reg = FDI_RX_CTL(pipe);
  1974. temp = I915_READ(reg);
  1975. if (HAS_PCH_CPT(dev)) {
  1976. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1977. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  1978. } else {
  1979. temp &= ~FDI_LINK_TRAIN_NONE;
  1980. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1981. }
  1982. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  1983. POSTING_READ(reg);
  1984. udelay(150);
  1985. if (HAS_PCH_CPT(dev))
  1986. cpt_phase_pointer_enable(dev, pipe);
  1987. for (i = 0; i < 4; i++ ) {
  1988. reg = FDI_TX_CTL(pipe);
  1989. temp = I915_READ(reg);
  1990. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1991. temp |= snb_b_fdi_train_param[i];
  1992. I915_WRITE(reg, temp);
  1993. POSTING_READ(reg);
  1994. udelay(500);
  1995. reg = FDI_RX_IIR(pipe);
  1996. temp = I915_READ(reg);
  1997. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1998. if (temp & FDI_RX_BIT_LOCK) {
  1999. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2000. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2001. break;
  2002. }
  2003. }
  2004. if (i == 4)
  2005. DRM_ERROR("FDI train 1 fail!\n");
  2006. /* Train 2 */
  2007. reg = FDI_TX_CTL(pipe);
  2008. temp = I915_READ(reg);
  2009. temp &= ~FDI_LINK_TRAIN_NONE;
  2010. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2011. if (IS_GEN6(dev)) {
  2012. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2013. /* SNB-B */
  2014. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2015. }
  2016. I915_WRITE(reg, temp);
  2017. reg = FDI_RX_CTL(pipe);
  2018. temp = I915_READ(reg);
  2019. if (HAS_PCH_CPT(dev)) {
  2020. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2021. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2022. } else {
  2023. temp &= ~FDI_LINK_TRAIN_NONE;
  2024. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2025. }
  2026. I915_WRITE(reg, temp);
  2027. POSTING_READ(reg);
  2028. udelay(150);
  2029. for (i = 0; i < 4; i++ ) {
  2030. reg = FDI_TX_CTL(pipe);
  2031. temp = I915_READ(reg);
  2032. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2033. temp |= snb_b_fdi_train_param[i];
  2034. I915_WRITE(reg, temp);
  2035. POSTING_READ(reg);
  2036. udelay(500);
  2037. reg = FDI_RX_IIR(pipe);
  2038. temp = I915_READ(reg);
  2039. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2040. if (temp & FDI_RX_SYMBOL_LOCK) {
  2041. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2042. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2043. break;
  2044. }
  2045. }
  2046. if (i == 4)
  2047. DRM_ERROR("FDI train 2 fail!\n");
  2048. DRM_DEBUG_KMS("FDI train done.\n");
  2049. }
  2050. /* Manual link training for Ivy Bridge A0 parts */
  2051. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2052. {
  2053. struct drm_device *dev = crtc->dev;
  2054. struct drm_i915_private *dev_priv = dev->dev_private;
  2055. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2056. int pipe = intel_crtc->pipe;
  2057. u32 reg, temp, i;
  2058. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2059. for train result */
  2060. reg = FDI_RX_IMR(pipe);
  2061. temp = I915_READ(reg);
  2062. temp &= ~FDI_RX_SYMBOL_LOCK;
  2063. temp &= ~FDI_RX_BIT_LOCK;
  2064. I915_WRITE(reg, temp);
  2065. POSTING_READ(reg);
  2066. udelay(150);
  2067. /* enable CPU FDI TX and PCH FDI RX */
  2068. reg = FDI_TX_CTL(pipe);
  2069. temp = I915_READ(reg);
  2070. temp &= ~(7 << 19);
  2071. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2072. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2073. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2074. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2075. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2076. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2077. reg = FDI_RX_CTL(pipe);
  2078. temp = I915_READ(reg);
  2079. temp &= ~FDI_LINK_TRAIN_AUTO;
  2080. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2081. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2082. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2083. POSTING_READ(reg);
  2084. udelay(150);
  2085. if (HAS_PCH_CPT(dev))
  2086. cpt_phase_pointer_enable(dev, pipe);
  2087. for (i = 0; i < 4; i++ ) {
  2088. reg = FDI_TX_CTL(pipe);
  2089. temp = I915_READ(reg);
  2090. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2091. temp |= snb_b_fdi_train_param[i];
  2092. I915_WRITE(reg, temp);
  2093. POSTING_READ(reg);
  2094. udelay(500);
  2095. reg = FDI_RX_IIR(pipe);
  2096. temp = I915_READ(reg);
  2097. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2098. if (temp & FDI_RX_BIT_LOCK ||
  2099. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2100. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2101. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2102. break;
  2103. }
  2104. }
  2105. if (i == 4)
  2106. DRM_ERROR("FDI train 1 fail!\n");
  2107. /* Train 2 */
  2108. reg = FDI_TX_CTL(pipe);
  2109. temp = I915_READ(reg);
  2110. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2111. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2112. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2113. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2114. I915_WRITE(reg, temp);
  2115. reg = FDI_RX_CTL(pipe);
  2116. temp = I915_READ(reg);
  2117. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2118. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2119. I915_WRITE(reg, temp);
  2120. POSTING_READ(reg);
  2121. udelay(150);
  2122. for (i = 0; i < 4; i++ ) {
  2123. reg = FDI_TX_CTL(pipe);
  2124. temp = I915_READ(reg);
  2125. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2126. temp |= snb_b_fdi_train_param[i];
  2127. I915_WRITE(reg, temp);
  2128. POSTING_READ(reg);
  2129. udelay(500);
  2130. reg = FDI_RX_IIR(pipe);
  2131. temp = I915_READ(reg);
  2132. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2133. if (temp & FDI_RX_SYMBOL_LOCK) {
  2134. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2135. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2136. break;
  2137. }
  2138. }
  2139. if (i == 4)
  2140. DRM_ERROR("FDI train 2 fail!\n");
  2141. DRM_DEBUG_KMS("FDI train done.\n");
  2142. }
  2143. static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
  2144. {
  2145. struct drm_device *dev = crtc->dev;
  2146. struct drm_i915_private *dev_priv = dev->dev_private;
  2147. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2148. int pipe = intel_crtc->pipe;
  2149. u32 reg, temp;
  2150. /* Write the TU size bits so error detection works */
  2151. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  2152. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  2153. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2154. reg = FDI_RX_CTL(pipe);
  2155. temp = I915_READ(reg);
  2156. temp &= ~((0x7 << 19) | (0x7 << 16));
  2157. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2158. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2159. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2160. POSTING_READ(reg);
  2161. udelay(200);
  2162. /* Switch from Rawclk to PCDclk */
  2163. temp = I915_READ(reg);
  2164. I915_WRITE(reg, temp | FDI_PCDCLK);
  2165. POSTING_READ(reg);
  2166. udelay(200);
  2167. /* Enable CPU FDI TX PLL, always on for Ironlake */
  2168. reg = FDI_TX_CTL(pipe);
  2169. temp = I915_READ(reg);
  2170. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2171. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2172. POSTING_READ(reg);
  2173. udelay(100);
  2174. }
  2175. }
  2176. static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
  2177. {
  2178. struct drm_i915_private *dev_priv = dev->dev_private;
  2179. u32 flags = I915_READ(SOUTH_CHICKEN1);
  2180. flags &= ~(FDI_PHASE_SYNC_EN(pipe));
  2181. I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
  2182. flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
  2183. I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
  2184. POSTING_READ(SOUTH_CHICKEN1);
  2185. }
  2186. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2187. {
  2188. struct drm_device *dev = crtc->dev;
  2189. struct drm_i915_private *dev_priv = dev->dev_private;
  2190. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2191. int pipe = intel_crtc->pipe;
  2192. u32 reg, temp;
  2193. /* disable CPU FDI tx and PCH FDI rx */
  2194. reg = FDI_TX_CTL(pipe);
  2195. temp = I915_READ(reg);
  2196. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2197. POSTING_READ(reg);
  2198. reg = FDI_RX_CTL(pipe);
  2199. temp = I915_READ(reg);
  2200. temp &= ~(0x7 << 16);
  2201. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2202. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2203. POSTING_READ(reg);
  2204. udelay(100);
  2205. /* Ironlake workaround, disable clock pointer after downing FDI */
  2206. if (HAS_PCH_IBX(dev)) {
  2207. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2208. I915_WRITE(FDI_RX_CHICKEN(pipe),
  2209. I915_READ(FDI_RX_CHICKEN(pipe) &
  2210. ~FDI_RX_PHASE_SYNC_POINTER_EN));
  2211. } else if (HAS_PCH_CPT(dev)) {
  2212. cpt_phase_pointer_disable(dev, pipe);
  2213. }
  2214. /* still set train pattern 1 */
  2215. reg = FDI_TX_CTL(pipe);
  2216. temp = I915_READ(reg);
  2217. temp &= ~FDI_LINK_TRAIN_NONE;
  2218. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2219. I915_WRITE(reg, temp);
  2220. reg = FDI_RX_CTL(pipe);
  2221. temp = I915_READ(reg);
  2222. if (HAS_PCH_CPT(dev)) {
  2223. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2224. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2225. } else {
  2226. temp &= ~FDI_LINK_TRAIN_NONE;
  2227. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2228. }
  2229. /* BPC in FDI rx is consistent with that in PIPECONF */
  2230. temp &= ~(0x07 << 16);
  2231. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2232. I915_WRITE(reg, temp);
  2233. POSTING_READ(reg);
  2234. udelay(100);
  2235. }
  2236. /*
  2237. * When we disable a pipe, we need to clear any pending scanline wait events
  2238. * to avoid hanging the ring, which we assume we are waiting on.
  2239. */
  2240. static void intel_clear_scanline_wait(struct drm_device *dev)
  2241. {
  2242. struct drm_i915_private *dev_priv = dev->dev_private;
  2243. struct intel_ring_buffer *ring;
  2244. u32 tmp;
  2245. if (IS_GEN2(dev))
  2246. /* Can't break the hang on i8xx */
  2247. return;
  2248. ring = LP_RING(dev_priv);
  2249. tmp = I915_READ_CTL(ring);
  2250. if (tmp & RING_WAIT)
  2251. I915_WRITE_CTL(ring, tmp);
  2252. }
  2253. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2254. {
  2255. struct drm_i915_gem_object *obj;
  2256. struct drm_i915_private *dev_priv;
  2257. if (crtc->fb == NULL)
  2258. return;
  2259. obj = to_intel_framebuffer(crtc->fb)->obj;
  2260. dev_priv = crtc->dev->dev_private;
  2261. wait_event(dev_priv->pending_flip_queue,
  2262. atomic_read(&obj->pending_flip) == 0);
  2263. }
  2264. static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
  2265. {
  2266. struct drm_device *dev = crtc->dev;
  2267. struct drm_mode_config *mode_config = &dev->mode_config;
  2268. struct intel_encoder *encoder;
  2269. /*
  2270. * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
  2271. * must be driven by its own crtc; no sharing is possible.
  2272. */
  2273. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  2274. if (encoder->base.crtc != crtc)
  2275. continue;
  2276. switch (encoder->type) {
  2277. case INTEL_OUTPUT_EDP:
  2278. if (!intel_encoder_is_pch_edp(&encoder->base))
  2279. return false;
  2280. continue;
  2281. }
  2282. }
  2283. return true;
  2284. }
  2285. /*
  2286. * Enable PCH resources required for PCH ports:
  2287. * - PCH PLLs
  2288. * - FDI training & RX/TX
  2289. * - update transcoder timings
  2290. * - DP transcoding bits
  2291. * - transcoder
  2292. */
  2293. static void ironlake_pch_enable(struct drm_crtc *crtc)
  2294. {
  2295. struct drm_device *dev = crtc->dev;
  2296. struct drm_i915_private *dev_priv = dev->dev_private;
  2297. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2298. int pipe = intel_crtc->pipe;
  2299. u32 reg, temp;
  2300. /* For PCH output, training FDI link */
  2301. dev_priv->display.fdi_link_train(crtc);
  2302. intel_enable_pch_pll(dev_priv, pipe);
  2303. if (HAS_PCH_CPT(dev)) {
  2304. /* Be sure PCH DPLL SEL is set */
  2305. temp = I915_READ(PCH_DPLL_SEL);
  2306. if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
  2307. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  2308. else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
  2309. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  2310. I915_WRITE(PCH_DPLL_SEL, temp);
  2311. }
  2312. /* set transcoder timing, panel must allow it */
  2313. assert_panel_unlocked(dev_priv, pipe);
  2314. I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
  2315. I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
  2316. I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
  2317. I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
  2318. I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
  2319. I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
  2320. intel_fdi_normal_train(crtc);
  2321. /* For PCH DP, enable TRANS_DP_CTL */
  2322. if (HAS_PCH_CPT(dev) &&
  2323. intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  2324. reg = TRANS_DP_CTL(pipe);
  2325. temp = I915_READ(reg);
  2326. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  2327. TRANS_DP_SYNC_MASK |
  2328. TRANS_DP_BPC_MASK);
  2329. temp |= (TRANS_DP_OUTPUT_ENABLE |
  2330. TRANS_DP_ENH_FRAMING);
  2331. temp |= TRANS_DP_8BPC;
  2332. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  2333. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  2334. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  2335. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  2336. switch (intel_trans_dp_port_sel(crtc)) {
  2337. case PCH_DP_B:
  2338. temp |= TRANS_DP_PORT_SEL_B;
  2339. break;
  2340. case PCH_DP_C:
  2341. temp |= TRANS_DP_PORT_SEL_C;
  2342. break;
  2343. case PCH_DP_D:
  2344. temp |= TRANS_DP_PORT_SEL_D;
  2345. break;
  2346. default:
  2347. DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
  2348. temp |= TRANS_DP_PORT_SEL_B;
  2349. break;
  2350. }
  2351. I915_WRITE(reg, temp);
  2352. }
  2353. intel_enable_transcoder(dev_priv, pipe);
  2354. }
  2355. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  2356. {
  2357. struct drm_device *dev = crtc->dev;
  2358. struct drm_i915_private *dev_priv = dev->dev_private;
  2359. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2360. int pipe = intel_crtc->pipe;
  2361. int plane = intel_crtc->plane;
  2362. u32 temp;
  2363. bool is_pch_port;
  2364. if (intel_crtc->active)
  2365. return;
  2366. intel_crtc->active = true;
  2367. intel_update_watermarks(dev);
  2368. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  2369. temp = I915_READ(PCH_LVDS);
  2370. if ((temp & LVDS_PORT_EN) == 0)
  2371. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  2372. }
  2373. is_pch_port = intel_crtc_driving_pch(crtc);
  2374. if (is_pch_port)
  2375. ironlake_fdi_pll_enable(crtc);
  2376. else
  2377. ironlake_fdi_disable(crtc);
  2378. /* Enable panel fitting for LVDS */
  2379. if (dev_priv->pch_pf_size &&
  2380. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
  2381. /* Force use of hard-coded filter coefficients
  2382. * as some pre-programmed values are broken,
  2383. * e.g. x201.
  2384. */
  2385. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  2386. I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
  2387. I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
  2388. }
  2389. /*
  2390. * On ILK+ LUT must be loaded before the pipe is running but with
  2391. * clocks enabled
  2392. */
  2393. intel_crtc_load_lut(crtc);
  2394. intel_enable_pipe(dev_priv, pipe, is_pch_port);
  2395. intel_enable_plane(dev_priv, plane, pipe);
  2396. if (is_pch_port)
  2397. ironlake_pch_enable(crtc);
  2398. mutex_lock(&dev->struct_mutex);
  2399. intel_update_fbc(dev);
  2400. mutex_unlock(&dev->struct_mutex);
  2401. intel_crtc_update_cursor(crtc, true);
  2402. }
  2403. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  2404. {
  2405. struct drm_device *dev = crtc->dev;
  2406. struct drm_i915_private *dev_priv = dev->dev_private;
  2407. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2408. int pipe = intel_crtc->pipe;
  2409. int plane = intel_crtc->plane;
  2410. u32 reg, temp;
  2411. if (!intel_crtc->active)
  2412. return;
  2413. intel_crtc_wait_for_pending_flips(crtc);
  2414. drm_vblank_off(dev, pipe);
  2415. intel_crtc_update_cursor(crtc, false);
  2416. intel_disable_plane(dev_priv, plane, pipe);
  2417. if (dev_priv->cfb_plane == plane &&
  2418. dev_priv->display.disable_fbc)
  2419. dev_priv->display.disable_fbc(dev);
  2420. intel_disable_pipe(dev_priv, pipe);
  2421. /* Disable PF */
  2422. I915_WRITE(PF_CTL(pipe), 0);
  2423. I915_WRITE(PF_WIN_SZ(pipe), 0);
  2424. ironlake_fdi_disable(crtc);
  2425. /* This is a horrible layering violation; we should be doing this in
  2426. * the connector/encoder ->prepare instead, but we don't always have
  2427. * enough information there about the config to know whether it will
  2428. * actually be necessary or just cause undesired flicker.
  2429. */
  2430. intel_disable_pch_ports(dev_priv, pipe);
  2431. intel_disable_transcoder(dev_priv, pipe);
  2432. if (HAS_PCH_CPT(dev)) {
  2433. /* disable TRANS_DP_CTL */
  2434. reg = TRANS_DP_CTL(pipe);
  2435. temp = I915_READ(reg);
  2436. temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  2437. temp |= TRANS_DP_PORT_SEL_NONE;
  2438. I915_WRITE(reg, temp);
  2439. /* disable DPLL_SEL */
  2440. temp = I915_READ(PCH_DPLL_SEL);
  2441. switch (pipe) {
  2442. case 0:
  2443. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  2444. break;
  2445. case 1:
  2446. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  2447. break;
  2448. case 2:
  2449. /* FIXME: manage transcoder PLLs? */
  2450. temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
  2451. break;
  2452. default:
  2453. BUG(); /* wtf */
  2454. }
  2455. I915_WRITE(PCH_DPLL_SEL, temp);
  2456. }
  2457. /* disable PCH DPLL */
  2458. intel_disable_pch_pll(dev_priv, pipe);
  2459. /* Switch from PCDclk to Rawclk */
  2460. reg = FDI_RX_CTL(pipe);
  2461. temp = I915_READ(reg);
  2462. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2463. /* Disable CPU FDI TX PLL */
  2464. reg = FDI_TX_CTL(pipe);
  2465. temp = I915_READ(reg);
  2466. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2467. POSTING_READ(reg);
  2468. udelay(100);
  2469. reg = FDI_RX_CTL(pipe);
  2470. temp = I915_READ(reg);
  2471. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2472. /* Wait for the clocks to turn off. */
  2473. POSTING_READ(reg);
  2474. udelay(100);
  2475. intel_crtc->active = false;
  2476. intel_update_watermarks(dev);
  2477. mutex_lock(&dev->struct_mutex);
  2478. intel_update_fbc(dev);
  2479. intel_clear_scanline_wait(dev);
  2480. mutex_unlock(&dev->struct_mutex);
  2481. }
  2482. static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
  2483. {
  2484. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2485. int pipe = intel_crtc->pipe;
  2486. int plane = intel_crtc->plane;
  2487. /* XXX: When our outputs are all unaware of DPMS modes other than off
  2488. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  2489. */
  2490. switch (mode) {
  2491. case DRM_MODE_DPMS_ON:
  2492. case DRM_MODE_DPMS_STANDBY:
  2493. case DRM_MODE_DPMS_SUSPEND:
  2494. DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
  2495. ironlake_crtc_enable(crtc);
  2496. break;
  2497. case DRM_MODE_DPMS_OFF:
  2498. DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
  2499. ironlake_crtc_disable(crtc);
  2500. break;
  2501. }
  2502. }
  2503. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  2504. {
  2505. if (!enable && intel_crtc->overlay) {
  2506. struct drm_device *dev = intel_crtc->base.dev;
  2507. struct drm_i915_private *dev_priv = dev->dev_private;
  2508. mutex_lock(&dev->struct_mutex);
  2509. dev_priv->mm.interruptible = false;
  2510. (void) intel_overlay_switch_off(intel_crtc->overlay);
  2511. dev_priv->mm.interruptible = true;
  2512. mutex_unlock(&dev->struct_mutex);
  2513. }
  2514. /* Let userspace switch the overlay on again. In most cases userspace
  2515. * has to recompute where to put it anyway.
  2516. */
  2517. }
  2518. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  2519. {
  2520. struct drm_device *dev = crtc->dev;
  2521. struct drm_i915_private *dev_priv = dev->dev_private;
  2522. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2523. int pipe = intel_crtc->pipe;
  2524. int plane = intel_crtc->plane;
  2525. if (intel_crtc->active)
  2526. return;
  2527. intel_crtc->active = true;
  2528. intel_update_watermarks(dev);
  2529. intel_enable_pll(dev_priv, pipe);
  2530. intel_enable_pipe(dev_priv, pipe, false);
  2531. intel_enable_plane(dev_priv, plane, pipe);
  2532. intel_crtc_load_lut(crtc);
  2533. intel_update_fbc(dev);
  2534. /* Give the overlay scaler a chance to enable if it's on this pipe */
  2535. intel_crtc_dpms_overlay(intel_crtc, true);
  2536. intel_crtc_update_cursor(crtc, true);
  2537. }
  2538. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  2539. {
  2540. struct drm_device *dev = crtc->dev;
  2541. struct drm_i915_private *dev_priv = dev->dev_private;
  2542. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2543. int pipe = intel_crtc->pipe;
  2544. int plane = intel_crtc->plane;
  2545. if (!intel_crtc->active)
  2546. return;
  2547. /* Give the overlay scaler a chance to disable if it's on this pipe */
  2548. intel_crtc_wait_for_pending_flips(crtc);
  2549. drm_vblank_off(dev, pipe);
  2550. intel_crtc_dpms_overlay(intel_crtc, false);
  2551. intel_crtc_update_cursor(crtc, false);
  2552. if (dev_priv->cfb_plane == plane &&
  2553. dev_priv->display.disable_fbc)
  2554. dev_priv->display.disable_fbc(dev);
  2555. intel_disable_plane(dev_priv, plane, pipe);
  2556. intel_disable_pipe(dev_priv, pipe);
  2557. intel_disable_pll(dev_priv, pipe);
  2558. intel_crtc->active = false;
  2559. intel_update_fbc(dev);
  2560. intel_update_watermarks(dev);
  2561. intel_clear_scanline_wait(dev);
  2562. }
  2563. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  2564. {
  2565. /* XXX: When our outputs are all unaware of DPMS modes other than off
  2566. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  2567. */
  2568. switch (mode) {
  2569. case DRM_MODE_DPMS_ON:
  2570. case DRM_MODE_DPMS_STANDBY:
  2571. case DRM_MODE_DPMS_SUSPEND:
  2572. i9xx_crtc_enable(crtc);
  2573. break;
  2574. case DRM_MODE_DPMS_OFF:
  2575. i9xx_crtc_disable(crtc);
  2576. break;
  2577. }
  2578. }
  2579. /**
  2580. * Sets the power management mode of the pipe and plane.
  2581. */
  2582. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  2583. {
  2584. struct drm_device *dev = crtc->dev;
  2585. struct drm_i915_private *dev_priv = dev->dev_private;
  2586. struct drm_i915_master_private *master_priv;
  2587. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2588. int pipe = intel_crtc->pipe;
  2589. bool enabled;
  2590. if (intel_crtc->dpms_mode == mode)
  2591. return;
  2592. intel_crtc->dpms_mode = mode;
  2593. dev_priv->display.dpms(crtc, mode);
  2594. if (!dev->primary->master)
  2595. return;
  2596. master_priv = dev->primary->master->driver_priv;
  2597. if (!master_priv->sarea_priv)
  2598. return;
  2599. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  2600. switch (pipe) {
  2601. case 0:
  2602. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  2603. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  2604. break;
  2605. case 1:
  2606. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  2607. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  2608. break;
  2609. default:
  2610. DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  2611. break;
  2612. }
  2613. }
  2614. static void intel_crtc_disable(struct drm_crtc *crtc)
  2615. {
  2616. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  2617. struct drm_device *dev = crtc->dev;
  2618. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  2619. if (crtc->fb) {
  2620. mutex_lock(&dev->struct_mutex);
  2621. i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
  2622. mutex_unlock(&dev->struct_mutex);
  2623. }
  2624. }
  2625. /* Prepare for a mode set.
  2626. *
  2627. * Note we could be a lot smarter here. We need to figure out which outputs
  2628. * will be enabled, which disabled (in short, how the config will changes)
  2629. * and perform the minimum necessary steps to accomplish that, e.g. updating
  2630. * watermarks, FBC configuration, making sure PLLs are programmed correctly,
  2631. * panel fitting is in the proper state, etc.
  2632. */
  2633. static void i9xx_crtc_prepare(struct drm_crtc *crtc)
  2634. {
  2635. i9xx_crtc_disable(crtc);
  2636. }
  2637. static void i9xx_crtc_commit(struct drm_crtc *crtc)
  2638. {
  2639. i9xx_crtc_enable(crtc);
  2640. }
  2641. static void ironlake_crtc_prepare(struct drm_crtc *crtc)
  2642. {
  2643. ironlake_crtc_disable(crtc);
  2644. }
  2645. static void ironlake_crtc_commit(struct drm_crtc *crtc)
  2646. {
  2647. ironlake_crtc_enable(crtc);
  2648. }
  2649. void intel_encoder_prepare (struct drm_encoder *encoder)
  2650. {
  2651. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2652. /* lvds has its own version of prepare see intel_lvds_prepare */
  2653. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  2654. }
  2655. void intel_encoder_commit (struct drm_encoder *encoder)
  2656. {
  2657. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2658. /* lvds has its own version of commit see intel_lvds_commit */
  2659. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  2660. }
  2661. void intel_encoder_destroy(struct drm_encoder *encoder)
  2662. {
  2663. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  2664. drm_encoder_cleanup(encoder);
  2665. kfree(intel_encoder);
  2666. }
  2667. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  2668. struct drm_display_mode *mode,
  2669. struct drm_display_mode *adjusted_mode)
  2670. {
  2671. struct drm_device *dev = crtc->dev;
  2672. if (HAS_PCH_SPLIT(dev)) {
  2673. /* FDI link clock is fixed at 2.7G */
  2674. if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
  2675. return false;
  2676. }
  2677. /* XXX some encoders set the crtcinfo, others don't.
  2678. * Obviously we need some form of conflict resolution here...
  2679. */
  2680. if (adjusted_mode->crtc_htotal == 0)
  2681. drm_mode_set_crtcinfo(adjusted_mode, 0);
  2682. return true;
  2683. }
  2684. static int i945_get_display_clock_speed(struct drm_device *dev)
  2685. {
  2686. return 400000;
  2687. }
  2688. static int i915_get_display_clock_speed(struct drm_device *dev)
  2689. {
  2690. return 333000;
  2691. }
  2692. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  2693. {
  2694. return 200000;
  2695. }
  2696. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  2697. {
  2698. u16 gcfgc = 0;
  2699. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  2700. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  2701. return 133000;
  2702. else {
  2703. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  2704. case GC_DISPLAY_CLOCK_333_MHZ:
  2705. return 333000;
  2706. default:
  2707. case GC_DISPLAY_CLOCK_190_200_MHZ:
  2708. return 190000;
  2709. }
  2710. }
  2711. }
  2712. static int i865_get_display_clock_speed(struct drm_device *dev)
  2713. {
  2714. return 266000;
  2715. }
  2716. static int i855_get_display_clock_speed(struct drm_device *dev)
  2717. {
  2718. u16 hpllcc = 0;
  2719. /* Assume that the hardware is in the high speed state. This
  2720. * should be the default.
  2721. */
  2722. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  2723. case GC_CLOCK_133_200:
  2724. case GC_CLOCK_100_200:
  2725. return 200000;
  2726. case GC_CLOCK_166_250:
  2727. return 250000;
  2728. case GC_CLOCK_100_133:
  2729. return 133000;
  2730. }
  2731. /* Shouldn't happen */
  2732. return 0;
  2733. }
  2734. static int i830_get_display_clock_speed(struct drm_device *dev)
  2735. {
  2736. return 133000;
  2737. }
  2738. struct fdi_m_n {
  2739. u32 tu;
  2740. u32 gmch_m;
  2741. u32 gmch_n;
  2742. u32 link_m;
  2743. u32 link_n;
  2744. };
  2745. static void
  2746. fdi_reduce_ratio(u32 *num, u32 *den)
  2747. {
  2748. while (*num > 0xffffff || *den > 0xffffff) {
  2749. *num >>= 1;
  2750. *den >>= 1;
  2751. }
  2752. }
  2753. static void
  2754. ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
  2755. int link_clock, struct fdi_m_n *m_n)
  2756. {
  2757. m_n->tu = 64; /* default size */
  2758. /* BUG_ON(pixel_clock > INT_MAX / 36); */
  2759. m_n->gmch_m = bits_per_pixel * pixel_clock;
  2760. m_n->gmch_n = link_clock * nlanes * 8;
  2761. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  2762. m_n->link_m = pixel_clock;
  2763. m_n->link_n = link_clock;
  2764. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  2765. }
  2766. struct intel_watermark_params {
  2767. unsigned long fifo_size;
  2768. unsigned long max_wm;
  2769. unsigned long default_wm;
  2770. unsigned long guard_size;
  2771. unsigned long cacheline_size;
  2772. };
  2773. /* Pineview has different values for various configs */
  2774. static const struct intel_watermark_params pineview_display_wm = {
  2775. PINEVIEW_DISPLAY_FIFO,
  2776. PINEVIEW_MAX_WM,
  2777. PINEVIEW_DFT_WM,
  2778. PINEVIEW_GUARD_WM,
  2779. PINEVIEW_FIFO_LINE_SIZE
  2780. };
  2781. static const struct intel_watermark_params pineview_display_hplloff_wm = {
  2782. PINEVIEW_DISPLAY_FIFO,
  2783. PINEVIEW_MAX_WM,
  2784. PINEVIEW_DFT_HPLLOFF_WM,
  2785. PINEVIEW_GUARD_WM,
  2786. PINEVIEW_FIFO_LINE_SIZE
  2787. };
  2788. static const struct intel_watermark_params pineview_cursor_wm = {
  2789. PINEVIEW_CURSOR_FIFO,
  2790. PINEVIEW_CURSOR_MAX_WM,
  2791. PINEVIEW_CURSOR_DFT_WM,
  2792. PINEVIEW_CURSOR_GUARD_WM,
  2793. PINEVIEW_FIFO_LINE_SIZE,
  2794. };
  2795. static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
  2796. PINEVIEW_CURSOR_FIFO,
  2797. PINEVIEW_CURSOR_MAX_WM,
  2798. PINEVIEW_CURSOR_DFT_WM,
  2799. PINEVIEW_CURSOR_GUARD_WM,
  2800. PINEVIEW_FIFO_LINE_SIZE
  2801. };
  2802. static const struct intel_watermark_params g4x_wm_info = {
  2803. G4X_FIFO_SIZE,
  2804. G4X_MAX_WM,
  2805. G4X_MAX_WM,
  2806. 2,
  2807. G4X_FIFO_LINE_SIZE,
  2808. };
  2809. static const struct intel_watermark_params g4x_cursor_wm_info = {
  2810. I965_CURSOR_FIFO,
  2811. I965_CURSOR_MAX_WM,
  2812. I965_CURSOR_DFT_WM,
  2813. 2,
  2814. G4X_FIFO_LINE_SIZE,
  2815. };
  2816. static const struct intel_watermark_params i965_cursor_wm_info = {
  2817. I965_CURSOR_FIFO,
  2818. I965_CURSOR_MAX_WM,
  2819. I965_CURSOR_DFT_WM,
  2820. 2,
  2821. I915_FIFO_LINE_SIZE,
  2822. };
  2823. static const struct intel_watermark_params i945_wm_info = {
  2824. I945_FIFO_SIZE,
  2825. I915_MAX_WM,
  2826. 1,
  2827. 2,
  2828. I915_FIFO_LINE_SIZE
  2829. };
  2830. static const struct intel_watermark_params i915_wm_info = {
  2831. I915_FIFO_SIZE,
  2832. I915_MAX_WM,
  2833. 1,
  2834. 2,
  2835. I915_FIFO_LINE_SIZE
  2836. };
  2837. static const struct intel_watermark_params i855_wm_info = {
  2838. I855GM_FIFO_SIZE,
  2839. I915_MAX_WM,
  2840. 1,
  2841. 2,
  2842. I830_FIFO_LINE_SIZE
  2843. };
  2844. static const struct intel_watermark_params i830_wm_info = {
  2845. I830_FIFO_SIZE,
  2846. I915_MAX_WM,
  2847. 1,
  2848. 2,
  2849. I830_FIFO_LINE_SIZE
  2850. };
  2851. static const struct intel_watermark_params ironlake_display_wm_info = {
  2852. ILK_DISPLAY_FIFO,
  2853. ILK_DISPLAY_MAXWM,
  2854. ILK_DISPLAY_DFTWM,
  2855. 2,
  2856. ILK_FIFO_LINE_SIZE
  2857. };
  2858. static const struct intel_watermark_params ironlake_cursor_wm_info = {
  2859. ILK_CURSOR_FIFO,
  2860. ILK_CURSOR_MAXWM,
  2861. ILK_CURSOR_DFTWM,
  2862. 2,
  2863. ILK_FIFO_LINE_SIZE
  2864. };
  2865. static const struct intel_watermark_params ironlake_display_srwm_info = {
  2866. ILK_DISPLAY_SR_FIFO,
  2867. ILK_DISPLAY_MAX_SRWM,
  2868. ILK_DISPLAY_DFT_SRWM,
  2869. 2,
  2870. ILK_FIFO_LINE_SIZE
  2871. };
  2872. static const struct intel_watermark_params ironlake_cursor_srwm_info = {
  2873. ILK_CURSOR_SR_FIFO,
  2874. ILK_CURSOR_MAX_SRWM,
  2875. ILK_CURSOR_DFT_SRWM,
  2876. 2,
  2877. ILK_FIFO_LINE_SIZE
  2878. };
  2879. static const struct intel_watermark_params sandybridge_display_wm_info = {
  2880. SNB_DISPLAY_FIFO,
  2881. SNB_DISPLAY_MAXWM,
  2882. SNB_DISPLAY_DFTWM,
  2883. 2,
  2884. SNB_FIFO_LINE_SIZE
  2885. };
  2886. static const struct intel_watermark_params sandybridge_cursor_wm_info = {
  2887. SNB_CURSOR_FIFO,
  2888. SNB_CURSOR_MAXWM,
  2889. SNB_CURSOR_DFTWM,
  2890. 2,
  2891. SNB_FIFO_LINE_SIZE
  2892. };
  2893. static const struct intel_watermark_params sandybridge_display_srwm_info = {
  2894. SNB_DISPLAY_SR_FIFO,
  2895. SNB_DISPLAY_MAX_SRWM,
  2896. SNB_DISPLAY_DFT_SRWM,
  2897. 2,
  2898. SNB_FIFO_LINE_SIZE
  2899. };
  2900. static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
  2901. SNB_CURSOR_SR_FIFO,
  2902. SNB_CURSOR_MAX_SRWM,
  2903. SNB_CURSOR_DFT_SRWM,
  2904. 2,
  2905. SNB_FIFO_LINE_SIZE
  2906. };
  2907. /**
  2908. * intel_calculate_wm - calculate watermark level
  2909. * @clock_in_khz: pixel clock
  2910. * @wm: chip FIFO params
  2911. * @pixel_size: display pixel size
  2912. * @latency_ns: memory latency for the platform
  2913. *
  2914. * Calculate the watermark level (the level at which the display plane will
  2915. * start fetching from memory again). Each chip has a different display
  2916. * FIFO size and allocation, so the caller needs to figure that out and pass
  2917. * in the correct intel_watermark_params structure.
  2918. *
  2919. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  2920. * on the pixel size. When it reaches the watermark level, it'll start
  2921. * fetching FIFO line sized based chunks from memory until the FIFO fills
  2922. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  2923. * will occur, and a display engine hang could result.
  2924. */
  2925. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  2926. const struct intel_watermark_params *wm,
  2927. int fifo_size,
  2928. int pixel_size,
  2929. unsigned long latency_ns)
  2930. {
  2931. long entries_required, wm_size;
  2932. /*
  2933. * Note: we need to make sure we don't overflow for various clock &
  2934. * latency values.
  2935. * clocks go from a few thousand to several hundred thousand.
  2936. * latency is usually a few thousand
  2937. */
  2938. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  2939. 1000;
  2940. entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  2941. DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
  2942. wm_size = fifo_size - (entries_required + wm->guard_size);
  2943. DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
  2944. /* Don't promote wm_size to unsigned... */
  2945. if (wm_size > (long)wm->max_wm)
  2946. wm_size = wm->max_wm;
  2947. if (wm_size <= 0)
  2948. wm_size = wm->default_wm;
  2949. return wm_size;
  2950. }
  2951. struct cxsr_latency {
  2952. int is_desktop;
  2953. int is_ddr3;
  2954. unsigned long fsb_freq;
  2955. unsigned long mem_freq;
  2956. unsigned long display_sr;
  2957. unsigned long display_hpll_disable;
  2958. unsigned long cursor_sr;
  2959. unsigned long cursor_hpll_disable;
  2960. };
  2961. static const struct cxsr_latency cxsr_latency_table[] = {
  2962. {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  2963. {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  2964. {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  2965. {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
  2966. {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
  2967. {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  2968. {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  2969. {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  2970. {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
  2971. {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
  2972. {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  2973. {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  2974. {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  2975. {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
  2976. {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
  2977. {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  2978. {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  2979. {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  2980. {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
  2981. {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
  2982. {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  2983. {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  2984. {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  2985. {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
  2986. {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
  2987. {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  2988. {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  2989. {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  2990. {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
  2991. {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
  2992. };
  2993. static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
  2994. int is_ddr3,
  2995. int fsb,
  2996. int mem)
  2997. {
  2998. const struct cxsr_latency *latency;
  2999. int i;
  3000. if (fsb == 0 || mem == 0)
  3001. return NULL;
  3002. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  3003. latency = &cxsr_latency_table[i];
  3004. if (is_desktop == latency->is_desktop &&
  3005. is_ddr3 == latency->is_ddr3 &&
  3006. fsb == latency->fsb_freq && mem == latency->mem_freq)
  3007. return latency;
  3008. }
  3009. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  3010. return NULL;
  3011. }
  3012. static void pineview_disable_cxsr(struct drm_device *dev)
  3013. {
  3014. struct drm_i915_private *dev_priv = dev->dev_private;
  3015. /* deactivate cxsr */
  3016. I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
  3017. }
  3018. /*
  3019. * Latency for FIFO fetches is dependent on several factors:
  3020. * - memory configuration (speed, channels)
  3021. * - chipset
  3022. * - current MCH state
  3023. * It can be fairly high in some situations, so here we assume a fairly
  3024. * pessimal value. It's a tradeoff between extra memory fetches (if we
  3025. * set this value too high, the FIFO will fetch frequently to stay full)
  3026. * and power consumption (set it too low to save power and we might see
  3027. * FIFO underruns and display "flicker").
  3028. *
  3029. * A value of 5us seems to be a good balance; safe for very low end
  3030. * platforms but not overly aggressive on lower latency configs.
  3031. */
  3032. static const int latency_ns = 5000;
  3033. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  3034. {
  3035. struct drm_i915_private *dev_priv = dev->dev_private;
  3036. uint32_t dsparb = I915_READ(DSPARB);
  3037. int size;
  3038. size = dsparb & 0x7f;
  3039. if (plane)
  3040. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  3041. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3042. plane ? "B" : "A", size);
  3043. return size;
  3044. }
  3045. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  3046. {
  3047. struct drm_i915_private *dev_priv = dev->dev_private;
  3048. uint32_t dsparb = I915_READ(DSPARB);
  3049. int size;
  3050. size = dsparb & 0x1ff;
  3051. if (plane)
  3052. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  3053. size >>= 1; /* Convert to cachelines */
  3054. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3055. plane ? "B" : "A", size);
  3056. return size;
  3057. }
  3058. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  3059. {
  3060. struct drm_i915_private *dev_priv = dev->dev_private;
  3061. uint32_t dsparb = I915_READ(DSPARB);
  3062. int size;
  3063. size = dsparb & 0x7f;
  3064. size >>= 2; /* Convert to cachelines */
  3065. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3066. plane ? "B" : "A",
  3067. size);
  3068. return size;
  3069. }
  3070. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  3071. {
  3072. struct drm_i915_private *dev_priv = dev->dev_private;
  3073. uint32_t dsparb = I915_READ(DSPARB);
  3074. int size;
  3075. size = dsparb & 0x7f;
  3076. size >>= 1; /* Convert to cachelines */
  3077. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3078. plane ? "B" : "A", size);
  3079. return size;
  3080. }
  3081. static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
  3082. {
  3083. struct drm_crtc *crtc, *enabled = NULL;
  3084. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3085. if (crtc->enabled && crtc->fb) {
  3086. if (enabled)
  3087. return NULL;
  3088. enabled = crtc;
  3089. }
  3090. }
  3091. return enabled;
  3092. }
  3093. static void pineview_update_wm(struct drm_device *dev)
  3094. {
  3095. struct drm_i915_private *dev_priv = dev->dev_private;
  3096. struct drm_crtc *crtc;
  3097. const struct cxsr_latency *latency;
  3098. u32 reg;
  3099. unsigned long wm;
  3100. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  3101. dev_priv->fsb_freq, dev_priv->mem_freq);
  3102. if (!latency) {
  3103. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  3104. pineview_disable_cxsr(dev);
  3105. return;
  3106. }
  3107. crtc = single_enabled_crtc(dev);
  3108. if (crtc) {
  3109. int clock = crtc->mode.clock;
  3110. int pixel_size = crtc->fb->bits_per_pixel / 8;
  3111. /* Display SR */
  3112. wm = intel_calculate_wm(clock, &pineview_display_wm,
  3113. pineview_display_wm.fifo_size,
  3114. pixel_size, latency->display_sr);
  3115. reg = I915_READ(DSPFW1);
  3116. reg &= ~DSPFW_SR_MASK;
  3117. reg |= wm << DSPFW_SR_SHIFT;
  3118. I915_WRITE(DSPFW1, reg);
  3119. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  3120. /* cursor SR */
  3121. wm = intel_calculate_wm(clock, &pineview_cursor_wm,
  3122. pineview_display_wm.fifo_size,
  3123. pixel_size, latency->cursor_sr);
  3124. reg = I915_READ(DSPFW3);
  3125. reg &= ~DSPFW_CURSOR_SR_MASK;
  3126. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  3127. I915_WRITE(DSPFW3, reg);
  3128. /* Display HPLL off SR */
  3129. wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
  3130. pineview_display_hplloff_wm.fifo_size,
  3131. pixel_size, latency->display_hpll_disable);
  3132. reg = I915_READ(DSPFW3);
  3133. reg &= ~DSPFW_HPLL_SR_MASK;
  3134. reg |= wm & DSPFW_HPLL_SR_MASK;
  3135. I915_WRITE(DSPFW3, reg);
  3136. /* cursor HPLL off SR */
  3137. wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
  3138. pineview_display_hplloff_wm.fifo_size,
  3139. pixel_size, latency->cursor_hpll_disable);
  3140. reg = I915_READ(DSPFW3);
  3141. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  3142. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  3143. I915_WRITE(DSPFW3, reg);
  3144. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  3145. /* activate cxsr */
  3146. I915_WRITE(DSPFW3,
  3147. I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
  3148. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  3149. } else {
  3150. pineview_disable_cxsr(dev);
  3151. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  3152. }
  3153. }
  3154. static bool g4x_compute_wm0(struct drm_device *dev,
  3155. int plane,
  3156. const struct intel_watermark_params *display,
  3157. int display_latency_ns,
  3158. const struct intel_watermark_params *cursor,
  3159. int cursor_latency_ns,
  3160. int *plane_wm,
  3161. int *cursor_wm)
  3162. {
  3163. struct drm_crtc *crtc;
  3164. int htotal, hdisplay, clock, pixel_size;
  3165. int line_time_us, line_count;
  3166. int entries, tlb_miss;
  3167. crtc = intel_get_crtc_for_plane(dev, plane);
  3168. if (crtc->fb == NULL || !crtc->enabled) {
  3169. *cursor_wm = cursor->guard_size;
  3170. *plane_wm = display->guard_size;
  3171. return false;
  3172. }
  3173. htotal = crtc->mode.htotal;
  3174. hdisplay = crtc->mode.hdisplay;
  3175. clock = crtc->mode.clock;
  3176. pixel_size = crtc->fb->bits_per_pixel / 8;
  3177. /* Use the small buffer method to calculate plane watermark */
  3178. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  3179. tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
  3180. if (tlb_miss > 0)
  3181. entries += tlb_miss;
  3182. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  3183. *plane_wm = entries + display->guard_size;
  3184. if (*plane_wm > (int)display->max_wm)
  3185. *plane_wm = display->max_wm;
  3186. /* Use the large buffer method to calculate cursor watermark */
  3187. line_time_us = ((htotal * 1000) / clock);
  3188. line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
  3189. entries = line_count * 64 * pixel_size;
  3190. tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
  3191. if (tlb_miss > 0)
  3192. entries += tlb_miss;
  3193. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  3194. *cursor_wm = entries + cursor->guard_size;
  3195. if (*cursor_wm > (int)cursor->max_wm)
  3196. *cursor_wm = (int)cursor->max_wm;
  3197. return true;
  3198. }
  3199. /*
  3200. * Check the wm result.
  3201. *
  3202. * If any calculated watermark values is larger than the maximum value that
  3203. * can be programmed into the associated watermark register, that watermark
  3204. * must be disabled.
  3205. */
  3206. static bool g4x_check_srwm(struct drm_device *dev,
  3207. int display_wm, int cursor_wm,
  3208. const struct intel_watermark_params *display,
  3209. const struct intel_watermark_params *cursor)
  3210. {
  3211. DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
  3212. display_wm, cursor_wm);
  3213. if (display_wm > display->max_wm) {
  3214. DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
  3215. display_wm, display->max_wm);
  3216. return false;
  3217. }
  3218. if (cursor_wm > cursor->max_wm) {
  3219. DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
  3220. cursor_wm, cursor->max_wm);
  3221. return false;
  3222. }
  3223. if (!(display_wm || cursor_wm)) {
  3224. DRM_DEBUG_KMS("SR latency is 0, disabling\n");
  3225. return false;
  3226. }
  3227. return true;
  3228. }
  3229. static bool g4x_compute_srwm(struct drm_device *dev,
  3230. int plane,
  3231. int latency_ns,
  3232. const struct intel_watermark_params *display,
  3233. const struct intel_watermark_params *cursor,
  3234. int *display_wm, int *cursor_wm)
  3235. {
  3236. struct drm_crtc *crtc;
  3237. int hdisplay, htotal, pixel_size, clock;
  3238. unsigned long line_time_us;
  3239. int line_count, line_size;
  3240. int small, large;
  3241. int entries;
  3242. if (!latency_ns) {
  3243. *display_wm = *cursor_wm = 0;
  3244. return false;
  3245. }
  3246. crtc = intel_get_crtc_for_plane(dev, plane);
  3247. hdisplay = crtc->mode.hdisplay;
  3248. htotal = crtc->mode.htotal;
  3249. clock = crtc->mode.clock;
  3250. pixel_size = crtc->fb->bits_per_pixel / 8;
  3251. line_time_us = (htotal * 1000) / clock;
  3252. line_count = (latency_ns / line_time_us + 1000) / 1000;
  3253. line_size = hdisplay * pixel_size;
  3254. /* Use the minimum of the small and large buffer method for primary */
  3255. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  3256. large = line_count * line_size;
  3257. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  3258. *display_wm = entries + display->guard_size;
  3259. /* calculate the self-refresh watermark for display cursor */
  3260. entries = line_count * pixel_size * 64;
  3261. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  3262. *cursor_wm = entries + cursor->guard_size;
  3263. return g4x_check_srwm(dev,
  3264. *display_wm, *cursor_wm,
  3265. display, cursor);
  3266. }
  3267. #define single_plane_enabled(mask) is_power_of_2(mask)
  3268. static void g4x_update_wm(struct drm_device *dev)
  3269. {
  3270. static const int sr_latency_ns = 12000;
  3271. struct drm_i915_private *dev_priv = dev->dev_private;
  3272. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  3273. int plane_sr, cursor_sr;
  3274. unsigned int enabled = 0;
  3275. if (g4x_compute_wm0(dev, 0,
  3276. &g4x_wm_info, latency_ns,
  3277. &g4x_cursor_wm_info, latency_ns,
  3278. &planea_wm, &cursora_wm))
  3279. enabled |= 1;
  3280. if (g4x_compute_wm0(dev, 1,
  3281. &g4x_wm_info, latency_ns,
  3282. &g4x_cursor_wm_info, latency_ns,
  3283. &planeb_wm, &cursorb_wm))
  3284. enabled |= 2;
  3285. plane_sr = cursor_sr = 0;
  3286. if (single_plane_enabled(enabled) &&
  3287. g4x_compute_srwm(dev, ffs(enabled) - 1,
  3288. sr_latency_ns,
  3289. &g4x_wm_info,
  3290. &g4x_cursor_wm_info,
  3291. &plane_sr, &cursor_sr))
  3292. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  3293. else
  3294. I915_WRITE(FW_BLC_SELF,
  3295. I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
  3296. DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  3297. planea_wm, cursora_wm,
  3298. planeb_wm, cursorb_wm,
  3299. plane_sr, cursor_sr);
  3300. I915_WRITE(DSPFW1,
  3301. (plane_sr << DSPFW_SR_SHIFT) |
  3302. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  3303. (planeb_wm << DSPFW_PLANEB_SHIFT) |
  3304. planea_wm);
  3305. I915_WRITE(DSPFW2,
  3306. (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  3307. (cursora_wm << DSPFW_CURSORA_SHIFT));
  3308. /* HPLL off in SR has some issues on G4x... disable it */
  3309. I915_WRITE(DSPFW3,
  3310. (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  3311. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  3312. }
  3313. static void i965_update_wm(struct drm_device *dev)
  3314. {
  3315. struct drm_i915_private *dev_priv = dev->dev_private;
  3316. struct drm_crtc *crtc;
  3317. int srwm = 1;
  3318. int cursor_sr = 16;
  3319. /* Calc sr entries for one plane configs */
  3320. crtc = single_enabled_crtc(dev);
  3321. if (crtc) {
  3322. /* self-refresh has much higher latency */
  3323. static const int sr_latency_ns = 12000;
  3324. int clock = crtc->mode.clock;
  3325. int htotal = crtc->mode.htotal;
  3326. int hdisplay = crtc->mode.hdisplay;
  3327. int pixel_size = crtc->fb->bits_per_pixel / 8;
  3328. unsigned long line_time_us;
  3329. int entries;
  3330. line_time_us = ((htotal * 1000) / clock);
  3331. /* Use ns/us then divide to preserve precision */
  3332. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  3333. pixel_size * hdisplay;
  3334. entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
  3335. srwm = I965_FIFO_SIZE - entries;
  3336. if (srwm < 0)
  3337. srwm = 1;
  3338. srwm &= 0x1ff;
  3339. DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
  3340. entries, srwm);
  3341. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  3342. pixel_size * 64;
  3343. entries = DIV_ROUND_UP(entries,
  3344. i965_cursor_wm_info.cacheline_size);
  3345. cursor_sr = i965_cursor_wm_info.fifo_size -
  3346. (entries + i965_cursor_wm_info.guard_size);
  3347. if (cursor_sr > i965_cursor_wm_info.max_wm)
  3348. cursor_sr = i965_cursor_wm_info.max_wm;
  3349. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  3350. "cursor %d\n", srwm, cursor_sr);
  3351. if (IS_CRESTLINE(dev))
  3352. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  3353. } else {
  3354. /* Turn off self refresh if both pipes are enabled */
  3355. if (IS_CRESTLINE(dev))
  3356. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  3357. & ~FW_BLC_SELF_EN);
  3358. }
  3359. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  3360. srwm);
  3361. /* 965 has limitations... */
  3362. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
  3363. (8 << 16) | (8 << 8) | (8 << 0));
  3364. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  3365. /* update cursor SR watermark */
  3366. I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  3367. }
  3368. static void i9xx_update_wm(struct drm_device *dev)
  3369. {
  3370. struct drm_i915_private *dev_priv = dev->dev_private;
  3371. const struct intel_watermark_params *wm_info;
  3372. uint32_t fwater_lo;
  3373. uint32_t fwater_hi;
  3374. int cwm, srwm = 1;
  3375. int fifo_size;
  3376. int planea_wm, planeb_wm;
  3377. struct drm_crtc *crtc, *enabled = NULL;
  3378. if (IS_I945GM(dev))
  3379. wm_info = &i945_wm_info;
  3380. else if (!IS_GEN2(dev))
  3381. wm_info = &i915_wm_info;
  3382. else
  3383. wm_info = &i855_wm_info;
  3384. fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  3385. crtc = intel_get_crtc_for_plane(dev, 0);
  3386. if (crtc->enabled && crtc->fb) {
  3387. planea_wm = intel_calculate_wm(crtc->mode.clock,
  3388. wm_info, fifo_size,
  3389. crtc->fb->bits_per_pixel / 8,
  3390. latency_ns);
  3391. enabled = crtc;
  3392. } else
  3393. planea_wm = fifo_size - wm_info->guard_size;
  3394. fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  3395. crtc = intel_get_crtc_for_plane(dev, 1);
  3396. if (crtc->enabled && crtc->fb) {
  3397. planeb_wm = intel_calculate_wm(crtc->mode.clock,
  3398. wm_info, fifo_size,
  3399. crtc->fb->bits_per_pixel / 8,
  3400. latency_ns);
  3401. if (enabled == NULL)
  3402. enabled = crtc;
  3403. else
  3404. enabled = NULL;
  3405. } else
  3406. planeb_wm = fifo_size - wm_info->guard_size;
  3407. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  3408. /*
  3409. * Overlay gets an aggressive default since video jitter is bad.
  3410. */
  3411. cwm = 2;
  3412. /* Play safe and disable self-refresh before adjusting watermarks. */
  3413. if (IS_I945G(dev) || IS_I945GM(dev))
  3414. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
  3415. else if (IS_I915GM(dev))
  3416. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  3417. /* Calc sr entries for one plane configs */
  3418. if (HAS_FW_BLC(dev) && enabled) {
  3419. /* self-refresh has much higher latency */
  3420. static const int sr_latency_ns = 6000;
  3421. int clock = enabled->mode.clock;
  3422. int htotal = enabled->mode.htotal;
  3423. int hdisplay = enabled->mode.hdisplay;
  3424. int pixel_size = enabled->fb->bits_per_pixel / 8;
  3425. unsigned long line_time_us;
  3426. int entries;
  3427. line_time_us = (htotal * 1000) / clock;
  3428. /* Use ns/us then divide to preserve precision */
  3429. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  3430. pixel_size * hdisplay;
  3431. entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
  3432. DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
  3433. srwm = wm_info->fifo_size - entries;
  3434. if (srwm < 0)
  3435. srwm = 1;
  3436. if (IS_I945G(dev) || IS_I945GM(dev))
  3437. I915_WRITE(FW_BLC_SELF,
  3438. FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  3439. else if (IS_I915GM(dev))
  3440. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  3441. }
  3442. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  3443. planea_wm, planeb_wm, cwm, srwm);
  3444. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  3445. fwater_hi = (cwm & 0x1f);
  3446. /* Set request length to 8 cachelines per fetch */
  3447. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  3448. fwater_hi = fwater_hi | (1 << 8);
  3449. I915_WRITE(FW_BLC, fwater_lo);
  3450. I915_WRITE(FW_BLC2, fwater_hi);
  3451. if (HAS_FW_BLC(dev)) {
  3452. if (enabled) {
  3453. if (IS_I945G(dev) || IS_I945GM(dev))
  3454. I915_WRITE(FW_BLC_SELF,
  3455. FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  3456. else if (IS_I915GM(dev))
  3457. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  3458. DRM_DEBUG_KMS("memory self refresh enabled\n");
  3459. } else
  3460. DRM_DEBUG_KMS("memory self refresh disabled\n");
  3461. }
  3462. }
  3463. static void i830_update_wm(struct drm_device *dev)
  3464. {
  3465. struct drm_i915_private *dev_priv = dev->dev_private;
  3466. struct drm_crtc *crtc;
  3467. uint32_t fwater_lo;
  3468. int planea_wm;
  3469. crtc = single_enabled_crtc(dev);
  3470. if (crtc == NULL)
  3471. return;
  3472. planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
  3473. dev_priv->display.get_fifo_size(dev, 0),
  3474. crtc->fb->bits_per_pixel / 8,
  3475. latency_ns);
  3476. fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  3477. fwater_lo |= (3<<8) | planea_wm;
  3478. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  3479. I915_WRITE(FW_BLC, fwater_lo);
  3480. }
  3481. #define ILK_LP0_PLANE_LATENCY 700
  3482. #define ILK_LP0_CURSOR_LATENCY 1300
  3483. /*
  3484. * Check the wm result.
  3485. *
  3486. * If any calculated watermark values is larger than the maximum value that
  3487. * can be programmed into the associated watermark register, that watermark
  3488. * must be disabled.
  3489. */
  3490. static bool ironlake_check_srwm(struct drm_device *dev, int level,
  3491. int fbc_wm, int display_wm, int cursor_wm,
  3492. const struct intel_watermark_params *display,
  3493. const struct intel_watermark_params *cursor)
  3494. {
  3495. struct drm_i915_private *dev_priv = dev->dev_private;
  3496. DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
  3497. " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
  3498. if (fbc_wm > SNB_FBC_MAX_SRWM) {
  3499. DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
  3500. fbc_wm, SNB_FBC_MAX_SRWM, level);
  3501. /* fbc has it's own way to disable FBC WM */
  3502. I915_WRITE(DISP_ARB_CTL,
  3503. I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
  3504. return false;
  3505. }
  3506. if (display_wm > display->max_wm) {
  3507. DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
  3508. display_wm, SNB_DISPLAY_MAX_SRWM, level);
  3509. return false;
  3510. }
  3511. if (cursor_wm > cursor->max_wm) {
  3512. DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
  3513. cursor_wm, SNB_CURSOR_MAX_SRWM, level);
  3514. return false;
  3515. }
  3516. if (!(fbc_wm || display_wm || cursor_wm)) {
  3517. DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
  3518. return false;
  3519. }
  3520. return true;
  3521. }
  3522. /*
  3523. * Compute watermark values of WM[1-3],
  3524. */
  3525. static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
  3526. int latency_ns,
  3527. const struct intel_watermark_params *display,
  3528. const struct intel_watermark_params *cursor,
  3529. int *fbc_wm, int *display_wm, int *cursor_wm)
  3530. {
  3531. struct drm_crtc *crtc;
  3532. unsigned long line_time_us;
  3533. int hdisplay, htotal, pixel_size, clock;
  3534. int line_count, line_size;
  3535. int small, large;
  3536. int entries;
  3537. if (!latency_ns) {
  3538. *fbc_wm = *display_wm = *cursor_wm = 0;
  3539. return false;
  3540. }
  3541. crtc = intel_get_crtc_for_plane(dev, plane);
  3542. hdisplay = crtc->mode.hdisplay;
  3543. htotal = crtc->mode.htotal;
  3544. clock = crtc->mode.clock;
  3545. pixel_size = crtc->fb->bits_per_pixel / 8;
  3546. line_time_us = (htotal * 1000) / clock;
  3547. line_count = (latency_ns / line_time_us + 1000) / 1000;
  3548. line_size = hdisplay * pixel_size;
  3549. /* Use the minimum of the small and large buffer method for primary */
  3550. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  3551. large = line_count * line_size;
  3552. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  3553. *display_wm = entries + display->guard_size;
  3554. /*
  3555. * Spec says:
  3556. * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
  3557. */
  3558. *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
  3559. /* calculate the self-refresh watermark for display cursor */
  3560. entries = line_count * pixel_size * 64;
  3561. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  3562. *cursor_wm = entries + cursor->guard_size;
  3563. return ironlake_check_srwm(dev, level,
  3564. *fbc_wm, *display_wm, *cursor_wm,
  3565. display, cursor);
  3566. }
  3567. static void ironlake_update_wm(struct drm_device *dev)
  3568. {
  3569. struct drm_i915_private *dev_priv = dev->dev_private;
  3570. int fbc_wm, plane_wm, cursor_wm;
  3571. unsigned int enabled;
  3572. enabled = 0;
  3573. if (g4x_compute_wm0(dev, 0,
  3574. &ironlake_display_wm_info,
  3575. ILK_LP0_PLANE_LATENCY,
  3576. &ironlake_cursor_wm_info,
  3577. ILK_LP0_CURSOR_LATENCY,
  3578. &plane_wm, &cursor_wm)) {
  3579. I915_WRITE(WM0_PIPEA_ILK,
  3580. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  3581. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  3582. " plane %d, " "cursor: %d\n",
  3583. plane_wm, cursor_wm);
  3584. enabled |= 1;
  3585. }
  3586. if (g4x_compute_wm0(dev, 1,
  3587. &ironlake_display_wm_info,
  3588. ILK_LP0_PLANE_LATENCY,
  3589. &ironlake_cursor_wm_info,
  3590. ILK_LP0_CURSOR_LATENCY,
  3591. &plane_wm, &cursor_wm)) {
  3592. I915_WRITE(WM0_PIPEB_ILK,
  3593. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  3594. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  3595. " plane %d, cursor: %d\n",
  3596. plane_wm, cursor_wm);
  3597. enabled |= 2;
  3598. }
  3599. /*
  3600. * Calculate and update the self-refresh watermark only when one
  3601. * display plane is used.
  3602. */
  3603. I915_WRITE(WM3_LP_ILK, 0);
  3604. I915_WRITE(WM2_LP_ILK, 0);
  3605. I915_WRITE(WM1_LP_ILK, 0);
  3606. if (!single_plane_enabled(enabled))
  3607. return;
  3608. enabled = ffs(enabled) - 1;
  3609. /* WM1 */
  3610. if (!ironlake_compute_srwm(dev, 1, enabled,
  3611. ILK_READ_WM1_LATENCY() * 500,
  3612. &ironlake_display_srwm_info,
  3613. &ironlake_cursor_srwm_info,
  3614. &fbc_wm, &plane_wm, &cursor_wm))
  3615. return;
  3616. I915_WRITE(WM1_LP_ILK,
  3617. WM1_LP_SR_EN |
  3618. (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3619. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3620. (plane_wm << WM1_LP_SR_SHIFT) |
  3621. cursor_wm);
  3622. /* WM2 */
  3623. if (!ironlake_compute_srwm(dev, 2, enabled,
  3624. ILK_READ_WM2_LATENCY() * 500,
  3625. &ironlake_display_srwm_info,
  3626. &ironlake_cursor_srwm_info,
  3627. &fbc_wm, &plane_wm, &cursor_wm))
  3628. return;
  3629. I915_WRITE(WM2_LP_ILK,
  3630. WM2_LP_EN |
  3631. (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3632. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3633. (plane_wm << WM1_LP_SR_SHIFT) |
  3634. cursor_wm);
  3635. /*
  3636. * WM3 is unsupported on ILK, probably because we don't have latency
  3637. * data for that power state
  3638. */
  3639. }
  3640. static void sandybridge_update_wm(struct drm_device *dev)
  3641. {
  3642. struct drm_i915_private *dev_priv = dev->dev_private;
  3643. int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
  3644. int fbc_wm, plane_wm, cursor_wm;
  3645. unsigned int enabled;
  3646. enabled = 0;
  3647. if (g4x_compute_wm0(dev, 0,
  3648. &sandybridge_display_wm_info, latency,
  3649. &sandybridge_cursor_wm_info, latency,
  3650. &plane_wm, &cursor_wm)) {
  3651. I915_WRITE(WM0_PIPEA_ILK,
  3652. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  3653. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  3654. " plane %d, " "cursor: %d\n",
  3655. plane_wm, cursor_wm);
  3656. enabled |= 1;
  3657. }
  3658. if (g4x_compute_wm0(dev, 1,
  3659. &sandybridge_display_wm_info, latency,
  3660. &sandybridge_cursor_wm_info, latency,
  3661. &plane_wm, &cursor_wm)) {
  3662. I915_WRITE(WM0_PIPEB_ILK,
  3663. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  3664. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  3665. " plane %d, cursor: %d\n",
  3666. plane_wm, cursor_wm);
  3667. enabled |= 2;
  3668. }
  3669. /*
  3670. * Calculate and update the self-refresh watermark only when one
  3671. * display plane is used.
  3672. *
  3673. * SNB support 3 levels of watermark.
  3674. *
  3675. * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
  3676. * and disabled in the descending order
  3677. *
  3678. */
  3679. I915_WRITE(WM3_LP_ILK, 0);
  3680. I915_WRITE(WM2_LP_ILK, 0);
  3681. I915_WRITE(WM1_LP_ILK, 0);
  3682. if (!single_plane_enabled(enabled))
  3683. return;
  3684. enabled = ffs(enabled) - 1;
  3685. /* WM1 */
  3686. if (!ironlake_compute_srwm(dev, 1, enabled,
  3687. SNB_READ_WM1_LATENCY() * 500,
  3688. &sandybridge_display_srwm_info,
  3689. &sandybridge_cursor_srwm_info,
  3690. &fbc_wm, &plane_wm, &cursor_wm))
  3691. return;
  3692. I915_WRITE(WM1_LP_ILK,
  3693. WM1_LP_SR_EN |
  3694. (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3695. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3696. (plane_wm << WM1_LP_SR_SHIFT) |
  3697. cursor_wm);
  3698. /* WM2 */
  3699. if (!ironlake_compute_srwm(dev, 2, enabled,
  3700. SNB_READ_WM2_LATENCY() * 500,
  3701. &sandybridge_display_srwm_info,
  3702. &sandybridge_cursor_srwm_info,
  3703. &fbc_wm, &plane_wm, &cursor_wm))
  3704. return;
  3705. I915_WRITE(WM2_LP_ILK,
  3706. WM2_LP_EN |
  3707. (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3708. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3709. (plane_wm << WM1_LP_SR_SHIFT) |
  3710. cursor_wm);
  3711. /* WM3 */
  3712. if (!ironlake_compute_srwm(dev, 3, enabled,
  3713. SNB_READ_WM3_LATENCY() * 500,
  3714. &sandybridge_display_srwm_info,
  3715. &sandybridge_cursor_srwm_info,
  3716. &fbc_wm, &plane_wm, &cursor_wm))
  3717. return;
  3718. I915_WRITE(WM3_LP_ILK,
  3719. WM3_LP_EN |
  3720. (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3721. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3722. (plane_wm << WM1_LP_SR_SHIFT) |
  3723. cursor_wm);
  3724. }
  3725. /**
  3726. * intel_update_watermarks - update FIFO watermark values based on current modes
  3727. *
  3728. * Calculate watermark values for the various WM regs based on current mode
  3729. * and plane configuration.
  3730. *
  3731. * There are several cases to deal with here:
  3732. * - normal (i.e. non-self-refresh)
  3733. * - self-refresh (SR) mode
  3734. * - lines are large relative to FIFO size (buffer can hold up to 2)
  3735. * - lines are small relative to FIFO size (buffer can hold more than 2
  3736. * lines), so need to account for TLB latency
  3737. *
  3738. * The normal calculation is:
  3739. * watermark = dotclock * bytes per pixel * latency
  3740. * where latency is platform & configuration dependent (we assume pessimal
  3741. * values here).
  3742. *
  3743. * The SR calculation is:
  3744. * watermark = (trunc(latency/line time)+1) * surface width *
  3745. * bytes per pixel
  3746. * where
  3747. * line time = htotal / dotclock
  3748. * surface width = hdisplay for normal plane and 64 for cursor
  3749. * and latency is assumed to be high, as above.
  3750. *
  3751. * The final value programmed to the register should always be rounded up,
  3752. * and include an extra 2 entries to account for clock crossings.
  3753. *
  3754. * We don't use the sprite, so we can ignore that. And on Crestline we have
  3755. * to set the non-SR watermarks to 8.
  3756. */
  3757. static void intel_update_watermarks(struct drm_device *dev)
  3758. {
  3759. struct drm_i915_private *dev_priv = dev->dev_private;
  3760. if (dev_priv->display.update_wm)
  3761. dev_priv->display.update_wm(dev);
  3762. }
  3763. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  3764. {
  3765. return dev_priv->lvds_use_ssc && i915_panel_use_ssc
  3766. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  3767. }
  3768. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  3769. struct drm_display_mode *mode,
  3770. struct drm_display_mode *adjusted_mode,
  3771. int x, int y,
  3772. struct drm_framebuffer *old_fb)
  3773. {
  3774. struct drm_device *dev = crtc->dev;
  3775. struct drm_i915_private *dev_priv = dev->dev_private;
  3776. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3777. int pipe = intel_crtc->pipe;
  3778. int plane = intel_crtc->plane;
  3779. int refclk, num_connectors = 0;
  3780. intel_clock_t clock, reduced_clock;
  3781. u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
  3782. bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
  3783. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  3784. struct drm_mode_config *mode_config = &dev->mode_config;
  3785. struct intel_encoder *encoder;
  3786. const intel_limit_t *limit;
  3787. int ret;
  3788. u32 temp;
  3789. u32 lvds_sync = 0;
  3790. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  3791. if (encoder->base.crtc != crtc)
  3792. continue;
  3793. switch (encoder->type) {
  3794. case INTEL_OUTPUT_LVDS:
  3795. is_lvds = true;
  3796. break;
  3797. case INTEL_OUTPUT_SDVO:
  3798. case INTEL_OUTPUT_HDMI:
  3799. is_sdvo = true;
  3800. if (encoder->needs_tv_clock)
  3801. is_tv = true;
  3802. break;
  3803. case INTEL_OUTPUT_DVO:
  3804. is_dvo = true;
  3805. break;
  3806. case INTEL_OUTPUT_TVOUT:
  3807. is_tv = true;
  3808. break;
  3809. case INTEL_OUTPUT_ANALOG:
  3810. is_crt = true;
  3811. break;
  3812. case INTEL_OUTPUT_DISPLAYPORT:
  3813. is_dp = true;
  3814. break;
  3815. }
  3816. num_connectors++;
  3817. }
  3818. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  3819. refclk = dev_priv->lvds_ssc_freq * 1000;
  3820. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3821. refclk / 1000);
  3822. } else if (!IS_GEN2(dev)) {
  3823. refclk = 96000;
  3824. } else {
  3825. refclk = 48000;
  3826. }
  3827. /*
  3828. * Returns a set of divisors for the desired target clock with the given
  3829. * refclk, or FALSE. The returned values represent the clock equation:
  3830. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  3831. */
  3832. limit = intel_limit(crtc, refclk);
  3833. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  3834. if (!ok) {
  3835. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  3836. return -EINVAL;
  3837. }
  3838. /* Ensure that the cursor is valid for the new mode before changing... */
  3839. intel_crtc_update_cursor(crtc, true);
  3840. if (is_lvds && dev_priv->lvds_downclock_avail) {
  3841. has_reduced_clock = limit->find_pll(limit, crtc,
  3842. dev_priv->lvds_downclock,
  3843. refclk,
  3844. &reduced_clock);
  3845. if (has_reduced_clock && (clock.p != reduced_clock.p)) {
  3846. /*
  3847. * If the different P is found, it means that we can't
  3848. * switch the display clock by using the FP0/FP1.
  3849. * In such case we will disable the LVDS downclock
  3850. * feature.
  3851. */
  3852. DRM_DEBUG_KMS("Different P is found for "
  3853. "LVDS clock/downclock\n");
  3854. has_reduced_clock = 0;
  3855. }
  3856. }
  3857. /* SDVO TV has fixed PLL values depend on its clock range,
  3858. this mirrors vbios setting. */
  3859. if (is_sdvo && is_tv) {
  3860. if (adjusted_mode->clock >= 100000
  3861. && adjusted_mode->clock < 140500) {
  3862. clock.p1 = 2;
  3863. clock.p2 = 10;
  3864. clock.n = 3;
  3865. clock.m1 = 16;
  3866. clock.m2 = 8;
  3867. } else if (adjusted_mode->clock >= 140500
  3868. && adjusted_mode->clock <= 200000) {
  3869. clock.p1 = 1;
  3870. clock.p2 = 10;
  3871. clock.n = 6;
  3872. clock.m1 = 12;
  3873. clock.m2 = 8;
  3874. }
  3875. }
  3876. if (IS_PINEVIEW(dev)) {
  3877. fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
  3878. if (has_reduced_clock)
  3879. fp2 = (1 << reduced_clock.n) << 16 |
  3880. reduced_clock.m1 << 8 | reduced_clock.m2;
  3881. } else {
  3882. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  3883. if (has_reduced_clock)
  3884. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  3885. reduced_clock.m2;
  3886. }
  3887. dpll = DPLL_VGA_MODE_DIS;
  3888. if (!IS_GEN2(dev)) {
  3889. if (is_lvds)
  3890. dpll |= DPLLB_MODE_LVDS;
  3891. else
  3892. dpll |= DPLLB_MODE_DAC_SERIAL;
  3893. if (is_sdvo) {
  3894. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  3895. if (pixel_multiplier > 1) {
  3896. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  3897. dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  3898. }
  3899. dpll |= DPLL_DVO_HIGH_SPEED;
  3900. }
  3901. if (is_dp)
  3902. dpll |= DPLL_DVO_HIGH_SPEED;
  3903. /* compute bitmask from p1 value */
  3904. if (IS_PINEVIEW(dev))
  3905. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3906. else {
  3907. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3908. if (IS_G4X(dev) && has_reduced_clock)
  3909. dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3910. }
  3911. switch (clock.p2) {
  3912. case 5:
  3913. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3914. break;
  3915. case 7:
  3916. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3917. break;
  3918. case 10:
  3919. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3920. break;
  3921. case 14:
  3922. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3923. break;
  3924. }
  3925. if (INTEL_INFO(dev)->gen >= 4)
  3926. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3927. } else {
  3928. if (is_lvds) {
  3929. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3930. } else {
  3931. if (clock.p1 == 2)
  3932. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3933. else
  3934. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3935. if (clock.p2 == 4)
  3936. dpll |= PLL_P2_DIVIDE_BY_4;
  3937. }
  3938. }
  3939. if (is_sdvo && is_tv)
  3940. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3941. else if (is_tv)
  3942. /* XXX: just matching BIOS for now */
  3943. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3944. dpll |= 3;
  3945. else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3946. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3947. else
  3948. dpll |= PLL_REF_INPUT_DREFCLK;
  3949. /* setup pipeconf */
  3950. pipeconf = I915_READ(PIPECONF(pipe));
  3951. /* Set up the display plane register */
  3952. dspcntr = DISPPLANE_GAMMA_ENABLE;
  3953. /* Ironlake's plane is forced to pipe, bit 24 is to
  3954. enable color space conversion */
  3955. if (pipe == 0)
  3956. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  3957. else
  3958. dspcntr |= DISPPLANE_SEL_PIPE_B;
  3959. if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
  3960. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  3961. * core speed.
  3962. *
  3963. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  3964. * pipe == 0 check?
  3965. */
  3966. if (mode->clock >
  3967. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  3968. pipeconf |= PIPECONF_DOUBLE_WIDE;
  3969. else
  3970. pipeconf &= ~PIPECONF_DOUBLE_WIDE;
  3971. }
  3972. dpll |= DPLL_VCO_ENABLE;
  3973. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  3974. drm_mode_debug_printmodeline(mode);
  3975. I915_WRITE(FP0(pipe), fp);
  3976. I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  3977. POSTING_READ(DPLL(pipe));
  3978. udelay(150);
  3979. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  3980. * This is an exception to the general rule that mode_set doesn't turn
  3981. * things on.
  3982. */
  3983. if (is_lvds) {
  3984. temp = I915_READ(LVDS);
  3985. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  3986. if (pipe == 1) {
  3987. temp |= LVDS_PIPEB_SELECT;
  3988. } else {
  3989. temp &= ~LVDS_PIPEB_SELECT;
  3990. }
  3991. /* set the corresponsding LVDS_BORDER bit */
  3992. temp |= dev_priv->lvds_border_bits;
  3993. /* Set the B0-B3 data pairs corresponding to whether we're going to
  3994. * set the DPLLs for dual-channel mode or not.
  3995. */
  3996. if (clock.p2 == 7)
  3997. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  3998. else
  3999. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  4000. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  4001. * appropriately here, but we need to look more thoroughly into how
  4002. * panels behave in the two modes.
  4003. */
  4004. /* set the dithering flag on LVDS as needed */
  4005. if (INTEL_INFO(dev)->gen >= 4) {
  4006. if (dev_priv->lvds_dither)
  4007. temp |= LVDS_ENABLE_DITHER;
  4008. else
  4009. temp &= ~LVDS_ENABLE_DITHER;
  4010. }
  4011. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  4012. lvds_sync |= LVDS_HSYNC_POLARITY;
  4013. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  4014. lvds_sync |= LVDS_VSYNC_POLARITY;
  4015. if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
  4016. != lvds_sync) {
  4017. char flags[2] = "-+";
  4018. DRM_INFO("Changing LVDS panel from "
  4019. "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
  4020. flags[!(temp & LVDS_HSYNC_POLARITY)],
  4021. flags[!(temp & LVDS_VSYNC_POLARITY)],
  4022. flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
  4023. flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
  4024. temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
  4025. temp |= lvds_sync;
  4026. }
  4027. I915_WRITE(LVDS, temp);
  4028. }
  4029. if (is_dp) {
  4030. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  4031. }
  4032. I915_WRITE(DPLL(pipe), dpll);
  4033. /* Wait for the clocks to stabilize. */
  4034. POSTING_READ(DPLL(pipe));
  4035. udelay(150);
  4036. if (INTEL_INFO(dev)->gen >= 4) {
  4037. temp = 0;
  4038. if (is_sdvo) {
  4039. temp = intel_mode_get_pixel_multiplier(adjusted_mode);
  4040. if (temp > 1)
  4041. temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  4042. else
  4043. temp = 0;
  4044. }
  4045. I915_WRITE(DPLL_MD(pipe), temp);
  4046. } else {
  4047. /* The pixel multiplier can only be updated once the
  4048. * DPLL is enabled and the clocks are stable.
  4049. *
  4050. * So write it again.
  4051. */
  4052. I915_WRITE(DPLL(pipe), dpll);
  4053. }
  4054. intel_crtc->lowfreq_avail = false;
  4055. if (is_lvds && has_reduced_clock && i915_powersave) {
  4056. I915_WRITE(FP1(pipe), fp2);
  4057. intel_crtc->lowfreq_avail = true;
  4058. if (HAS_PIPE_CXSR(dev)) {
  4059. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4060. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4061. }
  4062. } else {
  4063. I915_WRITE(FP1(pipe), fp);
  4064. if (HAS_PIPE_CXSR(dev)) {
  4065. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4066. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  4067. }
  4068. }
  4069. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  4070. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4071. /* the chip adds 2 halflines automatically */
  4072. adjusted_mode->crtc_vdisplay -= 1;
  4073. adjusted_mode->crtc_vtotal -= 1;
  4074. adjusted_mode->crtc_vblank_start -= 1;
  4075. adjusted_mode->crtc_vblank_end -= 1;
  4076. adjusted_mode->crtc_vsync_end -= 1;
  4077. adjusted_mode->crtc_vsync_start -= 1;
  4078. } else
  4079. pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
  4080. I915_WRITE(HTOTAL(pipe),
  4081. (adjusted_mode->crtc_hdisplay - 1) |
  4082. ((adjusted_mode->crtc_htotal - 1) << 16));
  4083. I915_WRITE(HBLANK(pipe),
  4084. (adjusted_mode->crtc_hblank_start - 1) |
  4085. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  4086. I915_WRITE(HSYNC(pipe),
  4087. (adjusted_mode->crtc_hsync_start - 1) |
  4088. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  4089. I915_WRITE(VTOTAL(pipe),
  4090. (adjusted_mode->crtc_vdisplay - 1) |
  4091. ((adjusted_mode->crtc_vtotal - 1) << 16));
  4092. I915_WRITE(VBLANK(pipe),
  4093. (adjusted_mode->crtc_vblank_start - 1) |
  4094. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  4095. I915_WRITE(VSYNC(pipe),
  4096. (adjusted_mode->crtc_vsync_start - 1) |
  4097. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  4098. /* pipesrc and dspsize control the size that is scaled from,
  4099. * which should always be the user's requested size.
  4100. */
  4101. I915_WRITE(DSPSIZE(plane),
  4102. ((mode->vdisplay - 1) << 16) |
  4103. (mode->hdisplay - 1));
  4104. I915_WRITE(DSPPOS(plane), 0);
  4105. I915_WRITE(PIPESRC(pipe),
  4106. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  4107. I915_WRITE(PIPECONF(pipe), pipeconf);
  4108. POSTING_READ(PIPECONF(pipe));
  4109. intel_enable_pipe(dev_priv, pipe, false);
  4110. intel_wait_for_vblank(dev, pipe);
  4111. I915_WRITE(DSPCNTR(plane), dspcntr);
  4112. POSTING_READ(DSPCNTR(plane));
  4113. intel_enable_plane(dev_priv, plane, pipe);
  4114. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  4115. intel_update_watermarks(dev);
  4116. return ret;
  4117. }
  4118. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  4119. struct drm_display_mode *mode,
  4120. struct drm_display_mode *adjusted_mode,
  4121. int x, int y,
  4122. struct drm_framebuffer *old_fb)
  4123. {
  4124. struct drm_device *dev = crtc->dev;
  4125. struct drm_i915_private *dev_priv = dev->dev_private;
  4126. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4127. int pipe = intel_crtc->pipe;
  4128. int plane = intel_crtc->plane;
  4129. int refclk, num_connectors = 0;
  4130. intel_clock_t clock, reduced_clock;
  4131. u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
  4132. bool ok, has_reduced_clock = false, is_sdvo = false;
  4133. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  4134. struct intel_encoder *has_edp_encoder = NULL;
  4135. struct drm_mode_config *mode_config = &dev->mode_config;
  4136. struct intel_encoder *encoder;
  4137. const intel_limit_t *limit;
  4138. int ret;
  4139. struct fdi_m_n m_n = {0};
  4140. u32 temp;
  4141. u32 lvds_sync = 0;
  4142. int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
  4143. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  4144. if (encoder->base.crtc != crtc)
  4145. continue;
  4146. switch (encoder->type) {
  4147. case INTEL_OUTPUT_LVDS:
  4148. is_lvds = true;
  4149. break;
  4150. case INTEL_OUTPUT_SDVO:
  4151. case INTEL_OUTPUT_HDMI:
  4152. is_sdvo = true;
  4153. if (encoder->needs_tv_clock)
  4154. is_tv = true;
  4155. break;
  4156. case INTEL_OUTPUT_TVOUT:
  4157. is_tv = true;
  4158. break;
  4159. case INTEL_OUTPUT_ANALOG:
  4160. is_crt = true;
  4161. break;
  4162. case INTEL_OUTPUT_DISPLAYPORT:
  4163. is_dp = true;
  4164. break;
  4165. case INTEL_OUTPUT_EDP:
  4166. has_edp_encoder = encoder;
  4167. break;
  4168. }
  4169. num_connectors++;
  4170. }
  4171. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4172. refclk = dev_priv->lvds_ssc_freq * 1000;
  4173. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4174. refclk / 1000);
  4175. } else {
  4176. refclk = 96000;
  4177. if (!has_edp_encoder ||
  4178. intel_encoder_is_pch_edp(&has_edp_encoder->base))
  4179. refclk = 120000; /* 120Mhz refclk */
  4180. }
  4181. /*
  4182. * Returns a set of divisors for the desired target clock with the given
  4183. * refclk, or FALSE. The returned values represent the clock equation:
  4184. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4185. */
  4186. limit = intel_limit(crtc, refclk);
  4187. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  4188. if (!ok) {
  4189. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4190. return -EINVAL;
  4191. }
  4192. /* Ensure that the cursor is valid for the new mode before changing... */
  4193. intel_crtc_update_cursor(crtc, true);
  4194. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4195. has_reduced_clock = limit->find_pll(limit, crtc,
  4196. dev_priv->lvds_downclock,
  4197. refclk,
  4198. &reduced_clock);
  4199. if (has_reduced_clock && (clock.p != reduced_clock.p)) {
  4200. /*
  4201. * If the different P is found, it means that we can't
  4202. * switch the display clock by using the FP0/FP1.
  4203. * In such case we will disable the LVDS downclock
  4204. * feature.
  4205. */
  4206. DRM_DEBUG_KMS("Different P is found for "
  4207. "LVDS clock/downclock\n");
  4208. has_reduced_clock = 0;
  4209. }
  4210. }
  4211. /* SDVO TV has fixed PLL values depend on its clock range,
  4212. this mirrors vbios setting. */
  4213. if (is_sdvo && is_tv) {
  4214. if (adjusted_mode->clock >= 100000
  4215. && adjusted_mode->clock < 140500) {
  4216. clock.p1 = 2;
  4217. clock.p2 = 10;
  4218. clock.n = 3;
  4219. clock.m1 = 16;
  4220. clock.m2 = 8;
  4221. } else if (adjusted_mode->clock >= 140500
  4222. && adjusted_mode->clock <= 200000) {
  4223. clock.p1 = 1;
  4224. clock.p2 = 10;
  4225. clock.n = 6;
  4226. clock.m1 = 12;
  4227. clock.m2 = 8;
  4228. }
  4229. }
  4230. /* FDI link */
  4231. pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4232. lane = 0;
  4233. /* CPU eDP doesn't require FDI link, so just set DP M/N
  4234. according to current link config */
  4235. if (has_edp_encoder &&
  4236. !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4237. target_clock = mode->clock;
  4238. intel_edp_link_config(has_edp_encoder,
  4239. &lane, &link_bw);
  4240. } else {
  4241. /* [e]DP over FDI requires target mode clock
  4242. instead of link clock */
  4243. if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
  4244. target_clock = mode->clock;
  4245. else
  4246. target_clock = adjusted_mode->clock;
  4247. /* FDI is a binary signal running at ~2.7GHz, encoding
  4248. * each output octet as 10 bits. The actual frequency
  4249. * is stored as a divider into a 100MHz clock, and the
  4250. * mode pixel clock is stored in units of 1KHz.
  4251. * Hence the bw of each lane in terms of the mode signal
  4252. * is:
  4253. */
  4254. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  4255. }
  4256. /* determine panel color depth */
  4257. temp = I915_READ(PIPECONF(pipe));
  4258. temp &= ~PIPE_BPC_MASK;
  4259. if (is_lvds) {
  4260. /* the BPC will be 6 if it is 18-bit LVDS panel */
  4261. if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
  4262. temp |= PIPE_8BPC;
  4263. else
  4264. temp |= PIPE_6BPC;
  4265. } else if (has_edp_encoder) {
  4266. switch (dev_priv->edp.bpp/3) {
  4267. case 8:
  4268. temp |= PIPE_8BPC;
  4269. break;
  4270. case 10:
  4271. temp |= PIPE_10BPC;
  4272. break;
  4273. case 6:
  4274. temp |= PIPE_6BPC;
  4275. break;
  4276. case 12:
  4277. temp |= PIPE_12BPC;
  4278. break;
  4279. }
  4280. } else
  4281. temp |= PIPE_8BPC;
  4282. I915_WRITE(PIPECONF(pipe), temp);
  4283. switch (temp & PIPE_BPC_MASK) {
  4284. case PIPE_8BPC:
  4285. bpp = 24;
  4286. break;
  4287. case PIPE_10BPC:
  4288. bpp = 30;
  4289. break;
  4290. case PIPE_6BPC:
  4291. bpp = 18;
  4292. break;
  4293. case PIPE_12BPC:
  4294. bpp = 36;
  4295. break;
  4296. default:
  4297. DRM_ERROR("unknown pipe bpc value\n");
  4298. bpp = 24;
  4299. }
  4300. if (!lane) {
  4301. /*
  4302. * Account for spread spectrum to avoid
  4303. * oversubscribing the link. Max center spread
  4304. * is 2.5%; use 5% for safety's sake.
  4305. */
  4306. u32 bps = target_clock * bpp * 21 / 20;
  4307. lane = bps / (link_bw * 8) + 1;
  4308. }
  4309. intel_crtc->fdi_lanes = lane;
  4310. if (pixel_multiplier > 1)
  4311. link_bw *= pixel_multiplier;
  4312. ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
  4313. /* Ironlake: try to setup display ref clock before DPLL
  4314. * enabling. This is only under driver's control after
  4315. * PCH B stepping, previous chipset stepping should be
  4316. * ignoring this setting.
  4317. */
  4318. temp = I915_READ(PCH_DREF_CONTROL);
  4319. /* Always enable nonspread source */
  4320. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  4321. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  4322. temp &= ~DREF_SSC_SOURCE_MASK;
  4323. temp |= DREF_SSC_SOURCE_ENABLE;
  4324. I915_WRITE(PCH_DREF_CONTROL, temp);
  4325. POSTING_READ(PCH_DREF_CONTROL);
  4326. udelay(200);
  4327. if (has_edp_encoder) {
  4328. if (intel_panel_use_ssc(dev_priv)) {
  4329. temp |= DREF_SSC1_ENABLE;
  4330. I915_WRITE(PCH_DREF_CONTROL, temp);
  4331. POSTING_READ(PCH_DREF_CONTROL);
  4332. udelay(200);
  4333. }
  4334. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4335. /* Enable CPU source on CPU attached eDP */
  4336. if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4337. if (intel_panel_use_ssc(dev_priv))
  4338. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4339. else
  4340. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4341. } else {
  4342. /* Enable SSC on PCH eDP if needed */
  4343. if (intel_panel_use_ssc(dev_priv)) {
  4344. DRM_ERROR("enabling SSC on PCH\n");
  4345. temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
  4346. }
  4347. }
  4348. I915_WRITE(PCH_DREF_CONTROL, temp);
  4349. POSTING_READ(PCH_DREF_CONTROL);
  4350. udelay(200);
  4351. }
  4352. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  4353. if (has_reduced_clock)
  4354. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  4355. reduced_clock.m2;
  4356. /* Enable autotuning of the PLL clock (if permissible) */
  4357. factor = 21;
  4358. if (is_lvds) {
  4359. if ((intel_panel_use_ssc(dev_priv) &&
  4360. dev_priv->lvds_ssc_freq == 100) ||
  4361. (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
  4362. factor = 25;
  4363. } else if (is_sdvo && is_tv)
  4364. factor = 20;
  4365. if (clock.m < factor * clock.n)
  4366. fp |= FP_CB_TUNE;
  4367. dpll = 0;
  4368. if (is_lvds)
  4369. dpll |= DPLLB_MODE_LVDS;
  4370. else
  4371. dpll |= DPLLB_MODE_DAC_SERIAL;
  4372. if (is_sdvo) {
  4373. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4374. if (pixel_multiplier > 1) {
  4375. dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  4376. }
  4377. dpll |= DPLL_DVO_HIGH_SPEED;
  4378. }
  4379. if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
  4380. dpll |= DPLL_DVO_HIGH_SPEED;
  4381. /* compute bitmask from p1 value */
  4382. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4383. /* also FPA1 */
  4384. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4385. switch (clock.p2) {
  4386. case 5:
  4387. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4388. break;
  4389. case 7:
  4390. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4391. break;
  4392. case 10:
  4393. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4394. break;
  4395. case 14:
  4396. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4397. break;
  4398. }
  4399. if (is_sdvo && is_tv)
  4400. dpll |= PLL_REF_INPUT_TVCLKINBC;
  4401. else if (is_tv)
  4402. /* XXX: just matching BIOS for now */
  4403. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  4404. dpll |= 3;
  4405. else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4406. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4407. else
  4408. dpll |= PLL_REF_INPUT_DREFCLK;
  4409. /* setup pipeconf */
  4410. pipeconf = I915_READ(PIPECONF(pipe));
  4411. /* Set up the display plane register */
  4412. dspcntr = DISPPLANE_GAMMA_ENABLE;
  4413. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  4414. drm_mode_debug_printmodeline(mode);
  4415. /* PCH eDP needs FDI, but CPU eDP does not */
  4416. if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4417. I915_WRITE(PCH_FP0(pipe), fp);
  4418. I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  4419. POSTING_READ(PCH_DPLL(pipe));
  4420. udelay(150);
  4421. }
  4422. /* enable transcoder DPLL */
  4423. if (HAS_PCH_CPT(dev)) {
  4424. temp = I915_READ(PCH_DPLL_SEL);
  4425. switch (pipe) {
  4426. case 0:
  4427. temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
  4428. break;
  4429. case 1:
  4430. temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
  4431. break;
  4432. case 2:
  4433. /* FIXME: manage transcoder PLLs? */
  4434. temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
  4435. break;
  4436. default:
  4437. BUG();
  4438. }
  4439. I915_WRITE(PCH_DPLL_SEL, temp);
  4440. POSTING_READ(PCH_DPLL_SEL);
  4441. udelay(150);
  4442. }
  4443. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  4444. * This is an exception to the general rule that mode_set doesn't turn
  4445. * things on.
  4446. */
  4447. if (is_lvds) {
  4448. temp = I915_READ(PCH_LVDS);
  4449. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  4450. if (pipe == 1) {
  4451. if (HAS_PCH_CPT(dev))
  4452. temp |= PORT_TRANS_B_SEL_CPT;
  4453. else
  4454. temp |= LVDS_PIPEB_SELECT;
  4455. } else {
  4456. if (HAS_PCH_CPT(dev))
  4457. temp &= ~PORT_TRANS_SEL_MASK;
  4458. else
  4459. temp &= ~LVDS_PIPEB_SELECT;
  4460. }
  4461. /* set the corresponsding LVDS_BORDER bit */
  4462. temp |= dev_priv->lvds_border_bits;
  4463. /* Set the B0-B3 data pairs corresponding to whether we're going to
  4464. * set the DPLLs for dual-channel mode or not.
  4465. */
  4466. if (clock.p2 == 7)
  4467. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  4468. else
  4469. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  4470. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  4471. * appropriately here, but we need to look more thoroughly into how
  4472. * panels behave in the two modes.
  4473. */
  4474. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  4475. lvds_sync |= LVDS_HSYNC_POLARITY;
  4476. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  4477. lvds_sync |= LVDS_VSYNC_POLARITY;
  4478. if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
  4479. != lvds_sync) {
  4480. char flags[2] = "-+";
  4481. DRM_INFO("Changing LVDS panel from "
  4482. "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
  4483. flags[!(temp & LVDS_HSYNC_POLARITY)],
  4484. flags[!(temp & LVDS_VSYNC_POLARITY)],
  4485. flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
  4486. flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
  4487. temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
  4488. temp |= lvds_sync;
  4489. }
  4490. I915_WRITE(PCH_LVDS, temp);
  4491. }
  4492. /* set the dithering flag and clear for anything other than a panel. */
  4493. pipeconf &= ~PIPECONF_DITHER_EN;
  4494. pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
  4495. if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
  4496. pipeconf |= PIPECONF_DITHER_EN;
  4497. pipeconf |= PIPECONF_DITHER_TYPE_ST1;
  4498. }
  4499. if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4500. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  4501. } else {
  4502. /* For non-DP output, clear any trans DP clock recovery setting.*/
  4503. I915_WRITE(TRANSDATA_M1(pipe), 0);
  4504. I915_WRITE(TRANSDATA_N1(pipe), 0);
  4505. I915_WRITE(TRANSDPLINK_M1(pipe), 0);
  4506. I915_WRITE(TRANSDPLINK_N1(pipe), 0);
  4507. }
  4508. if (!has_edp_encoder ||
  4509. intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4510. I915_WRITE(PCH_DPLL(pipe), dpll);
  4511. /* Wait for the clocks to stabilize. */
  4512. POSTING_READ(PCH_DPLL(pipe));
  4513. udelay(150);
  4514. /* The pixel multiplier can only be updated once the
  4515. * DPLL is enabled and the clocks are stable.
  4516. *
  4517. * So write it again.
  4518. */
  4519. I915_WRITE(PCH_DPLL(pipe), dpll);
  4520. }
  4521. intel_crtc->lowfreq_avail = false;
  4522. if (is_lvds && has_reduced_clock && i915_powersave) {
  4523. I915_WRITE(PCH_FP1(pipe), fp2);
  4524. intel_crtc->lowfreq_avail = true;
  4525. if (HAS_PIPE_CXSR(dev)) {
  4526. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4527. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4528. }
  4529. } else {
  4530. I915_WRITE(PCH_FP1(pipe), fp);
  4531. if (HAS_PIPE_CXSR(dev)) {
  4532. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4533. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  4534. }
  4535. }
  4536. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  4537. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4538. /* the chip adds 2 halflines automatically */
  4539. adjusted_mode->crtc_vdisplay -= 1;
  4540. adjusted_mode->crtc_vtotal -= 1;
  4541. adjusted_mode->crtc_vblank_start -= 1;
  4542. adjusted_mode->crtc_vblank_end -= 1;
  4543. adjusted_mode->crtc_vsync_end -= 1;
  4544. adjusted_mode->crtc_vsync_start -= 1;
  4545. } else
  4546. pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
  4547. I915_WRITE(HTOTAL(pipe),
  4548. (adjusted_mode->crtc_hdisplay - 1) |
  4549. ((adjusted_mode->crtc_htotal - 1) << 16));
  4550. I915_WRITE(HBLANK(pipe),
  4551. (adjusted_mode->crtc_hblank_start - 1) |
  4552. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  4553. I915_WRITE(HSYNC(pipe),
  4554. (adjusted_mode->crtc_hsync_start - 1) |
  4555. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  4556. I915_WRITE(VTOTAL(pipe),
  4557. (adjusted_mode->crtc_vdisplay - 1) |
  4558. ((adjusted_mode->crtc_vtotal - 1) << 16));
  4559. I915_WRITE(VBLANK(pipe),
  4560. (adjusted_mode->crtc_vblank_start - 1) |
  4561. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  4562. I915_WRITE(VSYNC(pipe),
  4563. (adjusted_mode->crtc_vsync_start - 1) |
  4564. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  4565. /* pipesrc controls the size that is scaled from, which should
  4566. * always be the user's requested size.
  4567. */
  4568. I915_WRITE(PIPESRC(pipe),
  4569. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  4570. I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
  4571. I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
  4572. I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
  4573. I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
  4574. if (has_edp_encoder &&
  4575. !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4576. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  4577. }
  4578. I915_WRITE(PIPECONF(pipe), pipeconf);
  4579. POSTING_READ(PIPECONF(pipe));
  4580. intel_wait_for_vblank(dev, pipe);
  4581. if (IS_GEN5(dev)) {
  4582. /* enable address swizzle for tiling buffer */
  4583. temp = I915_READ(DISP_ARB_CTL);
  4584. I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
  4585. }
  4586. I915_WRITE(DSPCNTR(plane), dspcntr);
  4587. POSTING_READ(DSPCNTR(plane));
  4588. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  4589. intel_update_watermarks(dev);
  4590. return ret;
  4591. }
  4592. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  4593. struct drm_display_mode *mode,
  4594. struct drm_display_mode *adjusted_mode,
  4595. int x, int y,
  4596. struct drm_framebuffer *old_fb)
  4597. {
  4598. struct drm_device *dev = crtc->dev;
  4599. struct drm_i915_private *dev_priv = dev->dev_private;
  4600. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4601. int pipe = intel_crtc->pipe;
  4602. int ret;
  4603. drm_vblank_pre_modeset(dev, pipe);
  4604. ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
  4605. x, y, old_fb);
  4606. drm_vblank_post_modeset(dev, pipe);
  4607. intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
  4608. return ret;
  4609. }
  4610. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  4611. void intel_crtc_load_lut(struct drm_crtc *crtc)
  4612. {
  4613. struct drm_device *dev = crtc->dev;
  4614. struct drm_i915_private *dev_priv = dev->dev_private;
  4615. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4616. int palreg = PALETTE(intel_crtc->pipe);
  4617. int i;
  4618. /* The clocks have to be on to load the palette. */
  4619. if (!crtc->enabled)
  4620. return;
  4621. /* use legacy palette for Ironlake */
  4622. if (HAS_PCH_SPLIT(dev))
  4623. palreg = LGC_PALETTE(intel_crtc->pipe);
  4624. for (i = 0; i < 256; i++) {
  4625. I915_WRITE(palreg + 4 * i,
  4626. (intel_crtc->lut_r[i] << 16) |
  4627. (intel_crtc->lut_g[i] << 8) |
  4628. intel_crtc->lut_b[i]);
  4629. }
  4630. }
  4631. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  4632. {
  4633. struct drm_device *dev = crtc->dev;
  4634. struct drm_i915_private *dev_priv = dev->dev_private;
  4635. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4636. bool visible = base != 0;
  4637. u32 cntl;
  4638. if (intel_crtc->cursor_visible == visible)
  4639. return;
  4640. cntl = I915_READ(_CURACNTR);
  4641. if (visible) {
  4642. /* On these chipsets we can only modify the base whilst
  4643. * the cursor is disabled.
  4644. */
  4645. I915_WRITE(_CURABASE, base);
  4646. cntl &= ~(CURSOR_FORMAT_MASK);
  4647. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  4648. cntl |= CURSOR_ENABLE |
  4649. CURSOR_GAMMA_ENABLE |
  4650. CURSOR_FORMAT_ARGB;
  4651. } else
  4652. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  4653. I915_WRITE(_CURACNTR, cntl);
  4654. intel_crtc->cursor_visible = visible;
  4655. }
  4656. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  4657. {
  4658. struct drm_device *dev = crtc->dev;
  4659. struct drm_i915_private *dev_priv = dev->dev_private;
  4660. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4661. int pipe = intel_crtc->pipe;
  4662. bool visible = base != 0;
  4663. if (intel_crtc->cursor_visible != visible) {
  4664. uint32_t cntl = I915_READ(CURCNTR(pipe));
  4665. if (base) {
  4666. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  4667. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  4668. cntl |= pipe << 28; /* Connect to correct pipe */
  4669. } else {
  4670. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  4671. cntl |= CURSOR_MODE_DISABLE;
  4672. }
  4673. I915_WRITE(CURCNTR(pipe), cntl);
  4674. intel_crtc->cursor_visible = visible;
  4675. }
  4676. /* and commit changes on next vblank */
  4677. I915_WRITE(CURBASE(pipe), base);
  4678. }
  4679. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  4680. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  4681. bool on)
  4682. {
  4683. struct drm_device *dev = crtc->dev;
  4684. struct drm_i915_private *dev_priv = dev->dev_private;
  4685. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4686. int pipe = intel_crtc->pipe;
  4687. int x = intel_crtc->cursor_x;
  4688. int y = intel_crtc->cursor_y;
  4689. u32 base, pos;
  4690. bool visible;
  4691. pos = 0;
  4692. if (on && crtc->enabled && crtc->fb) {
  4693. base = intel_crtc->cursor_addr;
  4694. if (x > (int) crtc->fb->width)
  4695. base = 0;
  4696. if (y > (int) crtc->fb->height)
  4697. base = 0;
  4698. } else
  4699. base = 0;
  4700. if (x < 0) {
  4701. if (x + intel_crtc->cursor_width < 0)
  4702. base = 0;
  4703. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  4704. x = -x;
  4705. }
  4706. pos |= x << CURSOR_X_SHIFT;
  4707. if (y < 0) {
  4708. if (y + intel_crtc->cursor_height < 0)
  4709. base = 0;
  4710. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  4711. y = -y;
  4712. }
  4713. pos |= y << CURSOR_Y_SHIFT;
  4714. visible = base != 0;
  4715. if (!visible && !intel_crtc->cursor_visible)
  4716. return;
  4717. I915_WRITE(CURPOS(pipe), pos);
  4718. if (IS_845G(dev) || IS_I865G(dev))
  4719. i845_update_cursor(crtc, base);
  4720. else
  4721. i9xx_update_cursor(crtc, base);
  4722. if (visible)
  4723. intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
  4724. }
  4725. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  4726. struct drm_file *file,
  4727. uint32_t handle,
  4728. uint32_t width, uint32_t height)
  4729. {
  4730. struct drm_device *dev = crtc->dev;
  4731. struct drm_i915_private *dev_priv = dev->dev_private;
  4732. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4733. struct drm_i915_gem_object *obj;
  4734. uint32_t addr;
  4735. int ret;
  4736. DRM_DEBUG_KMS("\n");
  4737. /* if we want to turn off the cursor ignore width and height */
  4738. if (!handle) {
  4739. DRM_DEBUG_KMS("cursor off\n");
  4740. addr = 0;
  4741. obj = NULL;
  4742. mutex_lock(&dev->struct_mutex);
  4743. goto finish;
  4744. }
  4745. /* Currently we only support 64x64 cursors */
  4746. if (width != 64 || height != 64) {
  4747. DRM_ERROR("we currently only support 64x64 cursors\n");
  4748. return -EINVAL;
  4749. }
  4750. obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  4751. if (&obj->base == NULL)
  4752. return -ENOENT;
  4753. if (obj->base.size < width * height * 4) {
  4754. DRM_ERROR("buffer is to small\n");
  4755. ret = -ENOMEM;
  4756. goto fail;
  4757. }
  4758. /* we only need to pin inside GTT if cursor is non-phy */
  4759. mutex_lock(&dev->struct_mutex);
  4760. if (!dev_priv->info->cursor_needs_physical) {
  4761. if (obj->tiling_mode) {
  4762. DRM_ERROR("cursor cannot be tiled\n");
  4763. ret = -EINVAL;
  4764. goto fail_locked;
  4765. }
  4766. ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
  4767. if (ret) {
  4768. DRM_ERROR("failed to pin cursor bo\n");
  4769. goto fail_locked;
  4770. }
  4771. ret = i915_gem_object_set_to_gtt_domain(obj, 0);
  4772. if (ret) {
  4773. DRM_ERROR("failed to move cursor bo into the GTT\n");
  4774. goto fail_unpin;
  4775. }
  4776. ret = i915_gem_object_put_fence(obj);
  4777. if (ret) {
  4778. DRM_ERROR("failed to move cursor bo into the GTT\n");
  4779. goto fail_unpin;
  4780. }
  4781. addr = obj->gtt_offset;
  4782. } else {
  4783. int align = IS_I830(dev) ? 16 * 1024 : 256;
  4784. ret = i915_gem_attach_phys_object(dev, obj,
  4785. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  4786. align);
  4787. if (ret) {
  4788. DRM_ERROR("failed to attach phys object\n");
  4789. goto fail_locked;
  4790. }
  4791. addr = obj->phys_obj->handle->busaddr;
  4792. }
  4793. if (IS_GEN2(dev))
  4794. I915_WRITE(CURSIZE, (height << 12) | width);
  4795. finish:
  4796. if (intel_crtc->cursor_bo) {
  4797. if (dev_priv->info->cursor_needs_physical) {
  4798. if (intel_crtc->cursor_bo != obj)
  4799. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  4800. } else
  4801. i915_gem_object_unpin(intel_crtc->cursor_bo);
  4802. drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  4803. }
  4804. mutex_unlock(&dev->struct_mutex);
  4805. intel_crtc->cursor_addr = addr;
  4806. intel_crtc->cursor_bo = obj;
  4807. intel_crtc->cursor_width = width;
  4808. intel_crtc->cursor_height = height;
  4809. intel_crtc_update_cursor(crtc, true);
  4810. return 0;
  4811. fail_unpin:
  4812. i915_gem_object_unpin(obj);
  4813. fail_locked:
  4814. mutex_unlock(&dev->struct_mutex);
  4815. fail:
  4816. drm_gem_object_unreference_unlocked(&obj->base);
  4817. return ret;
  4818. }
  4819. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  4820. {
  4821. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4822. intel_crtc->cursor_x = x;
  4823. intel_crtc->cursor_y = y;
  4824. intel_crtc_update_cursor(crtc, true);
  4825. return 0;
  4826. }
  4827. /** Sets the color ramps on behalf of RandR */
  4828. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  4829. u16 blue, int regno)
  4830. {
  4831. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4832. intel_crtc->lut_r[regno] = red >> 8;
  4833. intel_crtc->lut_g[regno] = green >> 8;
  4834. intel_crtc->lut_b[regno] = blue >> 8;
  4835. }
  4836. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  4837. u16 *blue, int regno)
  4838. {
  4839. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4840. *red = intel_crtc->lut_r[regno] << 8;
  4841. *green = intel_crtc->lut_g[regno] << 8;
  4842. *blue = intel_crtc->lut_b[regno] << 8;
  4843. }
  4844. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  4845. u16 *blue, uint32_t start, uint32_t size)
  4846. {
  4847. int end = (start + size > 256) ? 256 : start + size, i;
  4848. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4849. for (i = start; i < end; i++) {
  4850. intel_crtc->lut_r[i] = red[i] >> 8;
  4851. intel_crtc->lut_g[i] = green[i] >> 8;
  4852. intel_crtc->lut_b[i] = blue[i] >> 8;
  4853. }
  4854. intel_crtc_load_lut(crtc);
  4855. }
  4856. /**
  4857. * Get a pipe with a simple mode set on it for doing load-based monitor
  4858. * detection.
  4859. *
  4860. * It will be up to the load-detect code to adjust the pipe as appropriate for
  4861. * its requirements. The pipe will be connected to no other encoders.
  4862. *
  4863. * Currently this code will only succeed if there is a pipe with no encoders
  4864. * configured for it. In the future, it could choose to temporarily disable
  4865. * some outputs to free up a pipe for its use.
  4866. *
  4867. * \return crtc, or NULL if no pipes are available.
  4868. */
  4869. /* VESA 640x480x72Hz mode to set on the pipe */
  4870. static struct drm_display_mode load_detect_mode = {
  4871. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  4872. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  4873. };
  4874. static struct drm_framebuffer *
  4875. intel_framebuffer_create(struct drm_device *dev,
  4876. struct drm_mode_fb_cmd *mode_cmd,
  4877. struct drm_i915_gem_object *obj)
  4878. {
  4879. struct intel_framebuffer *intel_fb;
  4880. int ret;
  4881. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  4882. if (!intel_fb) {
  4883. drm_gem_object_unreference_unlocked(&obj->base);
  4884. return ERR_PTR(-ENOMEM);
  4885. }
  4886. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  4887. if (ret) {
  4888. drm_gem_object_unreference_unlocked(&obj->base);
  4889. kfree(intel_fb);
  4890. return ERR_PTR(ret);
  4891. }
  4892. return &intel_fb->base;
  4893. }
  4894. static u32
  4895. intel_framebuffer_pitch_for_width(int width, int bpp)
  4896. {
  4897. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  4898. return ALIGN(pitch, 64);
  4899. }
  4900. static u32
  4901. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  4902. {
  4903. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  4904. return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  4905. }
  4906. static struct drm_framebuffer *
  4907. intel_framebuffer_create_for_mode(struct drm_device *dev,
  4908. struct drm_display_mode *mode,
  4909. int depth, int bpp)
  4910. {
  4911. struct drm_i915_gem_object *obj;
  4912. struct drm_mode_fb_cmd mode_cmd;
  4913. obj = i915_gem_alloc_object(dev,
  4914. intel_framebuffer_size_for_mode(mode, bpp));
  4915. if (obj == NULL)
  4916. return ERR_PTR(-ENOMEM);
  4917. mode_cmd.width = mode->hdisplay;
  4918. mode_cmd.height = mode->vdisplay;
  4919. mode_cmd.depth = depth;
  4920. mode_cmd.bpp = bpp;
  4921. mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
  4922. return intel_framebuffer_create(dev, &mode_cmd, obj);
  4923. }
  4924. static struct drm_framebuffer *
  4925. mode_fits_in_fbdev(struct drm_device *dev,
  4926. struct drm_display_mode *mode)
  4927. {
  4928. struct drm_i915_private *dev_priv = dev->dev_private;
  4929. struct drm_i915_gem_object *obj;
  4930. struct drm_framebuffer *fb;
  4931. if (dev_priv->fbdev == NULL)
  4932. return NULL;
  4933. obj = dev_priv->fbdev->ifb.obj;
  4934. if (obj == NULL)
  4935. return NULL;
  4936. fb = &dev_priv->fbdev->ifb.base;
  4937. if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
  4938. fb->bits_per_pixel))
  4939. return NULL;
  4940. if (obj->base.size < mode->vdisplay * fb->pitch)
  4941. return NULL;
  4942. return fb;
  4943. }
  4944. bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
  4945. struct drm_connector *connector,
  4946. struct drm_display_mode *mode,
  4947. struct intel_load_detect_pipe *old)
  4948. {
  4949. struct intel_crtc *intel_crtc;
  4950. struct drm_crtc *possible_crtc;
  4951. struct drm_encoder *encoder = &intel_encoder->base;
  4952. struct drm_crtc *crtc = NULL;
  4953. struct drm_device *dev = encoder->dev;
  4954. struct drm_framebuffer *old_fb;
  4955. int i = -1;
  4956. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  4957. connector->base.id, drm_get_connector_name(connector),
  4958. encoder->base.id, drm_get_encoder_name(encoder));
  4959. /*
  4960. * Algorithm gets a little messy:
  4961. *
  4962. * - if the connector already has an assigned crtc, use it (but make
  4963. * sure it's on first)
  4964. *
  4965. * - try to find the first unused crtc that can drive this connector,
  4966. * and use that if we find one
  4967. */
  4968. /* See if we already have a CRTC for this connector */
  4969. if (encoder->crtc) {
  4970. crtc = encoder->crtc;
  4971. intel_crtc = to_intel_crtc(crtc);
  4972. old->dpms_mode = intel_crtc->dpms_mode;
  4973. old->load_detect_temp = false;
  4974. /* Make sure the crtc and connector are running */
  4975. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  4976. struct drm_encoder_helper_funcs *encoder_funcs;
  4977. struct drm_crtc_helper_funcs *crtc_funcs;
  4978. crtc_funcs = crtc->helper_private;
  4979. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  4980. encoder_funcs = encoder->helper_private;
  4981. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  4982. }
  4983. return true;
  4984. }
  4985. /* Find an unused one (if possible) */
  4986. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  4987. i++;
  4988. if (!(encoder->possible_crtcs & (1 << i)))
  4989. continue;
  4990. if (!possible_crtc->enabled) {
  4991. crtc = possible_crtc;
  4992. break;
  4993. }
  4994. }
  4995. /*
  4996. * If we didn't find an unused CRTC, don't use any.
  4997. */
  4998. if (!crtc) {
  4999. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  5000. return false;
  5001. }
  5002. encoder->crtc = crtc;
  5003. connector->encoder = encoder;
  5004. intel_crtc = to_intel_crtc(crtc);
  5005. old->dpms_mode = intel_crtc->dpms_mode;
  5006. old->load_detect_temp = true;
  5007. old->release_fb = NULL;
  5008. if (!mode)
  5009. mode = &load_detect_mode;
  5010. old_fb = crtc->fb;
  5011. /* We need a framebuffer large enough to accommodate all accesses
  5012. * that the plane may generate whilst we perform load detection.
  5013. * We can not rely on the fbcon either being present (we get called
  5014. * during its initialisation to detect all boot displays, or it may
  5015. * not even exist) or that it is large enough to satisfy the
  5016. * requested mode.
  5017. */
  5018. crtc->fb = mode_fits_in_fbdev(dev, mode);
  5019. if (crtc->fb == NULL) {
  5020. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  5021. crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  5022. old->release_fb = crtc->fb;
  5023. } else
  5024. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  5025. if (IS_ERR(crtc->fb)) {
  5026. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  5027. crtc->fb = old_fb;
  5028. return false;
  5029. }
  5030. if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
  5031. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  5032. if (old->release_fb)
  5033. old->release_fb->funcs->destroy(old->release_fb);
  5034. crtc->fb = old_fb;
  5035. return false;
  5036. }
  5037. /* let the connector get through one full cycle before testing */
  5038. intel_wait_for_vblank(dev, intel_crtc->pipe);
  5039. return true;
  5040. }
  5041. void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
  5042. struct drm_connector *connector,
  5043. struct intel_load_detect_pipe *old)
  5044. {
  5045. struct drm_encoder *encoder = &intel_encoder->base;
  5046. struct drm_device *dev = encoder->dev;
  5047. struct drm_crtc *crtc = encoder->crtc;
  5048. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  5049. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  5050. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5051. connector->base.id, drm_get_connector_name(connector),
  5052. encoder->base.id, drm_get_encoder_name(encoder));
  5053. if (old->load_detect_temp) {
  5054. connector->encoder = NULL;
  5055. drm_helper_disable_unused_functions(dev);
  5056. if (old->release_fb)
  5057. old->release_fb->funcs->destroy(old->release_fb);
  5058. return;
  5059. }
  5060. /* Switch crtc and encoder back off if necessary */
  5061. if (old->dpms_mode != DRM_MODE_DPMS_ON) {
  5062. encoder_funcs->dpms(encoder, old->dpms_mode);
  5063. crtc_funcs->dpms(crtc, old->dpms_mode);
  5064. }
  5065. }
  5066. /* Returns the clock of the currently programmed mode of the given pipe. */
  5067. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  5068. {
  5069. struct drm_i915_private *dev_priv = dev->dev_private;
  5070. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5071. int pipe = intel_crtc->pipe;
  5072. u32 dpll = I915_READ(DPLL(pipe));
  5073. u32 fp;
  5074. intel_clock_t clock;
  5075. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  5076. fp = I915_READ(FP0(pipe));
  5077. else
  5078. fp = I915_READ(FP1(pipe));
  5079. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  5080. if (IS_PINEVIEW(dev)) {
  5081. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  5082. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5083. } else {
  5084. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  5085. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5086. }
  5087. if (!IS_GEN2(dev)) {
  5088. if (IS_PINEVIEW(dev))
  5089. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  5090. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  5091. else
  5092. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  5093. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5094. switch (dpll & DPLL_MODE_MASK) {
  5095. case DPLLB_MODE_DAC_SERIAL:
  5096. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  5097. 5 : 10;
  5098. break;
  5099. case DPLLB_MODE_LVDS:
  5100. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  5101. 7 : 14;
  5102. break;
  5103. default:
  5104. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  5105. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  5106. return 0;
  5107. }
  5108. /* XXX: Handle the 100Mhz refclk */
  5109. intel_clock(dev, 96000, &clock);
  5110. } else {
  5111. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  5112. if (is_lvds) {
  5113. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  5114. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5115. clock.p2 = 14;
  5116. if ((dpll & PLL_REF_INPUT_MASK) ==
  5117. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  5118. /* XXX: might not be 66MHz */
  5119. intel_clock(dev, 66000, &clock);
  5120. } else
  5121. intel_clock(dev, 48000, &clock);
  5122. } else {
  5123. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  5124. clock.p1 = 2;
  5125. else {
  5126. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  5127. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  5128. }
  5129. if (dpll & PLL_P2_DIVIDE_BY_4)
  5130. clock.p2 = 4;
  5131. else
  5132. clock.p2 = 2;
  5133. intel_clock(dev, 48000, &clock);
  5134. }
  5135. }
  5136. /* XXX: It would be nice to validate the clocks, but we can't reuse
  5137. * i830PllIsValid() because it relies on the xf86_config connector
  5138. * configuration being accurate, which it isn't necessarily.
  5139. */
  5140. return clock.dot;
  5141. }
  5142. /** Returns the currently programmed mode of the given pipe. */
  5143. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  5144. struct drm_crtc *crtc)
  5145. {
  5146. struct drm_i915_private *dev_priv = dev->dev_private;
  5147. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5148. int pipe = intel_crtc->pipe;
  5149. struct drm_display_mode *mode;
  5150. int htot = I915_READ(HTOTAL(pipe));
  5151. int hsync = I915_READ(HSYNC(pipe));
  5152. int vtot = I915_READ(VTOTAL(pipe));
  5153. int vsync = I915_READ(VSYNC(pipe));
  5154. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  5155. if (!mode)
  5156. return NULL;
  5157. mode->clock = intel_crtc_clock_get(dev, crtc);
  5158. mode->hdisplay = (htot & 0xffff) + 1;
  5159. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  5160. mode->hsync_start = (hsync & 0xffff) + 1;
  5161. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  5162. mode->vdisplay = (vtot & 0xffff) + 1;
  5163. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  5164. mode->vsync_start = (vsync & 0xffff) + 1;
  5165. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  5166. drm_mode_set_name(mode);
  5167. drm_mode_set_crtcinfo(mode, 0);
  5168. return mode;
  5169. }
  5170. #define GPU_IDLE_TIMEOUT 500 /* ms */
  5171. /* When this timer fires, we've been idle for awhile */
  5172. static void intel_gpu_idle_timer(unsigned long arg)
  5173. {
  5174. struct drm_device *dev = (struct drm_device *)arg;
  5175. drm_i915_private_t *dev_priv = dev->dev_private;
  5176. if (!list_empty(&dev_priv->mm.active_list)) {
  5177. /* Still processing requests, so just re-arm the timer. */
  5178. mod_timer(&dev_priv->idle_timer, jiffies +
  5179. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  5180. return;
  5181. }
  5182. dev_priv->busy = false;
  5183. queue_work(dev_priv->wq, &dev_priv->idle_work);
  5184. }
  5185. #define CRTC_IDLE_TIMEOUT 1000 /* ms */
  5186. static void intel_crtc_idle_timer(unsigned long arg)
  5187. {
  5188. struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
  5189. struct drm_crtc *crtc = &intel_crtc->base;
  5190. drm_i915_private_t *dev_priv = crtc->dev->dev_private;
  5191. struct intel_framebuffer *intel_fb;
  5192. intel_fb = to_intel_framebuffer(crtc->fb);
  5193. if (intel_fb && intel_fb->obj->active) {
  5194. /* The framebuffer is still being accessed by the GPU. */
  5195. mod_timer(&intel_crtc->idle_timer, jiffies +
  5196. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  5197. return;
  5198. }
  5199. intel_crtc->busy = false;
  5200. queue_work(dev_priv->wq, &dev_priv->idle_work);
  5201. }
  5202. static void intel_increase_pllclock(struct drm_crtc *crtc)
  5203. {
  5204. struct drm_device *dev = crtc->dev;
  5205. drm_i915_private_t *dev_priv = dev->dev_private;
  5206. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5207. int pipe = intel_crtc->pipe;
  5208. int dpll_reg = DPLL(pipe);
  5209. int dpll;
  5210. if (HAS_PCH_SPLIT(dev))
  5211. return;
  5212. if (!dev_priv->lvds_downclock_avail)
  5213. return;
  5214. dpll = I915_READ(dpll_reg);
  5215. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  5216. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  5217. /* Unlock panel regs */
  5218. I915_WRITE(PP_CONTROL,
  5219. I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
  5220. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  5221. I915_WRITE(dpll_reg, dpll);
  5222. intel_wait_for_vblank(dev, pipe);
  5223. dpll = I915_READ(dpll_reg);
  5224. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  5225. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  5226. /* ...and lock them again */
  5227. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  5228. }
  5229. /* Schedule downclock */
  5230. mod_timer(&intel_crtc->idle_timer, jiffies +
  5231. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  5232. }
  5233. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  5234. {
  5235. struct drm_device *dev = crtc->dev;
  5236. drm_i915_private_t *dev_priv = dev->dev_private;
  5237. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5238. int pipe = intel_crtc->pipe;
  5239. int dpll_reg = DPLL(pipe);
  5240. int dpll = I915_READ(dpll_reg);
  5241. if (HAS_PCH_SPLIT(dev))
  5242. return;
  5243. if (!dev_priv->lvds_downclock_avail)
  5244. return;
  5245. /*
  5246. * Since this is called by a timer, we should never get here in
  5247. * the manual case.
  5248. */
  5249. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  5250. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  5251. /* Unlock panel regs */
  5252. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
  5253. PANEL_UNLOCK_REGS);
  5254. dpll |= DISPLAY_RATE_SELECT_FPA1;
  5255. I915_WRITE(dpll_reg, dpll);
  5256. intel_wait_for_vblank(dev, pipe);
  5257. dpll = I915_READ(dpll_reg);
  5258. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  5259. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  5260. /* ...and lock them again */
  5261. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  5262. }
  5263. }
  5264. /**
  5265. * intel_idle_update - adjust clocks for idleness
  5266. * @work: work struct
  5267. *
  5268. * Either the GPU or display (or both) went idle. Check the busy status
  5269. * here and adjust the CRTC and GPU clocks as necessary.
  5270. */
  5271. static void intel_idle_update(struct work_struct *work)
  5272. {
  5273. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  5274. idle_work);
  5275. struct drm_device *dev = dev_priv->dev;
  5276. struct drm_crtc *crtc;
  5277. struct intel_crtc *intel_crtc;
  5278. if (!i915_powersave)
  5279. return;
  5280. mutex_lock(&dev->struct_mutex);
  5281. i915_update_gfx_val(dev_priv);
  5282. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5283. /* Skip inactive CRTCs */
  5284. if (!crtc->fb)
  5285. continue;
  5286. intel_crtc = to_intel_crtc(crtc);
  5287. if (!intel_crtc->busy)
  5288. intel_decrease_pllclock(crtc);
  5289. }
  5290. mutex_unlock(&dev->struct_mutex);
  5291. }
  5292. /**
  5293. * intel_mark_busy - mark the GPU and possibly the display busy
  5294. * @dev: drm device
  5295. * @obj: object we're operating on
  5296. *
  5297. * Callers can use this function to indicate that the GPU is busy processing
  5298. * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
  5299. * buffer), we'll also mark the display as busy, so we know to increase its
  5300. * clock frequency.
  5301. */
  5302. void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
  5303. {
  5304. drm_i915_private_t *dev_priv = dev->dev_private;
  5305. struct drm_crtc *crtc = NULL;
  5306. struct intel_framebuffer *intel_fb;
  5307. struct intel_crtc *intel_crtc;
  5308. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  5309. return;
  5310. if (!dev_priv->busy)
  5311. dev_priv->busy = true;
  5312. else
  5313. mod_timer(&dev_priv->idle_timer, jiffies +
  5314. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  5315. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5316. if (!crtc->fb)
  5317. continue;
  5318. intel_crtc = to_intel_crtc(crtc);
  5319. intel_fb = to_intel_framebuffer(crtc->fb);
  5320. if (intel_fb->obj == obj) {
  5321. if (!intel_crtc->busy) {
  5322. /* Non-busy -> busy, upclock */
  5323. intel_increase_pllclock(crtc);
  5324. intel_crtc->busy = true;
  5325. } else {
  5326. /* Busy -> busy, put off timer */
  5327. mod_timer(&intel_crtc->idle_timer, jiffies +
  5328. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  5329. }
  5330. }
  5331. }
  5332. }
  5333. static void intel_crtc_destroy(struct drm_crtc *crtc)
  5334. {
  5335. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5336. struct drm_device *dev = crtc->dev;
  5337. struct intel_unpin_work *work;
  5338. unsigned long flags;
  5339. spin_lock_irqsave(&dev->event_lock, flags);
  5340. work = intel_crtc->unpin_work;
  5341. intel_crtc->unpin_work = NULL;
  5342. spin_unlock_irqrestore(&dev->event_lock, flags);
  5343. if (work) {
  5344. cancel_work_sync(&work->work);
  5345. kfree(work);
  5346. }
  5347. drm_crtc_cleanup(crtc);
  5348. kfree(intel_crtc);
  5349. }
  5350. static void intel_unpin_work_fn(struct work_struct *__work)
  5351. {
  5352. struct intel_unpin_work *work =
  5353. container_of(__work, struct intel_unpin_work, work);
  5354. mutex_lock(&work->dev->struct_mutex);
  5355. i915_gem_object_unpin(work->old_fb_obj);
  5356. drm_gem_object_unreference(&work->pending_flip_obj->base);
  5357. drm_gem_object_unreference(&work->old_fb_obj->base);
  5358. mutex_unlock(&work->dev->struct_mutex);
  5359. kfree(work);
  5360. }
  5361. static void do_intel_finish_page_flip(struct drm_device *dev,
  5362. struct drm_crtc *crtc)
  5363. {
  5364. drm_i915_private_t *dev_priv = dev->dev_private;
  5365. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5366. struct intel_unpin_work *work;
  5367. struct drm_i915_gem_object *obj;
  5368. struct drm_pending_vblank_event *e;
  5369. struct timeval tnow, tvbl;
  5370. unsigned long flags;
  5371. /* Ignore early vblank irqs */
  5372. if (intel_crtc == NULL)
  5373. return;
  5374. do_gettimeofday(&tnow);
  5375. spin_lock_irqsave(&dev->event_lock, flags);
  5376. work = intel_crtc->unpin_work;
  5377. if (work == NULL || !work->pending) {
  5378. spin_unlock_irqrestore(&dev->event_lock, flags);
  5379. return;
  5380. }
  5381. intel_crtc->unpin_work = NULL;
  5382. if (work->event) {
  5383. e = work->event;
  5384. e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
  5385. /* Called before vblank count and timestamps have
  5386. * been updated for the vblank interval of flip
  5387. * completion? Need to increment vblank count and
  5388. * add one videorefresh duration to returned timestamp
  5389. * to account for this. We assume this happened if we
  5390. * get called over 0.9 frame durations after the last
  5391. * timestamped vblank.
  5392. *
  5393. * This calculation can not be used with vrefresh rates
  5394. * below 5Hz (10Hz to be on the safe side) without
  5395. * promoting to 64 integers.
  5396. */
  5397. if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
  5398. 9 * crtc->framedur_ns) {
  5399. e->event.sequence++;
  5400. tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
  5401. crtc->framedur_ns);
  5402. }
  5403. e->event.tv_sec = tvbl.tv_sec;
  5404. e->event.tv_usec = tvbl.tv_usec;
  5405. list_add_tail(&e->base.link,
  5406. &e->base.file_priv->event_list);
  5407. wake_up_interruptible(&e->base.file_priv->event_wait);
  5408. }
  5409. drm_vblank_put(dev, intel_crtc->pipe);
  5410. spin_unlock_irqrestore(&dev->event_lock, flags);
  5411. obj = work->old_fb_obj;
  5412. atomic_clear_mask(1 << intel_crtc->plane,
  5413. &obj->pending_flip.counter);
  5414. if (atomic_read(&obj->pending_flip) == 0)
  5415. wake_up(&dev_priv->pending_flip_queue);
  5416. schedule_work(&work->work);
  5417. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  5418. }
  5419. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  5420. {
  5421. drm_i915_private_t *dev_priv = dev->dev_private;
  5422. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  5423. do_intel_finish_page_flip(dev, crtc);
  5424. }
  5425. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  5426. {
  5427. drm_i915_private_t *dev_priv = dev->dev_private;
  5428. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  5429. do_intel_finish_page_flip(dev, crtc);
  5430. }
  5431. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  5432. {
  5433. drm_i915_private_t *dev_priv = dev->dev_private;
  5434. struct intel_crtc *intel_crtc =
  5435. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  5436. unsigned long flags;
  5437. spin_lock_irqsave(&dev->event_lock, flags);
  5438. if (intel_crtc->unpin_work) {
  5439. if ((++intel_crtc->unpin_work->pending) > 1)
  5440. DRM_ERROR("Prepared flip multiple times\n");
  5441. } else {
  5442. DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
  5443. }
  5444. spin_unlock_irqrestore(&dev->event_lock, flags);
  5445. }
  5446. static int intel_gen2_queue_flip(struct drm_device *dev,
  5447. struct drm_crtc *crtc,
  5448. struct drm_framebuffer *fb,
  5449. struct drm_i915_gem_object *obj)
  5450. {
  5451. struct drm_i915_private *dev_priv = dev->dev_private;
  5452. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5453. unsigned long offset;
  5454. u32 flip_mask;
  5455. int ret;
  5456. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  5457. if (ret)
  5458. goto out;
  5459. /* Offset into the new buffer for cases of shared fbs between CRTCs */
  5460. offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
  5461. ret = BEGIN_LP_RING(6);
  5462. if (ret)
  5463. goto out;
  5464. /* Can't queue multiple flips, so wait for the previous
  5465. * one to finish before executing the next.
  5466. */
  5467. if (intel_crtc->plane)
  5468. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  5469. else
  5470. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  5471. OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
  5472. OUT_RING(MI_NOOP);
  5473. OUT_RING(MI_DISPLAY_FLIP |
  5474. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5475. OUT_RING(fb->pitch);
  5476. OUT_RING(obj->gtt_offset + offset);
  5477. OUT_RING(MI_NOOP);
  5478. ADVANCE_LP_RING();
  5479. out:
  5480. return ret;
  5481. }
  5482. static int intel_gen3_queue_flip(struct drm_device *dev,
  5483. struct drm_crtc *crtc,
  5484. struct drm_framebuffer *fb,
  5485. struct drm_i915_gem_object *obj)
  5486. {
  5487. struct drm_i915_private *dev_priv = dev->dev_private;
  5488. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5489. unsigned long offset;
  5490. u32 flip_mask;
  5491. int ret;
  5492. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  5493. if (ret)
  5494. goto out;
  5495. /* Offset into the new buffer for cases of shared fbs between CRTCs */
  5496. offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
  5497. ret = BEGIN_LP_RING(6);
  5498. if (ret)
  5499. goto out;
  5500. if (intel_crtc->plane)
  5501. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  5502. else
  5503. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  5504. OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
  5505. OUT_RING(MI_NOOP);
  5506. OUT_RING(MI_DISPLAY_FLIP_I915 |
  5507. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5508. OUT_RING(fb->pitch);
  5509. OUT_RING(obj->gtt_offset + offset);
  5510. OUT_RING(MI_NOOP);
  5511. ADVANCE_LP_RING();
  5512. out:
  5513. return ret;
  5514. }
  5515. static int intel_gen4_queue_flip(struct drm_device *dev,
  5516. struct drm_crtc *crtc,
  5517. struct drm_framebuffer *fb,
  5518. struct drm_i915_gem_object *obj)
  5519. {
  5520. struct drm_i915_private *dev_priv = dev->dev_private;
  5521. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5522. uint32_t pf, pipesrc;
  5523. int ret;
  5524. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  5525. if (ret)
  5526. goto out;
  5527. ret = BEGIN_LP_RING(4);
  5528. if (ret)
  5529. goto out;
  5530. /* i965+ uses the linear or tiled offsets from the
  5531. * Display Registers (which do not change across a page-flip)
  5532. * so we need only reprogram the base address.
  5533. */
  5534. OUT_RING(MI_DISPLAY_FLIP |
  5535. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5536. OUT_RING(fb->pitch);
  5537. OUT_RING(obj->gtt_offset | obj->tiling_mode);
  5538. /* XXX Enabling the panel-fitter across page-flip is so far
  5539. * untested on non-native modes, so ignore it for now.
  5540. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  5541. */
  5542. pf = 0;
  5543. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  5544. OUT_RING(pf | pipesrc);
  5545. ADVANCE_LP_RING();
  5546. out:
  5547. return ret;
  5548. }
  5549. static int intel_gen6_queue_flip(struct drm_device *dev,
  5550. struct drm_crtc *crtc,
  5551. struct drm_framebuffer *fb,
  5552. struct drm_i915_gem_object *obj)
  5553. {
  5554. struct drm_i915_private *dev_priv = dev->dev_private;
  5555. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5556. uint32_t pf, pipesrc;
  5557. int ret;
  5558. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  5559. if (ret)
  5560. goto out;
  5561. ret = BEGIN_LP_RING(4);
  5562. if (ret)
  5563. goto out;
  5564. OUT_RING(MI_DISPLAY_FLIP |
  5565. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5566. OUT_RING(fb->pitch | obj->tiling_mode);
  5567. OUT_RING(obj->gtt_offset);
  5568. pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  5569. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  5570. OUT_RING(pf | pipesrc);
  5571. ADVANCE_LP_RING();
  5572. out:
  5573. return ret;
  5574. }
  5575. /*
  5576. * On gen7 we currently use the blit ring because (in early silicon at least)
  5577. * the render ring doesn't give us interrpts for page flip completion, which
  5578. * means clients will hang after the first flip is queued. Fortunately the
  5579. * blit ring generates interrupts properly, so use it instead.
  5580. */
  5581. static int intel_gen7_queue_flip(struct drm_device *dev,
  5582. struct drm_crtc *crtc,
  5583. struct drm_framebuffer *fb,
  5584. struct drm_i915_gem_object *obj)
  5585. {
  5586. struct drm_i915_private *dev_priv = dev->dev_private;
  5587. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5588. struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
  5589. int ret;
  5590. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5591. if (ret)
  5592. goto out;
  5593. ret = intel_ring_begin(ring, 4);
  5594. if (ret)
  5595. goto out;
  5596. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
  5597. intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
  5598. intel_ring_emit(ring, (obj->gtt_offset));
  5599. intel_ring_emit(ring, (MI_NOOP));
  5600. intel_ring_advance(ring);
  5601. out:
  5602. return ret;
  5603. }
  5604. static int intel_default_queue_flip(struct drm_device *dev,
  5605. struct drm_crtc *crtc,
  5606. struct drm_framebuffer *fb,
  5607. struct drm_i915_gem_object *obj)
  5608. {
  5609. return -ENODEV;
  5610. }
  5611. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  5612. struct drm_framebuffer *fb,
  5613. struct drm_pending_vblank_event *event)
  5614. {
  5615. struct drm_device *dev = crtc->dev;
  5616. struct drm_i915_private *dev_priv = dev->dev_private;
  5617. struct intel_framebuffer *intel_fb;
  5618. struct drm_i915_gem_object *obj;
  5619. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5620. struct intel_unpin_work *work;
  5621. unsigned long flags;
  5622. int ret;
  5623. work = kzalloc(sizeof *work, GFP_KERNEL);
  5624. if (work == NULL)
  5625. return -ENOMEM;
  5626. work->event = event;
  5627. work->dev = crtc->dev;
  5628. intel_fb = to_intel_framebuffer(crtc->fb);
  5629. work->old_fb_obj = intel_fb->obj;
  5630. INIT_WORK(&work->work, intel_unpin_work_fn);
  5631. /* We borrow the event spin lock for protecting unpin_work */
  5632. spin_lock_irqsave(&dev->event_lock, flags);
  5633. if (intel_crtc->unpin_work) {
  5634. spin_unlock_irqrestore(&dev->event_lock, flags);
  5635. kfree(work);
  5636. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  5637. return -EBUSY;
  5638. }
  5639. intel_crtc->unpin_work = work;
  5640. spin_unlock_irqrestore(&dev->event_lock, flags);
  5641. intel_fb = to_intel_framebuffer(fb);
  5642. obj = intel_fb->obj;
  5643. mutex_lock(&dev->struct_mutex);
  5644. /* Reference the objects for the scheduled work. */
  5645. drm_gem_object_reference(&work->old_fb_obj->base);
  5646. drm_gem_object_reference(&obj->base);
  5647. crtc->fb = fb;
  5648. ret = drm_vblank_get(dev, intel_crtc->pipe);
  5649. if (ret)
  5650. goto cleanup_objs;
  5651. work->pending_flip_obj = obj;
  5652. work->enable_stall_check = true;
  5653. /* Block clients from rendering to the new back buffer until
  5654. * the flip occurs and the object is no longer visible.
  5655. */
  5656. atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
  5657. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
  5658. if (ret)
  5659. goto cleanup_pending;
  5660. mutex_unlock(&dev->struct_mutex);
  5661. trace_i915_flip_request(intel_crtc->plane, obj);
  5662. return 0;
  5663. cleanup_pending:
  5664. atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
  5665. cleanup_objs:
  5666. drm_gem_object_unreference(&work->old_fb_obj->base);
  5667. drm_gem_object_unreference(&obj->base);
  5668. mutex_unlock(&dev->struct_mutex);
  5669. spin_lock_irqsave(&dev->event_lock, flags);
  5670. intel_crtc->unpin_work = NULL;
  5671. spin_unlock_irqrestore(&dev->event_lock, flags);
  5672. kfree(work);
  5673. return ret;
  5674. }
  5675. static void intel_sanitize_modesetting(struct drm_device *dev,
  5676. int pipe, int plane)
  5677. {
  5678. struct drm_i915_private *dev_priv = dev->dev_private;
  5679. u32 reg, val;
  5680. if (HAS_PCH_SPLIT(dev))
  5681. return;
  5682. /* Who knows what state these registers were left in by the BIOS or
  5683. * grub?
  5684. *
  5685. * If we leave the registers in a conflicting state (e.g. with the
  5686. * display plane reading from the other pipe than the one we intend
  5687. * to use) then when we attempt to teardown the active mode, we will
  5688. * not disable the pipes and planes in the correct order -- leaving
  5689. * a plane reading from a disabled pipe and possibly leading to
  5690. * undefined behaviour.
  5691. */
  5692. reg = DSPCNTR(plane);
  5693. val = I915_READ(reg);
  5694. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  5695. return;
  5696. if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
  5697. return;
  5698. /* This display plane is active and attached to the other CPU pipe. */
  5699. pipe = !pipe;
  5700. /* Disable the plane and wait for it to stop reading from the pipe. */
  5701. intel_disable_plane(dev_priv, plane, pipe);
  5702. intel_disable_pipe(dev_priv, pipe);
  5703. }
  5704. static void intel_crtc_reset(struct drm_crtc *crtc)
  5705. {
  5706. struct drm_device *dev = crtc->dev;
  5707. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5708. /* Reset flags back to the 'unknown' status so that they
  5709. * will be correctly set on the initial modeset.
  5710. */
  5711. intel_crtc->dpms_mode = -1;
  5712. /* We need to fix up any BIOS configuration that conflicts with
  5713. * our expectations.
  5714. */
  5715. intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
  5716. }
  5717. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  5718. .dpms = intel_crtc_dpms,
  5719. .mode_fixup = intel_crtc_mode_fixup,
  5720. .mode_set = intel_crtc_mode_set,
  5721. .mode_set_base = intel_pipe_set_base,
  5722. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  5723. .load_lut = intel_crtc_load_lut,
  5724. .disable = intel_crtc_disable,
  5725. };
  5726. static const struct drm_crtc_funcs intel_crtc_funcs = {
  5727. .reset = intel_crtc_reset,
  5728. .cursor_set = intel_crtc_cursor_set,
  5729. .cursor_move = intel_crtc_cursor_move,
  5730. .gamma_set = intel_crtc_gamma_set,
  5731. .set_config = drm_crtc_helper_set_config,
  5732. .destroy = intel_crtc_destroy,
  5733. .page_flip = intel_crtc_page_flip,
  5734. };
  5735. static void intel_crtc_init(struct drm_device *dev, int pipe)
  5736. {
  5737. drm_i915_private_t *dev_priv = dev->dev_private;
  5738. struct intel_crtc *intel_crtc;
  5739. int i;
  5740. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  5741. if (intel_crtc == NULL)
  5742. return;
  5743. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  5744. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  5745. for (i = 0; i < 256; i++) {
  5746. intel_crtc->lut_r[i] = i;
  5747. intel_crtc->lut_g[i] = i;
  5748. intel_crtc->lut_b[i] = i;
  5749. }
  5750. /* Swap pipes & planes for FBC on pre-965 */
  5751. intel_crtc->pipe = pipe;
  5752. intel_crtc->plane = pipe;
  5753. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  5754. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  5755. intel_crtc->plane = !pipe;
  5756. }
  5757. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  5758. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  5759. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  5760. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  5761. intel_crtc_reset(&intel_crtc->base);
  5762. intel_crtc->active = true; /* force the pipe off on setup_init_config */
  5763. if (HAS_PCH_SPLIT(dev)) {
  5764. intel_helper_funcs.prepare = ironlake_crtc_prepare;
  5765. intel_helper_funcs.commit = ironlake_crtc_commit;
  5766. } else {
  5767. intel_helper_funcs.prepare = i9xx_crtc_prepare;
  5768. intel_helper_funcs.commit = i9xx_crtc_commit;
  5769. }
  5770. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  5771. intel_crtc->busy = false;
  5772. setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
  5773. (unsigned long)intel_crtc);
  5774. }
  5775. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  5776. struct drm_file *file)
  5777. {
  5778. drm_i915_private_t *dev_priv = dev->dev_private;
  5779. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  5780. struct drm_mode_object *drmmode_obj;
  5781. struct intel_crtc *crtc;
  5782. if (!dev_priv) {
  5783. DRM_ERROR("called with no initialization\n");
  5784. return -EINVAL;
  5785. }
  5786. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  5787. DRM_MODE_OBJECT_CRTC);
  5788. if (!drmmode_obj) {
  5789. DRM_ERROR("no such CRTC id\n");
  5790. return -EINVAL;
  5791. }
  5792. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  5793. pipe_from_crtc_id->pipe = crtc->pipe;
  5794. return 0;
  5795. }
  5796. static int intel_encoder_clones(struct drm_device *dev, int type_mask)
  5797. {
  5798. struct intel_encoder *encoder;
  5799. int index_mask = 0;
  5800. int entry = 0;
  5801. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  5802. if (type_mask & encoder->clone_mask)
  5803. index_mask |= (1 << entry);
  5804. entry++;
  5805. }
  5806. return index_mask;
  5807. }
  5808. static bool has_edp_a(struct drm_device *dev)
  5809. {
  5810. struct drm_i915_private *dev_priv = dev->dev_private;
  5811. if (!IS_MOBILE(dev))
  5812. return false;
  5813. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  5814. return false;
  5815. if (IS_GEN5(dev) &&
  5816. (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  5817. return false;
  5818. return true;
  5819. }
  5820. static void intel_setup_outputs(struct drm_device *dev)
  5821. {
  5822. struct drm_i915_private *dev_priv = dev->dev_private;
  5823. struct intel_encoder *encoder;
  5824. bool dpd_is_edp = false;
  5825. bool has_lvds = false;
  5826. if (IS_MOBILE(dev) && !IS_I830(dev))
  5827. has_lvds = intel_lvds_init(dev);
  5828. if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
  5829. /* disable the panel fitter on everything but LVDS */
  5830. I915_WRITE(PFIT_CONTROL, 0);
  5831. }
  5832. if (HAS_PCH_SPLIT(dev)) {
  5833. dpd_is_edp = intel_dpd_is_edp(dev);
  5834. if (has_edp_a(dev))
  5835. intel_dp_init(dev, DP_A);
  5836. if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  5837. intel_dp_init(dev, PCH_DP_D);
  5838. }
  5839. intel_crt_init(dev);
  5840. if (HAS_PCH_SPLIT(dev)) {
  5841. int found;
  5842. if (I915_READ(HDMIB) & PORT_DETECTED) {
  5843. /* PCH SDVOB multiplex with HDMIB */
  5844. found = intel_sdvo_init(dev, PCH_SDVOB);
  5845. if (!found)
  5846. intel_hdmi_init(dev, HDMIB);
  5847. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  5848. intel_dp_init(dev, PCH_DP_B);
  5849. }
  5850. if (I915_READ(HDMIC) & PORT_DETECTED)
  5851. intel_hdmi_init(dev, HDMIC);
  5852. if (I915_READ(HDMID) & PORT_DETECTED)
  5853. intel_hdmi_init(dev, HDMID);
  5854. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  5855. intel_dp_init(dev, PCH_DP_C);
  5856. if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  5857. intel_dp_init(dev, PCH_DP_D);
  5858. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  5859. bool found = false;
  5860. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  5861. DRM_DEBUG_KMS("probing SDVOB\n");
  5862. found = intel_sdvo_init(dev, SDVOB);
  5863. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  5864. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  5865. intel_hdmi_init(dev, SDVOB);
  5866. }
  5867. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  5868. DRM_DEBUG_KMS("probing DP_B\n");
  5869. intel_dp_init(dev, DP_B);
  5870. }
  5871. }
  5872. /* Before G4X SDVOC doesn't have its own detect register */
  5873. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  5874. DRM_DEBUG_KMS("probing SDVOC\n");
  5875. found = intel_sdvo_init(dev, SDVOC);
  5876. }
  5877. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  5878. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  5879. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  5880. intel_hdmi_init(dev, SDVOC);
  5881. }
  5882. if (SUPPORTS_INTEGRATED_DP(dev)) {
  5883. DRM_DEBUG_KMS("probing DP_C\n");
  5884. intel_dp_init(dev, DP_C);
  5885. }
  5886. }
  5887. if (SUPPORTS_INTEGRATED_DP(dev) &&
  5888. (I915_READ(DP_D) & DP_DETECTED)) {
  5889. DRM_DEBUG_KMS("probing DP_D\n");
  5890. intel_dp_init(dev, DP_D);
  5891. }
  5892. } else if (IS_GEN2(dev))
  5893. intel_dvo_init(dev);
  5894. if (SUPPORTS_TV(dev))
  5895. intel_tv_init(dev);
  5896. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  5897. encoder->base.possible_crtcs = encoder->crtc_mask;
  5898. encoder->base.possible_clones =
  5899. intel_encoder_clones(dev, encoder->clone_mask);
  5900. }
  5901. intel_panel_setup_backlight(dev);
  5902. /* disable all the possible outputs/crtcs before entering KMS mode */
  5903. drm_helper_disable_unused_functions(dev);
  5904. }
  5905. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  5906. {
  5907. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  5908. drm_framebuffer_cleanup(fb);
  5909. drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
  5910. kfree(intel_fb);
  5911. }
  5912. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  5913. struct drm_file *file,
  5914. unsigned int *handle)
  5915. {
  5916. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  5917. struct drm_i915_gem_object *obj = intel_fb->obj;
  5918. return drm_gem_handle_create(file, &obj->base, handle);
  5919. }
  5920. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  5921. .destroy = intel_user_framebuffer_destroy,
  5922. .create_handle = intel_user_framebuffer_create_handle,
  5923. };
  5924. int intel_framebuffer_init(struct drm_device *dev,
  5925. struct intel_framebuffer *intel_fb,
  5926. struct drm_mode_fb_cmd *mode_cmd,
  5927. struct drm_i915_gem_object *obj)
  5928. {
  5929. int ret;
  5930. if (obj->tiling_mode == I915_TILING_Y)
  5931. return -EINVAL;
  5932. if (mode_cmd->pitch & 63)
  5933. return -EINVAL;
  5934. switch (mode_cmd->bpp) {
  5935. case 8:
  5936. case 16:
  5937. case 24:
  5938. case 32:
  5939. break;
  5940. default:
  5941. return -EINVAL;
  5942. }
  5943. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  5944. if (ret) {
  5945. DRM_ERROR("framebuffer init failed %d\n", ret);
  5946. return ret;
  5947. }
  5948. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  5949. intel_fb->obj = obj;
  5950. return 0;
  5951. }
  5952. static struct drm_framebuffer *
  5953. intel_user_framebuffer_create(struct drm_device *dev,
  5954. struct drm_file *filp,
  5955. struct drm_mode_fb_cmd *mode_cmd)
  5956. {
  5957. struct drm_i915_gem_object *obj;
  5958. obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
  5959. if (&obj->base == NULL)
  5960. return ERR_PTR(-ENOENT);
  5961. return intel_framebuffer_create(dev, mode_cmd, obj);
  5962. }
  5963. static const struct drm_mode_config_funcs intel_mode_funcs = {
  5964. .fb_create = intel_user_framebuffer_create,
  5965. .output_poll_changed = intel_fb_output_poll_changed,
  5966. };
  5967. static struct drm_i915_gem_object *
  5968. intel_alloc_context_page(struct drm_device *dev)
  5969. {
  5970. struct drm_i915_gem_object *ctx;
  5971. int ret;
  5972. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  5973. ctx = i915_gem_alloc_object(dev, 4096);
  5974. if (!ctx) {
  5975. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  5976. return NULL;
  5977. }
  5978. ret = i915_gem_object_pin(ctx, 4096, true);
  5979. if (ret) {
  5980. DRM_ERROR("failed to pin power context: %d\n", ret);
  5981. goto err_unref;
  5982. }
  5983. ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
  5984. if (ret) {
  5985. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  5986. goto err_unpin;
  5987. }
  5988. return ctx;
  5989. err_unpin:
  5990. i915_gem_object_unpin(ctx);
  5991. err_unref:
  5992. drm_gem_object_unreference(&ctx->base);
  5993. mutex_unlock(&dev->struct_mutex);
  5994. return NULL;
  5995. }
  5996. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  5997. {
  5998. struct drm_i915_private *dev_priv = dev->dev_private;
  5999. u16 rgvswctl;
  6000. rgvswctl = I915_READ16(MEMSWCTL);
  6001. if (rgvswctl & MEMCTL_CMD_STS) {
  6002. DRM_DEBUG("gpu busy, RCS change rejected\n");
  6003. return false; /* still busy with another command */
  6004. }
  6005. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  6006. (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  6007. I915_WRITE16(MEMSWCTL, rgvswctl);
  6008. POSTING_READ16(MEMSWCTL);
  6009. rgvswctl |= MEMCTL_CMD_STS;
  6010. I915_WRITE16(MEMSWCTL, rgvswctl);
  6011. return true;
  6012. }
  6013. void ironlake_enable_drps(struct drm_device *dev)
  6014. {
  6015. struct drm_i915_private *dev_priv = dev->dev_private;
  6016. u32 rgvmodectl = I915_READ(MEMMODECTL);
  6017. u8 fmax, fmin, fstart, vstart;
  6018. /* Enable temp reporting */
  6019. I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
  6020. I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
  6021. /* 100ms RC evaluation intervals */
  6022. I915_WRITE(RCUPEI, 100000);
  6023. I915_WRITE(RCDNEI, 100000);
  6024. /* Set max/min thresholds to 90ms and 80ms respectively */
  6025. I915_WRITE(RCBMAXAVG, 90000);
  6026. I915_WRITE(RCBMINAVG, 80000);
  6027. I915_WRITE(MEMIHYST, 1);
  6028. /* Set up min, max, and cur for interrupt handling */
  6029. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  6030. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  6031. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  6032. MEMMODE_FSTART_SHIFT;
  6033. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  6034. PXVFREQ_PX_SHIFT;
  6035. dev_priv->fmax = fmax; /* IPS callback will increase this */
  6036. dev_priv->fstart = fstart;
  6037. dev_priv->max_delay = fstart;
  6038. dev_priv->min_delay = fmin;
  6039. dev_priv->cur_delay = fstart;
  6040. DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
  6041. fmax, fmin, fstart);
  6042. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  6043. /*
  6044. * Interrupts will be enabled in ironlake_irq_postinstall
  6045. */
  6046. I915_WRITE(VIDSTART, vstart);
  6047. POSTING_READ(VIDSTART);
  6048. rgvmodectl |= MEMMODE_SWMODE_EN;
  6049. I915_WRITE(MEMMODECTL, rgvmodectl);
  6050. if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
  6051. DRM_ERROR("stuck trying to change perf mode\n");
  6052. msleep(1);
  6053. ironlake_set_drps(dev, fstart);
  6054. dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  6055. I915_READ(0x112e0);
  6056. dev_priv->last_time1 = jiffies_to_msecs(jiffies);
  6057. dev_priv->last_count2 = I915_READ(0x112f4);
  6058. getrawmonotonic(&dev_priv->last_time2);
  6059. }
  6060. void ironlake_disable_drps(struct drm_device *dev)
  6061. {
  6062. struct drm_i915_private *dev_priv = dev->dev_private;
  6063. u16 rgvswctl = I915_READ16(MEMSWCTL);
  6064. /* Ack interrupts, disable EFC interrupt */
  6065. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  6066. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  6067. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  6068. I915_WRITE(DEIIR, DE_PCU_EVENT);
  6069. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  6070. /* Go back to the starting frequency */
  6071. ironlake_set_drps(dev, dev_priv->fstart);
  6072. msleep(1);
  6073. rgvswctl |= MEMCTL_CMD_STS;
  6074. I915_WRITE(MEMSWCTL, rgvswctl);
  6075. msleep(1);
  6076. }
  6077. void gen6_set_rps(struct drm_device *dev, u8 val)
  6078. {
  6079. struct drm_i915_private *dev_priv = dev->dev_private;
  6080. u32 swreq;
  6081. swreq = (val & 0x3ff) << 25;
  6082. I915_WRITE(GEN6_RPNSWREQ, swreq);
  6083. }
  6084. void gen6_disable_rps(struct drm_device *dev)
  6085. {
  6086. struct drm_i915_private *dev_priv = dev->dev_private;
  6087. I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
  6088. I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
  6089. I915_WRITE(GEN6_PMIER, 0);
  6090. spin_lock_irq(&dev_priv->rps_lock);
  6091. dev_priv->pm_iir = 0;
  6092. spin_unlock_irq(&dev_priv->rps_lock);
  6093. I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
  6094. }
  6095. static unsigned long intel_pxfreq(u32 vidfreq)
  6096. {
  6097. unsigned long freq;
  6098. int div = (vidfreq & 0x3f0000) >> 16;
  6099. int post = (vidfreq & 0x3000) >> 12;
  6100. int pre = (vidfreq & 0x7);
  6101. if (!pre)
  6102. return 0;
  6103. freq = ((div * 133333) / ((1<<post) * pre));
  6104. return freq;
  6105. }
  6106. void intel_init_emon(struct drm_device *dev)
  6107. {
  6108. struct drm_i915_private *dev_priv = dev->dev_private;
  6109. u32 lcfuse;
  6110. u8 pxw[16];
  6111. int i;
  6112. /* Disable to program */
  6113. I915_WRITE(ECR, 0);
  6114. POSTING_READ(ECR);
  6115. /* Program energy weights for various events */
  6116. I915_WRITE(SDEW, 0x15040d00);
  6117. I915_WRITE(CSIEW0, 0x007f0000);
  6118. I915_WRITE(CSIEW1, 0x1e220004);
  6119. I915_WRITE(CSIEW2, 0x04000004);
  6120. for (i = 0; i < 5; i++)
  6121. I915_WRITE(PEW + (i * 4), 0);
  6122. for (i = 0; i < 3; i++)
  6123. I915_WRITE(DEW + (i * 4), 0);
  6124. /* Program P-state weights to account for frequency power adjustment */
  6125. for (i = 0; i < 16; i++) {
  6126. u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  6127. unsigned long freq = intel_pxfreq(pxvidfreq);
  6128. unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  6129. PXVFREQ_PX_SHIFT;
  6130. unsigned long val;
  6131. val = vid * vid;
  6132. val *= (freq / 1000);
  6133. val *= 255;
  6134. val /= (127*127*900);
  6135. if (val > 0xff)
  6136. DRM_ERROR("bad pxval: %ld\n", val);
  6137. pxw[i] = val;
  6138. }
  6139. /* Render standby states get 0 weight */
  6140. pxw[14] = 0;
  6141. pxw[15] = 0;
  6142. for (i = 0; i < 4; i++) {
  6143. u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  6144. (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  6145. I915_WRITE(PXW + (i * 4), val);
  6146. }
  6147. /* Adjust magic regs to magic values (more experimental results) */
  6148. I915_WRITE(OGW0, 0);
  6149. I915_WRITE(OGW1, 0);
  6150. I915_WRITE(EG0, 0x00007f00);
  6151. I915_WRITE(EG1, 0x0000000e);
  6152. I915_WRITE(EG2, 0x000e0000);
  6153. I915_WRITE(EG3, 0x68000300);
  6154. I915_WRITE(EG4, 0x42000000);
  6155. I915_WRITE(EG5, 0x00140031);
  6156. I915_WRITE(EG6, 0);
  6157. I915_WRITE(EG7, 0);
  6158. for (i = 0; i < 8; i++)
  6159. I915_WRITE(PXWL + (i * 4), 0);
  6160. /* Enable PMON + select events */
  6161. I915_WRITE(ECR, 0x80000019);
  6162. lcfuse = I915_READ(LCFUSE02);
  6163. dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
  6164. }
  6165. void gen6_enable_rps(struct drm_i915_private *dev_priv)
  6166. {
  6167. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  6168. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  6169. u32 pcu_mbox, rc6_mask = 0;
  6170. int cur_freq, min_freq, max_freq;
  6171. int i;
  6172. /* Here begins a magic sequence of register writes to enable
  6173. * auto-downclocking.
  6174. *
  6175. * Perhaps there might be some value in exposing these to
  6176. * userspace...
  6177. */
  6178. I915_WRITE(GEN6_RC_STATE, 0);
  6179. mutex_lock(&dev_priv->dev->struct_mutex);
  6180. gen6_gt_force_wake_get(dev_priv);
  6181. /* disable the counters and set deterministic thresholds */
  6182. I915_WRITE(GEN6_RC_CONTROL, 0);
  6183. I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
  6184. I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
  6185. I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
  6186. I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
  6187. I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
  6188. for (i = 0; i < I915_NUM_RINGS; i++)
  6189. I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
  6190. I915_WRITE(GEN6_RC_SLEEP, 0);
  6191. I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
  6192. I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
  6193. I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
  6194. I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
  6195. if (i915_enable_rc6)
  6196. rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
  6197. GEN6_RC_CTL_RC6_ENABLE;
  6198. I915_WRITE(GEN6_RC_CONTROL,
  6199. rc6_mask |
  6200. GEN6_RC_CTL_EI_MODE(1) |
  6201. GEN6_RC_CTL_HW_ENABLE);
  6202. I915_WRITE(GEN6_RPNSWREQ,
  6203. GEN6_FREQUENCY(10) |
  6204. GEN6_OFFSET(0) |
  6205. GEN6_AGGRESSIVE_TURBO);
  6206. I915_WRITE(GEN6_RC_VIDEO_FREQ,
  6207. GEN6_FREQUENCY(12));
  6208. I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
  6209. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
  6210. 18 << 24 |
  6211. 6 << 16);
  6212. I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
  6213. I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
  6214. I915_WRITE(GEN6_RP_UP_EI, 100000);
  6215. I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
  6216. I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
  6217. I915_WRITE(GEN6_RP_CONTROL,
  6218. GEN6_RP_MEDIA_TURBO |
  6219. GEN6_RP_USE_NORMAL_FREQ |
  6220. GEN6_RP_MEDIA_IS_GFX |
  6221. GEN6_RP_ENABLE |
  6222. GEN6_RP_UP_BUSY_AVG |
  6223. GEN6_RP_DOWN_IDLE_CONT);
  6224. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  6225. 500))
  6226. DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  6227. I915_WRITE(GEN6_PCODE_DATA, 0);
  6228. I915_WRITE(GEN6_PCODE_MAILBOX,
  6229. GEN6_PCODE_READY |
  6230. GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
  6231. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  6232. 500))
  6233. DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  6234. min_freq = (rp_state_cap & 0xff0000) >> 16;
  6235. max_freq = rp_state_cap & 0xff;
  6236. cur_freq = (gt_perf_status & 0xff00) >> 8;
  6237. /* Check for overclock support */
  6238. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  6239. 500))
  6240. DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  6241. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
  6242. pcu_mbox = I915_READ(GEN6_PCODE_DATA);
  6243. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  6244. 500))
  6245. DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  6246. if (pcu_mbox & (1<<31)) { /* OC supported */
  6247. max_freq = pcu_mbox & 0xff;
  6248. DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
  6249. }
  6250. /* In units of 100MHz */
  6251. dev_priv->max_delay = max_freq;
  6252. dev_priv->min_delay = min_freq;
  6253. dev_priv->cur_delay = cur_freq;
  6254. /* requires MSI enabled */
  6255. I915_WRITE(GEN6_PMIER,
  6256. GEN6_PM_MBOX_EVENT |
  6257. GEN6_PM_THERMAL_EVENT |
  6258. GEN6_PM_RP_DOWN_TIMEOUT |
  6259. GEN6_PM_RP_UP_THRESHOLD |
  6260. GEN6_PM_RP_DOWN_THRESHOLD |
  6261. GEN6_PM_RP_UP_EI_EXPIRED |
  6262. GEN6_PM_RP_DOWN_EI_EXPIRED);
  6263. spin_lock_irq(&dev_priv->rps_lock);
  6264. WARN_ON(dev_priv->pm_iir != 0);
  6265. I915_WRITE(GEN6_PMIMR, 0);
  6266. spin_unlock_irq(&dev_priv->rps_lock);
  6267. /* enable all PM interrupts */
  6268. I915_WRITE(GEN6_PMINTRMSK, 0);
  6269. gen6_gt_force_wake_put(dev_priv);
  6270. mutex_unlock(&dev_priv->dev->struct_mutex);
  6271. }
  6272. static void ironlake_init_clock_gating(struct drm_device *dev)
  6273. {
  6274. struct drm_i915_private *dev_priv = dev->dev_private;
  6275. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  6276. /* Required for FBC */
  6277. dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
  6278. DPFCRUNIT_CLOCK_GATE_DISABLE |
  6279. DPFDUNIT_CLOCK_GATE_DISABLE;
  6280. /* Required for CxSR */
  6281. dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
  6282. I915_WRITE(PCH_3DCGDIS0,
  6283. MARIUNIT_CLOCK_GATE_DISABLE |
  6284. SVSMUNIT_CLOCK_GATE_DISABLE);
  6285. I915_WRITE(PCH_3DCGDIS1,
  6286. VFMUNIT_CLOCK_GATE_DISABLE);
  6287. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  6288. /*
  6289. * According to the spec the following bits should be set in
  6290. * order to enable memory self-refresh
  6291. * The bit 22/21 of 0x42004
  6292. * The bit 5 of 0x42020
  6293. * The bit 15 of 0x45000
  6294. */
  6295. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  6296. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  6297. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  6298. I915_WRITE(ILK_DSPCLK_GATE,
  6299. (I915_READ(ILK_DSPCLK_GATE) |
  6300. ILK_DPARB_CLK_GATE));
  6301. I915_WRITE(DISP_ARB_CTL,
  6302. (I915_READ(DISP_ARB_CTL) |
  6303. DISP_FBC_WM_DIS));
  6304. I915_WRITE(WM3_LP_ILK, 0);
  6305. I915_WRITE(WM2_LP_ILK, 0);
  6306. I915_WRITE(WM1_LP_ILK, 0);
  6307. /*
  6308. * Based on the document from hardware guys the following bits
  6309. * should be set unconditionally in order to enable FBC.
  6310. * The bit 22 of 0x42000
  6311. * The bit 22 of 0x42004
  6312. * The bit 7,8,9 of 0x42020.
  6313. */
  6314. if (IS_IRONLAKE_M(dev)) {
  6315. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  6316. I915_READ(ILK_DISPLAY_CHICKEN1) |
  6317. ILK_FBCQ_DIS);
  6318. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  6319. I915_READ(ILK_DISPLAY_CHICKEN2) |
  6320. ILK_DPARB_GATE);
  6321. I915_WRITE(ILK_DSPCLK_GATE,
  6322. I915_READ(ILK_DSPCLK_GATE) |
  6323. ILK_DPFC_DIS1 |
  6324. ILK_DPFC_DIS2 |
  6325. ILK_CLK_FBC);
  6326. }
  6327. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  6328. I915_READ(ILK_DISPLAY_CHICKEN2) |
  6329. ILK_ELPIN_409_SELECT);
  6330. I915_WRITE(_3D_CHICKEN2,
  6331. _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
  6332. _3D_CHICKEN2_WM_READ_PIPELINED);
  6333. }
  6334. static void gen6_init_clock_gating(struct drm_device *dev)
  6335. {
  6336. struct drm_i915_private *dev_priv = dev->dev_private;
  6337. int pipe;
  6338. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  6339. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  6340. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  6341. I915_READ(ILK_DISPLAY_CHICKEN2) |
  6342. ILK_ELPIN_409_SELECT);
  6343. I915_WRITE(WM3_LP_ILK, 0);
  6344. I915_WRITE(WM2_LP_ILK, 0);
  6345. I915_WRITE(WM1_LP_ILK, 0);
  6346. /*
  6347. * According to the spec the following bits should be
  6348. * set in order to enable memory self-refresh and fbc:
  6349. * The bit21 and bit22 of 0x42000
  6350. * The bit21 and bit22 of 0x42004
  6351. * The bit5 and bit7 of 0x42020
  6352. * The bit14 of 0x70180
  6353. * The bit14 of 0x71180
  6354. */
  6355. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  6356. I915_READ(ILK_DISPLAY_CHICKEN1) |
  6357. ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
  6358. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  6359. I915_READ(ILK_DISPLAY_CHICKEN2) |
  6360. ILK_DPARB_GATE | ILK_VSDPFD_FULL);
  6361. I915_WRITE(ILK_DSPCLK_GATE,
  6362. I915_READ(ILK_DSPCLK_GATE) |
  6363. ILK_DPARB_CLK_GATE |
  6364. ILK_DPFD_CLK_GATE);
  6365. for_each_pipe(pipe) {
  6366. I915_WRITE(DSPCNTR(pipe),
  6367. I915_READ(DSPCNTR(pipe)) |
  6368. DISPPLANE_TRICKLE_FEED_DISABLE);
  6369. intel_flush_display_plane(dev_priv, pipe);
  6370. }
  6371. }
  6372. static void ivybridge_init_clock_gating(struct drm_device *dev)
  6373. {
  6374. struct drm_i915_private *dev_priv = dev->dev_private;
  6375. int pipe;
  6376. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  6377. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  6378. I915_WRITE(WM3_LP_ILK, 0);
  6379. I915_WRITE(WM2_LP_ILK, 0);
  6380. I915_WRITE(WM1_LP_ILK, 0);
  6381. I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  6382. for_each_pipe(pipe) {
  6383. I915_WRITE(DSPCNTR(pipe),
  6384. I915_READ(DSPCNTR(pipe)) |
  6385. DISPPLANE_TRICKLE_FEED_DISABLE);
  6386. intel_flush_display_plane(dev_priv, pipe);
  6387. }
  6388. }
  6389. static void g4x_init_clock_gating(struct drm_device *dev)
  6390. {
  6391. struct drm_i915_private *dev_priv = dev->dev_private;
  6392. uint32_t dspclk_gate;
  6393. I915_WRITE(RENCLK_GATE_D1, 0);
  6394. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  6395. GS_UNIT_CLOCK_GATE_DISABLE |
  6396. CL_UNIT_CLOCK_GATE_DISABLE);
  6397. I915_WRITE(RAMCLK_GATE_D, 0);
  6398. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  6399. OVRUNIT_CLOCK_GATE_DISABLE |
  6400. OVCUNIT_CLOCK_GATE_DISABLE;
  6401. if (IS_GM45(dev))
  6402. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  6403. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  6404. }
  6405. static void crestline_init_clock_gating(struct drm_device *dev)
  6406. {
  6407. struct drm_i915_private *dev_priv = dev->dev_private;
  6408. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  6409. I915_WRITE(RENCLK_GATE_D2, 0);
  6410. I915_WRITE(DSPCLK_GATE_D, 0);
  6411. I915_WRITE(RAMCLK_GATE_D, 0);
  6412. I915_WRITE16(DEUC, 0);
  6413. }
  6414. static void broadwater_init_clock_gating(struct drm_device *dev)
  6415. {
  6416. struct drm_i915_private *dev_priv = dev->dev_private;
  6417. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  6418. I965_RCC_CLOCK_GATE_DISABLE |
  6419. I965_RCPB_CLOCK_GATE_DISABLE |
  6420. I965_ISC_CLOCK_GATE_DISABLE |
  6421. I965_FBC_CLOCK_GATE_DISABLE);
  6422. I915_WRITE(RENCLK_GATE_D2, 0);
  6423. }
  6424. static void gen3_init_clock_gating(struct drm_device *dev)
  6425. {
  6426. struct drm_i915_private *dev_priv = dev->dev_private;
  6427. u32 dstate = I915_READ(D_STATE);
  6428. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  6429. DSTATE_DOT_CLOCK_GATING;
  6430. I915_WRITE(D_STATE, dstate);
  6431. }
  6432. static void i85x_init_clock_gating(struct drm_device *dev)
  6433. {
  6434. struct drm_i915_private *dev_priv = dev->dev_private;
  6435. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  6436. }
  6437. static void i830_init_clock_gating(struct drm_device *dev)
  6438. {
  6439. struct drm_i915_private *dev_priv = dev->dev_private;
  6440. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  6441. }
  6442. static void ibx_init_clock_gating(struct drm_device *dev)
  6443. {
  6444. struct drm_i915_private *dev_priv = dev->dev_private;
  6445. /*
  6446. * On Ibex Peak and Cougar Point, we need to disable clock
  6447. * gating for the panel power sequencer or it will fail to
  6448. * start up when no ports are active.
  6449. */
  6450. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  6451. }
  6452. static void cpt_init_clock_gating(struct drm_device *dev)
  6453. {
  6454. struct drm_i915_private *dev_priv = dev->dev_private;
  6455. int pipe;
  6456. /*
  6457. * On Ibex Peak and Cougar Point, we need to disable clock
  6458. * gating for the panel power sequencer or it will fail to
  6459. * start up when no ports are active.
  6460. */
  6461. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  6462. I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
  6463. DPLS_EDP_PPS_FIX_DIS);
  6464. /* Without this, mode sets may fail silently on FDI */
  6465. for_each_pipe(pipe)
  6466. I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
  6467. }
  6468. static void ironlake_teardown_rc6(struct drm_device *dev)
  6469. {
  6470. struct drm_i915_private *dev_priv = dev->dev_private;
  6471. if (dev_priv->renderctx) {
  6472. i915_gem_object_unpin(dev_priv->renderctx);
  6473. drm_gem_object_unreference(&dev_priv->renderctx->base);
  6474. dev_priv->renderctx = NULL;
  6475. }
  6476. if (dev_priv->pwrctx) {
  6477. i915_gem_object_unpin(dev_priv->pwrctx);
  6478. drm_gem_object_unreference(&dev_priv->pwrctx->base);
  6479. dev_priv->pwrctx = NULL;
  6480. }
  6481. }
  6482. static void ironlake_disable_rc6(struct drm_device *dev)
  6483. {
  6484. struct drm_i915_private *dev_priv = dev->dev_private;
  6485. if (I915_READ(PWRCTXA)) {
  6486. /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
  6487. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
  6488. wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
  6489. 50);
  6490. I915_WRITE(PWRCTXA, 0);
  6491. POSTING_READ(PWRCTXA);
  6492. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  6493. POSTING_READ(RSTDBYCTL);
  6494. }
  6495. ironlake_teardown_rc6(dev);
  6496. }
  6497. static int ironlake_setup_rc6(struct drm_device *dev)
  6498. {
  6499. struct drm_i915_private *dev_priv = dev->dev_private;
  6500. if (dev_priv->renderctx == NULL)
  6501. dev_priv->renderctx = intel_alloc_context_page(dev);
  6502. if (!dev_priv->renderctx)
  6503. return -ENOMEM;
  6504. if (dev_priv->pwrctx == NULL)
  6505. dev_priv->pwrctx = intel_alloc_context_page(dev);
  6506. if (!dev_priv->pwrctx) {
  6507. ironlake_teardown_rc6(dev);
  6508. return -ENOMEM;
  6509. }
  6510. return 0;
  6511. }
  6512. void ironlake_enable_rc6(struct drm_device *dev)
  6513. {
  6514. struct drm_i915_private *dev_priv = dev->dev_private;
  6515. int ret;
  6516. /* rc6 disabled by default due to repeated reports of hanging during
  6517. * boot and resume.
  6518. */
  6519. if (!i915_enable_rc6)
  6520. return;
  6521. mutex_lock(&dev->struct_mutex);
  6522. ret = ironlake_setup_rc6(dev);
  6523. if (ret) {
  6524. mutex_unlock(&dev->struct_mutex);
  6525. return;
  6526. }
  6527. /*
  6528. * GPU can automatically power down the render unit if given a page
  6529. * to save state.
  6530. */
  6531. ret = BEGIN_LP_RING(6);
  6532. if (ret) {
  6533. ironlake_teardown_rc6(dev);
  6534. mutex_unlock(&dev->struct_mutex);
  6535. return;
  6536. }
  6537. OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
  6538. OUT_RING(MI_SET_CONTEXT);
  6539. OUT_RING(dev_priv->renderctx->gtt_offset |
  6540. MI_MM_SPACE_GTT |
  6541. MI_SAVE_EXT_STATE_EN |
  6542. MI_RESTORE_EXT_STATE_EN |
  6543. MI_RESTORE_INHIBIT);
  6544. OUT_RING(MI_SUSPEND_FLUSH);
  6545. OUT_RING(MI_NOOP);
  6546. OUT_RING(MI_FLUSH);
  6547. ADVANCE_LP_RING();
  6548. /*
  6549. * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
  6550. * does an implicit flush, combined with MI_FLUSH above, it should be
  6551. * safe to assume that renderctx is valid
  6552. */
  6553. ret = intel_wait_ring_idle(LP_RING(dev_priv));
  6554. if (ret) {
  6555. DRM_ERROR("failed to enable ironlake power power savings\n");
  6556. ironlake_teardown_rc6(dev);
  6557. mutex_unlock(&dev->struct_mutex);
  6558. return;
  6559. }
  6560. I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
  6561. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  6562. mutex_unlock(&dev->struct_mutex);
  6563. }
  6564. void intel_init_clock_gating(struct drm_device *dev)
  6565. {
  6566. struct drm_i915_private *dev_priv = dev->dev_private;
  6567. dev_priv->display.init_clock_gating(dev);
  6568. if (dev_priv->display.init_pch_clock_gating)
  6569. dev_priv->display.init_pch_clock_gating(dev);
  6570. }
  6571. /* Set up chip specific display functions */
  6572. static void intel_init_display(struct drm_device *dev)
  6573. {
  6574. struct drm_i915_private *dev_priv = dev->dev_private;
  6575. /* We always want a DPMS function */
  6576. if (HAS_PCH_SPLIT(dev)) {
  6577. dev_priv->display.dpms = ironlake_crtc_dpms;
  6578. dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  6579. } else {
  6580. dev_priv->display.dpms = i9xx_crtc_dpms;
  6581. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  6582. }
  6583. if (I915_HAS_FBC(dev)) {
  6584. if (HAS_PCH_SPLIT(dev)) {
  6585. dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
  6586. dev_priv->display.enable_fbc = ironlake_enable_fbc;
  6587. dev_priv->display.disable_fbc = ironlake_disable_fbc;
  6588. } else if (IS_GM45(dev)) {
  6589. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  6590. dev_priv->display.enable_fbc = g4x_enable_fbc;
  6591. dev_priv->display.disable_fbc = g4x_disable_fbc;
  6592. } else if (IS_CRESTLINE(dev)) {
  6593. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  6594. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  6595. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  6596. }
  6597. /* 855GM needs testing */
  6598. }
  6599. /* Returns the core display clock speed */
  6600. if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
  6601. dev_priv->display.get_display_clock_speed =
  6602. i945_get_display_clock_speed;
  6603. else if (IS_I915G(dev))
  6604. dev_priv->display.get_display_clock_speed =
  6605. i915_get_display_clock_speed;
  6606. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  6607. dev_priv->display.get_display_clock_speed =
  6608. i9xx_misc_get_display_clock_speed;
  6609. else if (IS_I915GM(dev))
  6610. dev_priv->display.get_display_clock_speed =
  6611. i915gm_get_display_clock_speed;
  6612. else if (IS_I865G(dev))
  6613. dev_priv->display.get_display_clock_speed =
  6614. i865_get_display_clock_speed;
  6615. else if (IS_I85X(dev))
  6616. dev_priv->display.get_display_clock_speed =
  6617. i855_get_display_clock_speed;
  6618. else /* 852, 830 */
  6619. dev_priv->display.get_display_clock_speed =
  6620. i830_get_display_clock_speed;
  6621. /* For FIFO watermark updates */
  6622. if (HAS_PCH_SPLIT(dev)) {
  6623. if (HAS_PCH_IBX(dev))
  6624. dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
  6625. else if (HAS_PCH_CPT(dev))
  6626. dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
  6627. if (IS_GEN5(dev)) {
  6628. if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  6629. dev_priv->display.update_wm = ironlake_update_wm;
  6630. else {
  6631. DRM_DEBUG_KMS("Failed to get proper latency. "
  6632. "Disable CxSR\n");
  6633. dev_priv->display.update_wm = NULL;
  6634. }
  6635. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  6636. dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
  6637. } else if (IS_GEN6(dev)) {
  6638. if (SNB_READ_WM0_LATENCY()) {
  6639. dev_priv->display.update_wm = sandybridge_update_wm;
  6640. } else {
  6641. DRM_DEBUG_KMS("Failed to read display plane latency. "
  6642. "Disable CxSR\n");
  6643. dev_priv->display.update_wm = NULL;
  6644. }
  6645. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  6646. dev_priv->display.init_clock_gating = gen6_init_clock_gating;
  6647. } else if (IS_IVYBRIDGE(dev)) {
  6648. /* FIXME: detect B0+ stepping and use auto training */
  6649. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  6650. if (SNB_READ_WM0_LATENCY()) {
  6651. dev_priv->display.update_wm = sandybridge_update_wm;
  6652. } else {
  6653. DRM_DEBUG_KMS("Failed to read display plane latency. "
  6654. "Disable CxSR\n");
  6655. dev_priv->display.update_wm = NULL;
  6656. }
  6657. dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
  6658. } else
  6659. dev_priv->display.update_wm = NULL;
  6660. } else if (IS_PINEVIEW(dev)) {
  6661. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  6662. dev_priv->is_ddr3,
  6663. dev_priv->fsb_freq,
  6664. dev_priv->mem_freq)) {
  6665. DRM_INFO("failed to find known CxSR latency "
  6666. "(found ddr%s fsb freq %d, mem freq %d), "
  6667. "disabling CxSR\n",
  6668. (dev_priv->is_ddr3 == 1) ? "3": "2",
  6669. dev_priv->fsb_freq, dev_priv->mem_freq);
  6670. /* Disable CxSR and never update its watermark again */
  6671. pineview_disable_cxsr(dev);
  6672. dev_priv->display.update_wm = NULL;
  6673. } else
  6674. dev_priv->display.update_wm = pineview_update_wm;
  6675. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  6676. } else if (IS_G4X(dev)) {
  6677. dev_priv->display.update_wm = g4x_update_wm;
  6678. dev_priv->display.init_clock_gating = g4x_init_clock_gating;
  6679. } else if (IS_GEN4(dev)) {
  6680. dev_priv->display.update_wm = i965_update_wm;
  6681. if (IS_CRESTLINE(dev))
  6682. dev_priv->display.init_clock_gating = crestline_init_clock_gating;
  6683. else if (IS_BROADWATER(dev))
  6684. dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
  6685. } else if (IS_GEN3(dev)) {
  6686. dev_priv->display.update_wm = i9xx_update_wm;
  6687. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  6688. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  6689. } else if (IS_I865G(dev)) {
  6690. dev_priv->display.update_wm = i830_update_wm;
  6691. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  6692. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  6693. } else if (IS_I85X(dev)) {
  6694. dev_priv->display.update_wm = i9xx_update_wm;
  6695. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  6696. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  6697. } else {
  6698. dev_priv->display.update_wm = i830_update_wm;
  6699. dev_priv->display.init_clock_gating = i830_init_clock_gating;
  6700. if (IS_845G(dev))
  6701. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  6702. else
  6703. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  6704. }
  6705. /* Default just returns -ENODEV to indicate unsupported */
  6706. dev_priv->display.queue_flip = intel_default_queue_flip;
  6707. switch (INTEL_INFO(dev)->gen) {
  6708. case 2:
  6709. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  6710. break;
  6711. case 3:
  6712. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  6713. break;
  6714. case 4:
  6715. case 5:
  6716. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  6717. break;
  6718. case 6:
  6719. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  6720. break;
  6721. case 7:
  6722. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  6723. break;
  6724. }
  6725. }
  6726. /*
  6727. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  6728. * resume, or other times. This quirk makes sure that's the case for
  6729. * affected systems.
  6730. */
  6731. static void quirk_pipea_force (struct drm_device *dev)
  6732. {
  6733. struct drm_i915_private *dev_priv = dev->dev_private;
  6734. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  6735. DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
  6736. }
  6737. /*
  6738. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  6739. */
  6740. static void quirk_ssc_force_disable(struct drm_device *dev)
  6741. {
  6742. struct drm_i915_private *dev_priv = dev->dev_private;
  6743. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  6744. }
  6745. struct intel_quirk {
  6746. int device;
  6747. int subsystem_vendor;
  6748. int subsystem_device;
  6749. void (*hook)(struct drm_device *dev);
  6750. };
  6751. struct intel_quirk intel_quirks[] = {
  6752. /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
  6753. { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
  6754. /* HP Mini needs pipe A force quirk (LP: #322104) */
  6755. { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
  6756. /* Thinkpad R31 needs pipe A force quirk */
  6757. { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
  6758. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  6759. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  6760. /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
  6761. { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
  6762. /* ThinkPad X40 needs pipe A force quirk */
  6763. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  6764. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  6765. /* 855 & before need to leave pipe A & dpll A up */
  6766. { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  6767. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  6768. /* Lenovo U160 cannot use SSC on LVDS */
  6769. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  6770. /* Sony Vaio Y cannot use SSC on LVDS */
  6771. { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  6772. };
  6773. static void intel_init_quirks(struct drm_device *dev)
  6774. {
  6775. struct pci_dev *d = dev->pdev;
  6776. int i;
  6777. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  6778. struct intel_quirk *q = &intel_quirks[i];
  6779. if (d->device == q->device &&
  6780. (d->subsystem_vendor == q->subsystem_vendor ||
  6781. q->subsystem_vendor == PCI_ANY_ID) &&
  6782. (d->subsystem_device == q->subsystem_device ||
  6783. q->subsystem_device == PCI_ANY_ID))
  6784. q->hook(dev);
  6785. }
  6786. }
  6787. /* Disable the VGA plane that we never use */
  6788. static void i915_disable_vga(struct drm_device *dev)
  6789. {
  6790. struct drm_i915_private *dev_priv = dev->dev_private;
  6791. u8 sr1;
  6792. u32 vga_reg;
  6793. if (HAS_PCH_SPLIT(dev))
  6794. vga_reg = CPU_VGACNTRL;
  6795. else
  6796. vga_reg = VGACNTRL;
  6797. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  6798. outb(1, VGA_SR_INDEX);
  6799. sr1 = inb(VGA_SR_DATA);
  6800. outb(sr1 | 1<<5, VGA_SR_DATA);
  6801. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  6802. udelay(300);
  6803. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  6804. POSTING_READ(vga_reg);
  6805. }
  6806. void intel_modeset_init(struct drm_device *dev)
  6807. {
  6808. struct drm_i915_private *dev_priv = dev->dev_private;
  6809. int i;
  6810. drm_mode_config_init(dev);
  6811. dev->mode_config.min_width = 0;
  6812. dev->mode_config.min_height = 0;
  6813. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  6814. intel_init_quirks(dev);
  6815. intel_init_display(dev);
  6816. if (IS_GEN2(dev)) {
  6817. dev->mode_config.max_width = 2048;
  6818. dev->mode_config.max_height = 2048;
  6819. } else if (IS_GEN3(dev)) {
  6820. dev->mode_config.max_width = 4096;
  6821. dev->mode_config.max_height = 4096;
  6822. } else {
  6823. dev->mode_config.max_width = 8192;
  6824. dev->mode_config.max_height = 8192;
  6825. }
  6826. dev->mode_config.fb_base = dev->agp->base;
  6827. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  6828. dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
  6829. for (i = 0; i < dev_priv->num_pipe; i++) {
  6830. intel_crtc_init(dev, i);
  6831. }
  6832. /* Just disable it once at startup */
  6833. i915_disable_vga(dev);
  6834. intel_setup_outputs(dev);
  6835. intel_init_clock_gating(dev);
  6836. if (IS_IRONLAKE_M(dev)) {
  6837. ironlake_enable_drps(dev);
  6838. intel_init_emon(dev);
  6839. }
  6840. if (IS_GEN6(dev))
  6841. gen6_enable_rps(dev_priv);
  6842. INIT_WORK(&dev_priv->idle_work, intel_idle_update);
  6843. setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
  6844. (unsigned long)dev);
  6845. }
  6846. void intel_modeset_gem_init(struct drm_device *dev)
  6847. {
  6848. if (IS_IRONLAKE_M(dev))
  6849. ironlake_enable_rc6(dev);
  6850. intel_setup_overlay(dev);
  6851. }
  6852. void intel_modeset_cleanup(struct drm_device *dev)
  6853. {
  6854. struct drm_i915_private *dev_priv = dev->dev_private;
  6855. struct drm_crtc *crtc;
  6856. struct intel_crtc *intel_crtc;
  6857. drm_kms_helper_poll_fini(dev);
  6858. mutex_lock(&dev->struct_mutex);
  6859. intel_unregister_dsm_handler();
  6860. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6861. /* Skip inactive CRTCs */
  6862. if (!crtc->fb)
  6863. continue;
  6864. intel_crtc = to_intel_crtc(crtc);
  6865. intel_increase_pllclock(crtc);
  6866. }
  6867. if (dev_priv->display.disable_fbc)
  6868. dev_priv->display.disable_fbc(dev);
  6869. if (IS_IRONLAKE_M(dev))
  6870. ironlake_disable_drps(dev);
  6871. if (IS_GEN6(dev))
  6872. gen6_disable_rps(dev);
  6873. if (IS_IRONLAKE_M(dev))
  6874. ironlake_disable_rc6(dev);
  6875. mutex_unlock(&dev->struct_mutex);
  6876. /* Disable the irq before mode object teardown, for the irq might
  6877. * enqueue unpin/hotplug work. */
  6878. drm_irq_uninstall(dev);
  6879. cancel_work_sync(&dev_priv->hotplug_work);
  6880. /* Shut off idle work before the crtcs get freed. */
  6881. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6882. intel_crtc = to_intel_crtc(crtc);
  6883. del_timer_sync(&intel_crtc->idle_timer);
  6884. }
  6885. del_timer_sync(&dev_priv->idle_timer);
  6886. cancel_work_sync(&dev_priv->idle_work);
  6887. drm_mode_config_cleanup(dev);
  6888. }
  6889. /*
  6890. * Return which encoder is currently attached for connector.
  6891. */
  6892. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  6893. {
  6894. return &intel_attached_encoder(connector)->base;
  6895. }
  6896. void intel_connector_attach_encoder(struct intel_connector *connector,
  6897. struct intel_encoder *encoder)
  6898. {
  6899. connector->encoder = encoder;
  6900. drm_mode_connector_attach_encoder(&connector->base,
  6901. &encoder->base);
  6902. }
  6903. /*
  6904. * set vga decode state - true == enable VGA decode
  6905. */
  6906. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  6907. {
  6908. struct drm_i915_private *dev_priv = dev->dev_private;
  6909. u16 gmch_ctrl;
  6910. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  6911. if (state)
  6912. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  6913. else
  6914. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  6915. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  6916. return 0;
  6917. }
  6918. #ifdef CONFIG_DEBUG_FS
  6919. #include <linux/seq_file.h>
  6920. struct intel_display_error_state {
  6921. struct intel_cursor_error_state {
  6922. u32 control;
  6923. u32 position;
  6924. u32 base;
  6925. u32 size;
  6926. } cursor[2];
  6927. struct intel_pipe_error_state {
  6928. u32 conf;
  6929. u32 source;
  6930. u32 htotal;
  6931. u32 hblank;
  6932. u32 hsync;
  6933. u32 vtotal;
  6934. u32 vblank;
  6935. u32 vsync;
  6936. } pipe[2];
  6937. struct intel_plane_error_state {
  6938. u32 control;
  6939. u32 stride;
  6940. u32 size;
  6941. u32 pos;
  6942. u32 addr;
  6943. u32 surface;
  6944. u32 tile_offset;
  6945. } plane[2];
  6946. };
  6947. struct intel_display_error_state *
  6948. intel_display_capture_error_state(struct drm_device *dev)
  6949. {
  6950. drm_i915_private_t *dev_priv = dev->dev_private;
  6951. struct intel_display_error_state *error;
  6952. int i;
  6953. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  6954. if (error == NULL)
  6955. return NULL;
  6956. for (i = 0; i < 2; i++) {
  6957. error->cursor[i].control = I915_READ(CURCNTR(i));
  6958. error->cursor[i].position = I915_READ(CURPOS(i));
  6959. error->cursor[i].base = I915_READ(CURBASE(i));
  6960. error->plane[i].control = I915_READ(DSPCNTR(i));
  6961. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  6962. error->plane[i].size = I915_READ(DSPSIZE(i));
  6963. error->plane[i].pos= I915_READ(DSPPOS(i));
  6964. error->plane[i].addr = I915_READ(DSPADDR(i));
  6965. if (INTEL_INFO(dev)->gen >= 4) {
  6966. error->plane[i].surface = I915_READ(DSPSURF(i));
  6967. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  6968. }
  6969. error->pipe[i].conf = I915_READ(PIPECONF(i));
  6970. error->pipe[i].source = I915_READ(PIPESRC(i));
  6971. error->pipe[i].htotal = I915_READ(HTOTAL(i));
  6972. error->pipe[i].hblank = I915_READ(HBLANK(i));
  6973. error->pipe[i].hsync = I915_READ(HSYNC(i));
  6974. error->pipe[i].vtotal = I915_READ(VTOTAL(i));
  6975. error->pipe[i].vblank = I915_READ(VBLANK(i));
  6976. error->pipe[i].vsync = I915_READ(VSYNC(i));
  6977. }
  6978. return error;
  6979. }
  6980. void
  6981. intel_display_print_error_state(struct seq_file *m,
  6982. struct drm_device *dev,
  6983. struct intel_display_error_state *error)
  6984. {
  6985. int i;
  6986. for (i = 0; i < 2; i++) {
  6987. seq_printf(m, "Pipe [%d]:\n", i);
  6988. seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
  6989. seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
  6990. seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
  6991. seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
  6992. seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
  6993. seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
  6994. seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
  6995. seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
  6996. seq_printf(m, "Plane [%d]:\n", i);
  6997. seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
  6998. seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  6999. seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
  7000. seq_printf(m, " POS: %08x\n", error->plane[i].pos);
  7001. seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  7002. if (INTEL_INFO(dev)->gen >= 4) {
  7003. seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
  7004. seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  7005. }
  7006. seq_printf(m, "Cursor [%d]:\n", i);
  7007. seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  7008. seq_printf(m, " POS: %08x\n", error->cursor[i].position);
  7009. seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
  7010. }
  7011. }
  7012. #endif