exynos_hdmi.c 69 KB

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  1. /*
  2. * Copyright (C) 2011 Samsung Electronics Co.Ltd
  3. * Authors:
  4. * Seung-Woo Kim <sw0312.kim@samsung.com>
  5. * Inki Dae <inki.dae@samsung.com>
  6. * Joonyoung Shim <jy0922.shim@samsung.com>
  7. *
  8. * Based on drivers/media/video/s5p-tv/hdmi_drv.c
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. *
  15. */
  16. #include "drmP.h"
  17. #include "drm_edid.h"
  18. #include "drm_crtc_helper.h"
  19. #include "regs-hdmi.h"
  20. #include <linux/kernel.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/wait.h>
  23. #include <linux/i2c.h>
  24. #include <linux/module.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/irq.h>
  28. #include <linux/delay.h>
  29. #include <linux/pm_runtime.h>
  30. #include <linux/clk.h>
  31. #include <linux/regulator/consumer.h>
  32. #include <drm/exynos_drm.h>
  33. #include "exynos_drm_drv.h"
  34. #include "exynos_drm_hdmi.h"
  35. #include "exynos_hdmi.h"
  36. #define MAX_WIDTH 1920
  37. #define MAX_HEIGHT 1080
  38. #define get_hdmi_context(dev) platform_get_drvdata(to_platform_device(dev))
  39. struct hdmi_resources {
  40. struct clk *hdmi;
  41. struct clk *sclk_hdmi;
  42. struct clk *sclk_pixel;
  43. struct clk *sclk_hdmiphy;
  44. struct clk *hdmiphy;
  45. struct regulator_bulk_data *regul_bulk;
  46. int regul_count;
  47. };
  48. struct hdmi_context {
  49. struct device *dev;
  50. struct drm_device *drm_dev;
  51. bool hpd;
  52. bool powered;
  53. bool is_v13;
  54. bool dvi_mode;
  55. struct mutex hdmi_mutex;
  56. void __iomem *regs;
  57. unsigned int external_irq;
  58. unsigned int internal_irq;
  59. struct i2c_client *ddc_port;
  60. struct i2c_client *hdmiphy_port;
  61. /* current hdmiphy conf index */
  62. int cur_conf;
  63. struct hdmi_resources res;
  64. void *parent_ctx;
  65. void (*cfg_hpd)(bool external);
  66. int (*get_hpd)(void);
  67. };
  68. /* HDMI Version 1.3 */
  69. static const u8 hdmiphy_v13_conf27[32] = {
  70. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
  71. 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
  72. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  73. 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
  74. };
  75. static const u8 hdmiphy_v13_conf27_027[32] = {
  76. 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
  77. 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
  78. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  79. 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
  80. };
  81. static const u8 hdmiphy_v13_conf74_175[32] = {
  82. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
  83. 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
  84. 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
  85. 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
  86. };
  87. static const u8 hdmiphy_v13_conf74_25[32] = {
  88. 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
  89. 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
  90. 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
  91. 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
  92. };
  93. static const u8 hdmiphy_v13_conf148_5[32] = {
  94. 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
  95. 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
  96. 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
  97. 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
  98. };
  99. struct hdmi_v13_tg_regs {
  100. u8 cmd;
  101. u8 h_fsz_l;
  102. u8 h_fsz_h;
  103. u8 hact_st_l;
  104. u8 hact_st_h;
  105. u8 hact_sz_l;
  106. u8 hact_sz_h;
  107. u8 v_fsz_l;
  108. u8 v_fsz_h;
  109. u8 vsync_l;
  110. u8 vsync_h;
  111. u8 vsync2_l;
  112. u8 vsync2_h;
  113. u8 vact_st_l;
  114. u8 vact_st_h;
  115. u8 vact_sz_l;
  116. u8 vact_sz_h;
  117. u8 field_chg_l;
  118. u8 field_chg_h;
  119. u8 vact_st2_l;
  120. u8 vact_st2_h;
  121. u8 vsync_top_hdmi_l;
  122. u8 vsync_top_hdmi_h;
  123. u8 vsync_bot_hdmi_l;
  124. u8 vsync_bot_hdmi_h;
  125. u8 field_top_hdmi_l;
  126. u8 field_top_hdmi_h;
  127. u8 field_bot_hdmi_l;
  128. u8 field_bot_hdmi_h;
  129. };
  130. struct hdmi_v13_core_regs {
  131. u8 h_blank[2];
  132. u8 v_blank[3];
  133. u8 h_v_line[3];
  134. u8 vsync_pol[1];
  135. u8 int_pro_mode[1];
  136. u8 v_blank_f[3];
  137. u8 h_sync_gen[3];
  138. u8 v_sync_gen1[3];
  139. u8 v_sync_gen2[3];
  140. u8 v_sync_gen3[3];
  141. };
  142. struct hdmi_v13_preset_conf {
  143. struct hdmi_v13_core_regs core;
  144. struct hdmi_v13_tg_regs tg;
  145. };
  146. struct hdmi_v13_conf {
  147. int width;
  148. int height;
  149. int vrefresh;
  150. bool interlace;
  151. const u8 *hdmiphy_data;
  152. const struct hdmi_v13_preset_conf *conf;
  153. };
  154. static const struct hdmi_v13_preset_conf hdmi_v13_conf_480p = {
  155. .core = {
  156. .h_blank = {0x8a, 0x00},
  157. .v_blank = {0x0d, 0x6a, 0x01},
  158. .h_v_line = {0x0d, 0xa2, 0x35},
  159. .vsync_pol = {0x01},
  160. .int_pro_mode = {0x00},
  161. .v_blank_f = {0x00, 0x00, 0x00},
  162. .h_sync_gen = {0x0e, 0x30, 0x11},
  163. .v_sync_gen1 = {0x0f, 0x90, 0x00},
  164. /* other don't care */
  165. },
  166. .tg = {
  167. 0x00, /* cmd */
  168. 0x5a, 0x03, /* h_fsz */
  169. 0x8a, 0x00, 0xd0, 0x02, /* hact */
  170. 0x0d, 0x02, /* v_fsz */
  171. 0x01, 0x00, 0x33, 0x02, /* vsync */
  172. 0x2d, 0x00, 0xe0, 0x01, /* vact */
  173. 0x33, 0x02, /* field_chg */
  174. 0x49, 0x02, /* vact_st2 */
  175. 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
  176. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  177. },
  178. };
  179. static const struct hdmi_v13_preset_conf hdmi_v13_conf_720p60 = {
  180. .core = {
  181. .h_blank = {0x72, 0x01},
  182. .v_blank = {0xee, 0xf2, 0x00},
  183. .h_v_line = {0xee, 0x22, 0x67},
  184. .vsync_pol = {0x00},
  185. .int_pro_mode = {0x00},
  186. .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
  187. .h_sync_gen = {0x6c, 0x50, 0x02},
  188. .v_sync_gen1 = {0x0a, 0x50, 0x00},
  189. .v_sync_gen2 = {0x01, 0x10, 0x00},
  190. .v_sync_gen3 = {0x01, 0x10, 0x00},
  191. /* other don't care */
  192. },
  193. .tg = {
  194. 0x00, /* cmd */
  195. 0x72, 0x06, /* h_fsz */
  196. 0x71, 0x01, 0x01, 0x05, /* hact */
  197. 0xee, 0x02, /* v_fsz */
  198. 0x01, 0x00, 0x33, 0x02, /* vsync */
  199. 0x1e, 0x00, 0xd0, 0x02, /* vact */
  200. 0x33, 0x02, /* field_chg */
  201. 0x49, 0x02, /* vact_st2 */
  202. 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
  203. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  204. },
  205. };
  206. static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i50 = {
  207. .core = {
  208. .h_blank = {0xd0, 0x02},
  209. .v_blank = {0x32, 0xB2, 0x00},
  210. .h_v_line = {0x65, 0x04, 0xa5},
  211. .vsync_pol = {0x00},
  212. .int_pro_mode = {0x01},
  213. .v_blank_f = {0x49, 0x2A, 0x23},
  214. .h_sync_gen = {0x0E, 0xEA, 0x08},
  215. .v_sync_gen1 = {0x07, 0x20, 0x00},
  216. .v_sync_gen2 = {0x39, 0x42, 0x23},
  217. .v_sync_gen3 = {0x38, 0x87, 0x73},
  218. /* other don't care */
  219. },
  220. .tg = {
  221. 0x00, /* cmd */
  222. 0x50, 0x0A, /* h_fsz */
  223. 0xCF, 0x02, 0x81, 0x07, /* hact */
  224. 0x65, 0x04, /* v_fsz */
  225. 0x01, 0x00, 0x33, 0x02, /* vsync */
  226. 0x16, 0x00, 0x1c, 0x02, /* vact */
  227. 0x33, 0x02, /* field_chg */
  228. 0x49, 0x02, /* vact_st2 */
  229. 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
  230. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  231. },
  232. };
  233. static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p50 = {
  234. .core = {
  235. .h_blank = {0xd0, 0x02},
  236. .v_blank = {0x65, 0x6c, 0x01},
  237. .h_v_line = {0x65, 0x04, 0xa5},
  238. .vsync_pol = {0x00},
  239. .int_pro_mode = {0x00},
  240. .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
  241. .h_sync_gen = {0x0e, 0xea, 0x08},
  242. .v_sync_gen1 = {0x09, 0x40, 0x00},
  243. .v_sync_gen2 = {0x01, 0x10, 0x00},
  244. .v_sync_gen3 = {0x01, 0x10, 0x00},
  245. /* other don't care */
  246. },
  247. .tg = {
  248. 0x00, /* cmd */
  249. 0x50, 0x0A, /* h_fsz */
  250. 0xCF, 0x02, 0x81, 0x07, /* hact */
  251. 0x65, 0x04, /* v_fsz */
  252. 0x01, 0x00, 0x33, 0x02, /* vsync */
  253. 0x2d, 0x00, 0x38, 0x04, /* vact */
  254. 0x33, 0x02, /* field_chg */
  255. 0x48, 0x02, /* vact_st2 */
  256. 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
  257. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  258. },
  259. };
  260. static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i60 = {
  261. .core = {
  262. .h_blank = {0x18, 0x01},
  263. .v_blank = {0x32, 0xB2, 0x00},
  264. .h_v_line = {0x65, 0x84, 0x89},
  265. .vsync_pol = {0x00},
  266. .int_pro_mode = {0x01},
  267. .v_blank_f = {0x49, 0x2A, 0x23},
  268. .h_sync_gen = {0x56, 0x08, 0x02},
  269. .v_sync_gen1 = {0x07, 0x20, 0x00},
  270. .v_sync_gen2 = {0x39, 0x42, 0x23},
  271. .v_sync_gen3 = {0xa4, 0x44, 0x4a},
  272. /* other don't care */
  273. },
  274. .tg = {
  275. 0x00, /* cmd */
  276. 0x98, 0x08, /* h_fsz */
  277. 0x17, 0x01, 0x81, 0x07, /* hact */
  278. 0x65, 0x04, /* v_fsz */
  279. 0x01, 0x00, 0x33, 0x02, /* vsync */
  280. 0x16, 0x00, 0x1c, 0x02, /* vact */
  281. 0x33, 0x02, /* field_chg */
  282. 0x49, 0x02, /* vact_st2 */
  283. 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
  284. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  285. },
  286. };
  287. static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = {
  288. .core = {
  289. .h_blank = {0x18, 0x01},
  290. .v_blank = {0x65, 0x6c, 0x01},
  291. .h_v_line = {0x65, 0x84, 0x89},
  292. .vsync_pol = {0x00},
  293. .int_pro_mode = {0x00},
  294. .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
  295. .h_sync_gen = {0x56, 0x08, 0x02},
  296. .v_sync_gen1 = {0x09, 0x40, 0x00},
  297. .v_sync_gen2 = {0x01, 0x10, 0x00},
  298. .v_sync_gen3 = {0x01, 0x10, 0x00},
  299. /* other don't care */
  300. },
  301. .tg = {
  302. 0x00, /* cmd */
  303. 0x98, 0x08, /* h_fsz */
  304. 0x17, 0x01, 0x81, 0x07, /* hact */
  305. 0x65, 0x04, /* v_fsz */
  306. 0x01, 0x00, 0x33, 0x02, /* vsync */
  307. 0x2d, 0x00, 0x38, 0x04, /* vact */
  308. 0x33, 0x02, /* field_chg */
  309. 0x48, 0x02, /* vact_st2 */
  310. 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
  311. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  312. },
  313. };
  314. static const struct hdmi_v13_conf hdmi_v13_confs[] = {
  315. { 1280, 720, 60, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
  316. { 1280, 720, 50, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
  317. { 720, 480, 60, false, hdmiphy_v13_conf27_027, &hdmi_v13_conf_480p },
  318. { 1920, 1080, 50, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i50 },
  319. { 1920, 1080, 50, false, hdmiphy_v13_conf148_5,
  320. &hdmi_v13_conf_1080p50 },
  321. { 1920, 1080, 60, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i60 },
  322. { 1920, 1080, 60, false, hdmiphy_v13_conf148_5,
  323. &hdmi_v13_conf_1080p60 },
  324. };
  325. /* HDMI Version 1.4 */
  326. static const u8 hdmiphy_conf27_027[32] = {
  327. 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
  328. 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
  329. 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  330. 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
  331. };
  332. static const u8 hdmiphy_conf74_176[32] = {
  333. 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x5b, 0xef, 0x08,
  334. 0x81, 0xa0, 0xb9, 0xd8, 0x45, 0xa0, 0xac, 0x80,
  335. 0x5a, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  336. 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
  337. };
  338. static const u8 hdmiphy_conf74_25[32] = {
  339. 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
  340. 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
  341. 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  342. 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
  343. };
  344. static const u8 hdmiphy_conf148_5[32] = {
  345. 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
  346. 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
  347. 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
  348. 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
  349. };
  350. struct hdmi_tg_regs {
  351. u8 cmd;
  352. u8 h_fsz_l;
  353. u8 h_fsz_h;
  354. u8 hact_st_l;
  355. u8 hact_st_h;
  356. u8 hact_sz_l;
  357. u8 hact_sz_h;
  358. u8 v_fsz_l;
  359. u8 v_fsz_h;
  360. u8 vsync_l;
  361. u8 vsync_h;
  362. u8 vsync2_l;
  363. u8 vsync2_h;
  364. u8 vact_st_l;
  365. u8 vact_st_h;
  366. u8 vact_sz_l;
  367. u8 vact_sz_h;
  368. u8 field_chg_l;
  369. u8 field_chg_h;
  370. u8 vact_st2_l;
  371. u8 vact_st2_h;
  372. u8 vact_st3_l;
  373. u8 vact_st3_h;
  374. u8 vact_st4_l;
  375. u8 vact_st4_h;
  376. u8 vsync_top_hdmi_l;
  377. u8 vsync_top_hdmi_h;
  378. u8 vsync_bot_hdmi_l;
  379. u8 vsync_bot_hdmi_h;
  380. u8 field_top_hdmi_l;
  381. u8 field_top_hdmi_h;
  382. u8 field_bot_hdmi_l;
  383. u8 field_bot_hdmi_h;
  384. u8 tg_3d;
  385. };
  386. struct hdmi_core_regs {
  387. u8 h_blank[2];
  388. u8 v2_blank[2];
  389. u8 v1_blank[2];
  390. u8 v_line[2];
  391. u8 h_line[2];
  392. u8 hsync_pol[1];
  393. u8 vsync_pol[1];
  394. u8 int_pro_mode[1];
  395. u8 v_blank_f0[2];
  396. u8 v_blank_f1[2];
  397. u8 h_sync_start[2];
  398. u8 h_sync_end[2];
  399. u8 v_sync_line_bef_2[2];
  400. u8 v_sync_line_bef_1[2];
  401. u8 v_sync_line_aft_2[2];
  402. u8 v_sync_line_aft_1[2];
  403. u8 v_sync_line_aft_pxl_2[2];
  404. u8 v_sync_line_aft_pxl_1[2];
  405. u8 v_blank_f2[2]; /* for 3D mode */
  406. u8 v_blank_f3[2]; /* for 3D mode */
  407. u8 v_blank_f4[2]; /* for 3D mode */
  408. u8 v_blank_f5[2]; /* for 3D mode */
  409. u8 v_sync_line_aft_3[2];
  410. u8 v_sync_line_aft_4[2];
  411. u8 v_sync_line_aft_5[2];
  412. u8 v_sync_line_aft_6[2];
  413. u8 v_sync_line_aft_pxl_3[2];
  414. u8 v_sync_line_aft_pxl_4[2];
  415. u8 v_sync_line_aft_pxl_5[2];
  416. u8 v_sync_line_aft_pxl_6[2];
  417. u8 vact_space_1[2];
  418. u8 vact_space_2[2];
  419. u8 vact_space_3[2];
  420. u8 vact_space_4[2];
  421. u8 vact_space_5[2];
  422. u8 vact_space_6[2];
  423. };
  424. struct hdmi_preset_conf {
  425. struct hdmi_core_regs core;
  426. struct hdmi_tg_regs tg;
  427. };
  428. struct hdmi_conf {
  429. int width;
  430. int height;
  431. int vrefresh;
  432. bool interlace;
  433. const u8 *hdmiphy_data;
  434. const struct hdmi_preset_conf *conf;
  435. };
  436. static const struct hdmi_preset_conf hdmi_conf_480p60 = {
  437. .core = {
  438. .h_blank = {0x8a, 0x00},
  439. .v2_blank = {0x0d, 0x02},
  440. .v1_blank = {0x2d, 0x00},
  441. .v_line = {0x0d, 0x02},
  442. .h_line = {0x5a, 0x03},
  443. .hsync_pol = {0x01},
  444. .vsync_pol = {0x01},
  445. .int_pro_mode = {0x00},
  446. .v_blank_f0 = {0xff, 0xff},
  447. .v_blank_f1 = {0xff, 0xff},
  448. .h_sync_start = {0x0e, 0x00},
  449. .h_sync_end = {0x4c, 0x00},
  450. .v_sync_line_bef_2 = {0x0f, 0x00},
  451. .v_sync_line_bef_1 = {0x09, 0x00},
  452. .v_sync_line_aft_2 = {0xff, 0xff},
  453. .v_sync_line_aft_1 = {0xff, 0xff},
  454. .v_sync_line_aft_pxl_2 = {0xff, 0xff},
  455. .v_sync_line_aft_pxl_1 = {0xff, 0xff},
  456. .v_blank_f2 = {0xff, 0xff},
  457. .v_blank_f3 = {0xff, 0xff},
  458. .v_blank_f4 = {0xff, 0xff},
  459. .v_blank_f5 = {0xff, 0xff},
  460. .v_sync_line_aft_3 = {0xff, 0xff},
  461. .v_sync_line_aft_4 = {0xff, 0xff},
  462. .v_sync_line_aft_5 = {0xff, 0xff},
  463. .v_sync_line_aft_6 = {0xff, 0xff},
  464. .v_sync_line_aft_pxl_3 = {0xff, 0xff},
  465. .v_sync_line_aft_pxl_4 = {0xff, 0xff},
  466. .v_sync_line_aft_pxl_5 = {0xff, 0xff},
  467. .v_sync_line_aft_pxl_6 = {0xff, 0xff},
  468. .vact_space_1 = {0xff, 0xff},
  469. .vact_space_2 = {0xff, 0xff},
  470. .vact_space_3 = {0xff, 0xff},
  471. .vact_space_4 = {0xff, 0xff},
  472. .vact_space_5 = {0xff, 0xff},
  473. .vact_space_6 = {0xff, 0xff},
  474. /* other don't care */
  475. },
  476. .tg = {
  477. 0x00, /* cmd */
  478. 0x5a, 0x03, /* h_fsz */
  479. 0x8a, 0x00, 0xd0, 0x02, /* hact */
  480. 0x0d, 0x02, /* v_fsz */
  481. 0x01, 0x00, 0x33, 0x02, /* vsync */
  482. 0x2d, 0x00, 0xe0, 0x01, /* vact */
  483. 0x33, 0x02, /* field_chg */
  484. 0x48, 0x02, /* vact_st2 */
  485. 0x00, 0x00, /* vact_st3 */
  486. 0x00, 0x00, /* vact_st4 */
  487. 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
  488. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  489. 0x00, /* 3d FP */
  490. },
  491. };
  492. static const struct hdmi_preset_conf hdmi_conf_720p50 = {
  493. .core = {
  494. .h_blank = {0xbc, 0x02},
  495. .v2_blank = {0xee, 0x02},
  496. .v1_blank = {0x1e, 0x00},
  497. .v_line = {0xee, 0x02},
  498. .h_line = {0xbc, 0x07},
  499. .hsync_pol = {0x00},
  500. .vsync_pol = {0x00},
  501. .int_pro_mode = {0x00},
  502. .v_blank_f0 = {0xff, 0xff},
  503. .v_blank_f1 = {0xff, 0xff},
  504. .h_sync_start = {0xb6, 0x01},
  505. .h_sync_end = {0xde, 0x01},
  506. .v_sync_line_bef_2 = {0x0a, 0x00},
  507. .v_sync_line_bef_1 = {0x05, 0x00},
  508. .v_sync_line_aft_2 = {0xff, 0xff},
  509. .v_sync_line_aft_1 = {0xff, 0xff},
  510. .v_sync_line_aft_pxl_2 = {0xff, 0xff},
  511. .v_sync_line_aft_pxl_1 = {0xff, 0xff},
  512. .v_blank_f2 = {0xff, 0xff},
  513. .v_blank_f3 = {0xff, 0xff},
  514. .v_blank_f4 = {0xff, 0xff},
  515. .v_blank_f5 = {0xff, 0xff},
  516. .v_sync_line_aft_3 = {0xff, 0xff},
  517. .v_sync_line_aft_4 = {0xff, 0xff},
  518. .v_sync_line_aft_5 = {0xff, 0xff},
  519. .v_sync_line_aft_6 = {0xff, 0xff},
  520. .v_sync_line_aft_pxl_3 = {0xff, 0xff},
  521. .v_sync_line_aft_pxl_4 = {0xff, 0xff},
  522. .v_sync_line_aft_pxl_5 = {0xff, 0xff},
  523. .v_sync_line_aft_pxl_6 = {0xff, 0xff},
  524. .vact_space_1 = {0xff, 0xff},
  525. .vact_space_2 = {0xff, 0xff},
  526. .vact_space_3 = {0xff, 0xff},
  527. .vact_space_4 = {0xff, 0xff},
  528. .vact_space_5 = {0xff, 0xff},
  529. .vact_space_6 = {0xff, 0xff},
  530. /* other don't care */
  531. },
  532. .tg = {
  533. 0x00, /* cmd */
  534. 0xbc, 0x07, /* h_fsz */
  535. 0xbc, 0x02, 0x00, 0x05, /* hact */
  536. 0xee, 0x02, /* v_fsz */
  537. 0x01, 0x00, 0x33, 0x02, /* vsync */
  538. 0x1e, 0x00, 0xd0, 0x02, /* vact */
  539. 0x33, 0x02, /* field_chg */
  540. 0x48, 0x02, /* vact_st2 */
  541. 0x00, 0x00, /* vact_st3 */
  542. 0x00, 0x00, /* vact_st4 */
  543. 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
  544. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  545. 0x00, /* 3d FP */
  546. },
  547. };
  548. static const struct hdmi_preset_conf hdmi_conf_720p60 = {
  549. .core = {
  550. .h_blank = {0x72, 0x01},
  551. .v2_blank = {0xee, 0x02},
  552. .v1_blank = {0x1e, 0x00},
  553. .v_line = {0xee, 0x02},
  554. .h_line = {0x72, 0x06},
  555. .hsync_pol = {0x00},
  556. .vsync_pol = {0x00},
  557. .int_pro_mode = {0x00},
  558. .v_blank_f0 = {0xff, 0xff},
  559. .v_blank_f1 = {0xff, 0xff},
  560. .h_sync_start = {0x6c, 0x00},
  561. .h_sync_end = {0x94, 0x00},
  562. .v_sync_line_bef_2 = {0x0a, 0x00},
  563. .v_sync_line_bef_1 = {0x05, 0x00},
  564. .v_sync_line_aft_2 = {0xff, 0xff},
  565. .v_sync_line_aft_1 = {0xff, 0xff},
  566. .v_sync_line_aft_pxl_2 = {0xff, 0xff},
  567. .v_sync_line_aft_pxl_1 = {0xff, 0xff},
  568. .v_blank_f2 = {0xff, 0xff},
  569. .v_blank_f3 = {0xff, 0xff},
  570. .v_blank_f4 = {0xff, 0xff},
  571. .v_blank_f5 = {0xff, 0xff},
  572. .v_sync_line_aft_3 = {0xff, 0xff},
  573. .v_sync_line_aft_4 = {0xff, 0xff},
  574. .v_sync_line_aft_5 = {0xff, 0xff},
  575. .v_sync_line_aft_6 = {0xff, 0xff},
  576. .v_sync_line_aft_pxl_3 = {0xff, 0xff},
  577. .v_sync_line_aft_pxl_4 = {0xff, 0xff},
  578. .v_sync_line_aft_pxl_5 = {0xff, 0xff},
  579. .v_sync_line_aft_pxl_6 = {0xff, 0xff},
  580. .vact_space_1 = {0xff, 0xff},
  581. .vact_space_2 = {0xff, 0xff},
  582. .vact_space_3 = {0xff, 0xff},
  583. .vact_space_4 = {0xff, 0xff},
  584. .vact_space_5 = {0xff, 0xff},
  585. .vact_space_6 = {0xff, 0xff},
  586. /* other don't care */
  587. },
  588. .tg = {
  589. 0x00, /* cmd */
  590. 0x72, 0x06, /* h_fsz */
  591. 0x72, 0x01, 0x00, 0x05, /* hact */
  592. 0xee, 0x02, /* v_fsz */
  593. 0x01, 0x00, 0x33, 0x02, /* vsync */
  594. 0x1e, 0x00, 0xd0, 0x02, /* vact */
  595. 0x33, 0x02, /* field_chg */
  596. 0x48, 0x02, /* vact_st2 */
  597. 0x00, 0x00, /* vact_st3 */
  598. 0x00, 0x00, /* vact_st4 */
  599. 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
  600. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  601. 0x00, /* 3d FP */
  602. },
  603. };
  604. static const struct hdmi_preset_conf hdmi_conf_1080i50 = {
  605. .core = {
  606. .h_blank = {0xd0, 0x02},
  607. .v2_blank = {0x32, 0x02},
  608. .v1_blank = {0x16, 0x00},
  609. .v_line = {0x65, 0x04},
  610. .h_line = {0x50, 0x0a},
  611. .hsync_pol = {0x00},
  612. .vsync_pol = {0x00},
  613. .int_pro_mode = {0x01},
  614. .v_blank_f0 = {0x49, 0x02},
  615. .v_blank_f1 = {0x65, 0x04},
  616. .h_sync_start = {0x0e, 0x02},
  617. .h_sync_end = {0x3a, 0x02},
  618. .v_sync_line_bef_2 = {0x07, 0x00},
  619. .v_sync_line_bef_1 = {0x02, 0x00},
  620. .v_sync_line_aft_2 = {0x39, 0x02},
  621. .v_sync_line_aft_1 = {0x34, 0x02},
  622. .v_sync_line_aft_pxl_2 = {0x38, 0x07},
  623. .v_sync_line_aft_pxl_1 = {0x38, 0x07},
  624. .v_blank_f2 = {0xff, 0xff},
  625. .v_blank_f3 = {0xff, 0xff},
  626. .v_blank_f4 = {0xff, 0xff},
  627. .v_blank_f5 = {0xff, 0xff},
  628. .v_sync_line_aft_3 = {0xff, 0xff},
  629. .v_sync_line_aft_4 = {0xff, 0xff},
  630. .v_sync_line_aft_5 = {0xff, 0xff},
  631. .v_sync_line_aft_6 = {0xff, 0xff},
  632. .v_sync_line_aft_pxl_3 = {0xff, 0xff},
  633. .v_sync_line_aft_pxl_4 = {0xff, 0xff},
  634. .v_sync_line_aft_pxl_5 = {0xff, 0xff},
  635. .v_sync_line_aft_pxl_6 = {0xff, 0xff},
  636. .vact_space_1 = {0xff, 0xff},
  637. .vact_space_2 = {0xff, 0xff},
  638. .vact_space_3 = {0xff, 0xff},
  639. .vact_space_4 = {0xff, 0xff},
  640. .vact_space_5 = {0xff, 0xff},
  641. .vact_space_6 = {0xff, 0xff},
  642. /* other don't care */
  643. },
  644. .tg = {
  645. 0x00, /* cmd */
  646. 0x50, 0x0a, /* h_fsz */
  647. 0xd0, 0x02, 0x80, 0x07, /* hact */
  648. 0x65, 0x04, /* v_fsz */
  649. 0x01, 0x00, 0x33, 0x02, /* vsync */
  650. 0x16, 0x00, 0x1c, 0x02, /* vact */
  651. 0x33, 0x02, /* field_chg */
  652. 0x49, 0x02, /* vact_st2 */
  653. 0x00, 0x00, /* vact_st3 */
  654. 0x00, 0x00, /* vact_st4 */
  655. 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
  656. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  657. 0x00, /* 3d FP */
  658. },
  659. };
  660. static const struct hdmi_preset_conf hdmi_conf_1080i60 = {
  661. .core = {
  662. .h_blank = {0x18, 0x01},
  663. .v2_blank = {0x32, 0x02},
  664. .v1_blank = {0x16, 0x00},
  665. .v_line = {0x65, 0x04},
  666. .h_line = {0x98, 0x08},
  667. .hsync_pol = {0x00},
  668. .vsync_pol = {0x00},
  669. .int_pro_mode = {0x01},
  670. .v_blank_f0 = {0x49, 0x02},
  671. .v_blank_f1 = {0x65, 0x04},
  672. .h_sync_start = {0x56, 0x00},
  673. .h_sync_end = {0x82, 0x00},
  674. .v_sync_line_bef_2 = {0x07, 0x00},
  675. .v_sync_line_bef_1 = {0x02, 0x00},
  676. .v_sync_line_aft_2 = {0x39, 0x02},
  677. .v_sync_line_aft_1 = {0x34, 0x02},
  678. .v_sync_line_aft_pxl_2 = {0xa4, 0x04},
  679. .v_sync_line_aft_pxl_1 = {0xa4, 0x04},
  680. .v_blank_f2 = {0xff, 0xff},
  681. .v_blank_f3 = {0xff, 0xff},
  682. .v_blank_f4 = {0xff, 0xff},
  683. .v_blank_f5 = {0xff, 0xff},
  684. .v_sync_line_aft_3 = {0xff, 0xff},
  685. .v_sync_line_aft_4 = {0xff, 0xff},
  686. .v_sync_line_aft_5 = {0xff, 0xff},
  687. .v_sync_line_aft_6 = {0xff, 0xff},
  688. .v_sync_line_aft_pxl_3 = {0xff, 0xff},
  689. .v_sync_line_aft_pxl_4 = {0xff, 0xff},
  690. .v_sync_line_aft_pxl_5 = {0xff, 0xff},
  691. .v_sync_line_aft_pxl_6 = {0xff, 0xff},
  692. .vact_space_1 = {0xff, 0xff},
  693. .vact_space_2 = {0xff, 0xff},
  694. .vact_space_3 = {0xff, 0xff},
  695. .vact_space_4 = {0xff, 0xff},
  696. .vact_space_5 = {0xff, 0xff},
  697. .vact_space_6 = {0xff, 0xff},
  698. /* other don't care */
  699. },
  700. .tg = {
  701. 0x00, /* cmd */
  702. 0x98, 0x08, /* h_fsz */
  703. 0x18, 0x01, 0x80, 0x07, /* hact */
  704. 0x65, 0x04, /* v_fsz */
  705. 0x01, 0x00, 0x33, 0x02, /* vsync */
  706. 0x16, 0x00, 0x1c, 0x02, /* vact */
  707. 0x33, 0x02, /* field_chg */
  708. 0x49, 0x02, /* vact_st2 */
  709. 0x00, 0x00, /* vact_st3 */
  710. 0x00, 0x00, /* vact_st4 */
  711. 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
  712. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  713. 0x00, /* 3d FP */
  714. },
  715. };
  716. static const struct hdmi_preset_conf hdmi_conf_1080p30 = {
  717. .core = {
  718. .h_blank = {0x18, 0x01},
  719. .v2_blank = {0x65, 0x04},
  720. .v1_blank = {0x2d, 0x00},
  721. .v_line = {0x65, 0x04},
  722. .h_line = {0x98, 0x08},
  723. .hsync_pol = {0x00},
  724. .vsync_pol = {0x00},
  725. .int_pro_mode = {0x00},
  726. .v_blank_f0 = {0xff, 0xff},
  727. .v_blank_f1 = {0xff, 0xff},
  728. .h_sync_start = {0x56, 0x00},
  729. .h_sync_end = {0x82, 0x00},
  730. .v_sync_line_bef_2 = {0x09, 0x00},
  731. .v_sync_line_bef_1 = {0x04, 0x00},
  732. .v_sync_line_aft_2 = {0xff, 0xff},
  733. .v_sync_line_aft_1 = {0xff, 0xff},
  734. .v_sync_line_aft_pxl_2 = {0xff, 0xff},
  735. .v_sync_line_aft_pxl_1 = {0xff, 0xff},
  736. .v_blank_f2 = {0xff, 0xff},
  737. .v_blank_f3 = {0xff, 0xff},
  738. .v_blank_f4 = {0xff, 0xff},
  739. .v_blank_f5 = {0xff, 0xff},
  740. .v_sync_line_aft_3 = {0xff, 0xff},
  741. .v_sync_line_aft_4 = {0xff, 0xff},
  742. .v_sync_line_aft_5 = {0xff, 0xff},
  743. .v_sync_line_aft_6 = {0xff, 0xff},
  744. .v_sync_line_aft_pxl_3 = {0xff, 0xff},
  745. .v_sync_line_aft_pxl_4 = {0xff, 0xff},
  746. .v_sync_line_aft_pxl_5 = {0xff, 0xff},
  747. .v_sync_line_aft_pxl_6 = {0xff, 0xff},
  748. .vact_space_1 = {0xff, 0xff},
  749. .vact_space_2 = {0xff, 0xff},
  750. .vact_space_3 = {0xff, 0xff},
  751. .vact_space_4 = {0xff, 0xff},
  752. .vact_space_5 = {0xff, 0xff},
  753. .vact_space_6 = {0xff, 0xff},
  754. /* other don't care */
  755. },
  756. .tg = {
  757. 0x00, /* cmd */
  758. 0x98, 0x08, /* h_fsz */
  759. 0x18, 0x01, 0x80, 0x07, /* hact */
  760. 0x65, 0x04, /* v_fsz */
  761. 0x01, 0x00, 0x33, 0x02, /* vsync */
  762. 0x2d, 0x00, 0x38, 0x04, /* vact */
  763. 0x33, 0x02, /* field_chg */
  764. 0x48, 0x02, /* vact_st2 */
  765. 0x00, 0x00, /* vact_st3 */
  766. 0x00, 0x00, /* vact_st4 */
  767. 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
  768. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  769. 0x00, /* 3d FP */
  770. },
  771. };
  772. static const struct hdmi_preset_conf hdmi_conf_1080p50 = {
  773. .core = {
  774. .h_blank = {0xd0, 0x02},
  775. .v2_blank = {0x65, 0x04},
  776. .v1_blank = {0x2d, 0x00},
  777. .v_line = {0x65, 0x04},
  778. .h_line = {0x50, 0x0a},
  779. .hsync_pol = {0x00},
  780. .vsync_pol = {0x00},
  781. .int_pro_mode = {0x00},
  782. .v_blank_f0 = {0xff, 0xff},
  783. .v_blank_f1 = {0xff, 0xff},
  784. .h_sync_start = {0x0e, 0x02},
  785. .h_sync_end = {0x3a, 0x02},
  786. .v_sync_line_bef_2 = {0x09, 0x00},
  787. .v_sync_line_bef_1 = {0x04, 0x00},
  788. .v_sync_line_aft_2 = {0xff, 0xff},
  789. .v_sync_line_aft_1 = {0xff, 0xff},
  790. .v_sync_line_aft_pxl_2 = {0xff, 0xff},
  791. .v_sync_line_aft_pxl_1 = {0xff, 0xff},
  792. .v_blank_f2 = {0xff, 0xff},
  793. .v_blank_f3 = {0xff, 0xff},
  794. .v_blank_f4 = {0xff, 0xff},
  795. .v_blank_f5 = {0xff, 0xff},
  796. .v_sync_line_aft_3 = {0xff, 0xff},
  797. .v_sync_line_aft_4 = {0xff, 0xff},
  798. .v_sync_line_aft_5 = {0xff, 0xff},
  799. .v_sync_line_aft_6 = {0xff, 0xff},
  800. .v_sync_line_aft_pxl_3 = {0xff, 0xff},
  801. .v_sync_line_aft_pxl_4 = {0xff, 0xff},
  802. .v_sync_line_aft_pxl_5 = {0xff, 0xff},
  803. .v_sync_line_aft_pxl_6 = {0xff, 0xff},
  804. .vact_space_1 = {0xff, 0xff},
  805. .vact_space_2 = {0xff, 0xff},
  806. .vact_space_3 = {0xff, 0xff},
  807. .vact_space_4 = {0xff, 0xff},
  808. .vact_space_5 = {0xff, 0xff},
  809. .vact_space_6 = {0xff, 0xff},
  810. /* other don't care */
  811. },
  812. .tg = {
  813. 0x00, /* cmd */
  814. 0x50, 0x0a, /* h_fsz */
  815. 0xd0, 0x02, 0x80, 0x07, /* hact */
  816. 0x65, 0x04, /* v_fsz */
  817. 0x01, 0x00, 0x33, 0x02, /* vsync */
  818. 0x2d, 0x00, 0x38, 0x04, /* vact */
  819. 0x33, 0x02, /* field_chg */
  820. 0x48, 0x02, /* vact_st2 */
  821. 0x00, 0x00, /* vact_st3 */
  822. 0x00, 0x00, /* vact_st4 */
  823. 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
  824. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  825. 0x00, /* 3d FP */
  826. },
  827. };
  828. static const struct hdmi_preset_conf hdmi_conf_1080p60 = {
  829. .core = {
  830. .h_blank = {0x18, 0x01},
  831. .v2_blank = {0x65, 0x04},
  832. .v1_blank = {0x2d, 0x00},
  833. .v_line = {0x65, 0x04},
  834. .h_line = {0x98, 0x08},
  835. .hsync_pol = {0x00},
  836. .vsync_pol = {0x00},
  837. .int_pro_mode = {0x00},
  838. .v_blank_f0 = {0xff, 0xff},
  839. .v_blank_f1 = {0xff, 0xff},
  840. .h_sync_start = {0x56, 0x00},
  841. .h_sync_end = {0x82, 0x00},
  842. .v_sync_line_bef_2 = {0x09, 0x00},
  843. .v_sync_line_bef_1 = {0x04, 0x00},
  844. .v_sync_line_aft_2 = {0xff, 0xff},
  845. .v_sync_line_aft_1 = {0xff, 0xff},
  846. .v_sync_line_aft_pxl_2 = {0xff, 0xff},
  847. .v_sync_line_aft_pxl_1 = {0xff, 0xff},
  848. .v_blank_f2 = {0xff, 0xff},
  849. .v_blank_f3 = {0xff, 0xff},
  850. .v_blank_f4 = {0xff, 0xff},
  851. .v_blank_f5 = {0xff, 0xff},
  852. .v_sync_line_aft_3 = {0xff, 0xff},
  853. .v_sync_line_aft_4 = {0xff, 0xff},
  854. .v_sync_line_aft_5 = {0xff, 0xff},
  855. .v_sync_line_aft_6 = {0xff, 0xff},
  856. .v_sync_line_aft_pxl_3 = {0xff, 0xff},
  857. .v_sync_line_aft_pxl_4 = {0xff, 0xff},
  858. .v_sync_line_aft_pxl_5 = {0xff, 0xff},
  859. .v_sync_line_aft_pxl_6 = {0xff, 0xff},
  860. /* other don't care */
  861. },
  862. .tg = {
  863. 0x00, /* cmd */
  864. 0x98, 0x08, /* h_fsz */
  865. 0x18, 0x01, 0x80, 0x07, /* hact */
  866. 0x65, 0x04, /* v_fsz */
  867. 0x01, 0x00, 0x33, 0x02, /* vsync */
  868. 0x2d, 0x00, 0x38, 0x04, /* vact */
  869. 0x33, 0x02, /* field_chg */
  870. 0x48, 0x02, /* vact_st2 */
  871. 0x00, 0x00, /* vact_st3 */
  872. 0x00, 0x00, /* vact_st4 */
  873. 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
  874. 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  875. 0x00, /* 3d FP */
  876. },
  877. };
  878. static const struct hdmi_conf hdmi_confs[] = {
  879. { 720, 480, 60, false, hdmiphy_conf27_027, &hdmi_conf_480p60 },
  880. { 1280, 720, 50, false, hdmiphy_conf74_25, &hdmi_conf_720p50 },
  881. { 1280, 720, 60, false, hdmiphy_conf74_25, &hdmi_conf_720p60 },
  882. { 1920, 1080, 50, true, hdmiphy_conf74_25, &hdmi_conf_1080i50 },
  883. { 1920, 1080, 60, true, hdmiphy_conf74_25, &hdmi_conf_1080i60 },
  884. { 1920, 1080, 30, false, hdmiphy_conf74_176, &hdmi_conf_1080p30 },
  885. { 1920, 1080, 50, false, hdmiphy_conf148_5, &hdmi_conf_1080p50 },
  886. { 1920, 1080, 60, false, hdmiphy_conf148_5, &hdmi_conf_1080p60 },
  887. };
  888. static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
  889. {
  890. return readl(hdata->regs + reg_id);
  891. }
  892. static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
  893. u32 reg_id, u8 value)
  894. {
  895. writeb(value, hdata->regs + reg_id);
  896. }
  897. static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
  898. u32 reg_id, u32 value, u32 mask)
  899. {
  900. u32 old = readl(hdata->regs + reg_id);
  901. value = (value & mask) | (old & ~mask);
  902. writel(value, hdata->regs + reg_id);
  903. }
  904. static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
  905. {
  906. #define DUMPREG(reg_id) \
  907. DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
  908. readl(hdata->regs + reg_id))
  909. DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
  910. DUMPREG(HDMI_INTC_FLAG);
  911. DUMPREG(HDMI_INTC_CON);
  912. DUMPREG(HDMI_HPD_STATUS);
  913. DUMPREG(HDMI_V13_PHY_RSTOUT);
  914. DUMPREG(HDMI_V13_PHY_VPLL);
  915. DUMPREG(HDMI_V13_PHY_CMU);
  916. DUMPREG(HDMI_V13_CORE_RSTOUT);
  917. DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
  918. DUMPREG(HDMI_CON_0);
  919. DUMPREG(HDMI_CON_1);
  920. DUMPREG(HDMI_CON_2);
  921. DUMPREG(HDMI_SYS_STATUS);
  922. DUMPREG(HDMI_V13_PHY_STATUS);
  923. DUMPREG(HDMI_STATUS_EN);
  924. DUMPREG(HDMI_HPD);
  925. DUMPREG(HDMI_MODE_SEL);
  926. DUMPREG(HDMI_V13_HPD_GEN);
  927. DUMPREG(HDMI_V13_DC_CONTROL);
  928. DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
  929. DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
  930. DUMPREG(HDMI_H_BLANK_0);
  931. DUMPREG(HDMI_H_BLANK_1);
  932. DUMPREG(HDMI_V13_V_BLANK_0);
  933. DUMPREG(HDMI_V13_V_BLANK_1);
  934. DUMPREG(HDMI_V13_V_BLANK_2);
  935. DUMPREG(HDMI_V13_H_V_LINE_0);
  936. DUMPREG(HDMI_V13_H_V_LINE_1);
  937. DUMPREG(HDMI_V13_H_V_LINE_2);
  938. DUMPREG(HDMI_VSYNC_POL);
  939. DUMPREG(HDMI_INT_PRO_MODE);
  940. DUMPREG(HDMI_V13_V_BLANK_F_0);
  941. DUMPREG(HDMI_V13_V_BLANK_F_1);
  942. DUMPREG(HDMI_V13_V_BLANK_F_2);
  943. DUMPREG(HDMI_V13_H_SYNC_GEN_0);
  944. DUMPREG(HDMI_V13_H_SYNC_GEN_1);
  945. DUMPREG(HDMI_V13_H_SYNC_GEN_2);
  946. DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
  947. DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
  948. DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
  949. DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
  950. DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
  951. DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
  952. DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
  953. DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
  954. DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
  955. DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
  956. DUMPREG(HDMI_TG_CMD);
  957. DUMPREG(HDMI_TG_H_FSZ_L);
  958. DUMPREG(HDMI_TG_H_FSZ_H);
  959. DUMPREG(HDMI_TG_HACT_ST_L);
  960. DUMPREG(HDMI_TG_HACT_ST_H);
  961. DUMPREG(HDMI_TG_HACT_SZ_L);
  962. DUMPREG(HDMI_TG_HACT_SZ_H);
  963. DUMPREG(HDMI_TG_V_FSZ_L);
  964. DUMPREG(HDMI_TG_V_FSZ_H);
  965. DUMPREG(HDMI_TG_VSYNC_L);
  966. DUMPREG(HDMI_TG_VSYNC_H);
  967. DUMPREG(HDMI_TG_VSYNC2_L);
  968. DUMPREG(HDMI_TG_VSYNC2_H);
  969. DUMPREG(HDMI_TG_VACT_ST_L);
  970. DUMPREG(HDMI_TG_VACT_ST_H);
  971. DUMPREG(HDMI_TG_VACT_SZ_L);
  972. DUMPREG(HDMI_TG_VACT_SZ_H);
  973. DUMPREG(HDMI_TG_FIELD_CHG_L);
  974. DUMPREG(HDMI_TG_FIELD_CHG_H);
  975. DUMPREG(HDMI_TG_VACT_ST2_L);
  976. DUMPREG(HDMI_TG_VACT_ST2_H);
  977. DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
  978. DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
  979. DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
  980. DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
  981. DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
  982. DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
  983. DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
  984. DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
  985. #undef DUMPREG
  986. }
  987. static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
  988. {
  989. int i;
  990. #define DUMPREG(reg_id) \
  991. DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
  992. readl(hdata->regs + reg_id))
  993. DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
  994. DUMPREG(HDMI_INTC_CON);
  995. DUMPREG(HDMI_INTC_FLAG);
  996. DUMPREG(HDMI_HPD_STATUS);
  997. DUMPREG(HDMI_INTC_CON_1);
  998. DUMPREG(HDMI_INTC_FLAG_1);
  999. DUMPREG(HDMI_PHY_STATUS_0);
  1000. DUMPREG(HDMI_PHY_STATUS_PLL);
  1001. DUMPREG(HDMI_PHY_CON_0);
  1002. DUMPREG(HDMI_PHY_RSTOUT);
  1003. DUMPREG(HDMI_PHY_VPLL);
  1004. DUMPREG(HDMI_PHY_CMU);
  1005. DUMPREG(HDMI_CORE_RSTOUT);
  1006. DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
  1007. DUMPREG(HDMI_CON_0);
  1008. DUMPREG(HDMI_CON_1);
  1009. DUMPREG(HDMI_CON_2);
  1010. DUMPREG(HDMI_SYS_STATUS);
  1011. DUMPREG(HDMI_PHY_STATUS_0);
  1012. DUMPREG(HDMI_STATUS_EN);
  1013. DUMPREG(HDMI_HPD);
  1014. DUMPREG(HDMI_MODE_SEL);
  1015. DUMPREG(HDMI_ENC_EN);
  1016. DUMPREG(HDMI_DC_CONTROL);
  1017. DUMPREG(HDMI_VIDEO_PATTERN_GEN);
  1018. DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
  1019. DUMPREG(HDMI_H_BLANK_0);
  1020. DUMPREG(HDMI_H_BLANK_1);
  1021. DUMPREG(HDMI_V2_BLANK_0);
  1022. DUMPREG(HDMI_V2_BLANK_1);
  1023. DUMPREG(HDMI_V1_BLANK_0);
  1024. DUMPREG(HDMI_V1_BLANK_1);
  1025. DUMPREG(HDMI_V_LINE_0);
  1026. DUMPREG(HDMI_V_LINE_1);
  1027. DUMPREG(HDMI_H_LINE_0);
  1028. DUMPREG(HDMI_H_LINE_1);
  1029. DUMPREG(HDMI_HSYNC_POL);
  1030. DUMPREG(HDMI_VSYNC_POL);
  1031. DUMPREG(HDMI_INT_PRO_MODE);
  1032. DUMPREG(HDMI_V_BLANK_F0_0);
  1033. DUMPREG(HDMI_V_BLANK_F0_1);
  1034. DUMPREG(HDMI_V_BLANK_F1_0);
  1035. DUMPREG(HDMI_V_BLANK_F1_1);
  1036. DUMPREG(HDMI_H_SYNC_START_0);
  1037. DUMPREG(HDMI_H_SYNC_START_1);
  1038. DUMPREG(HDMI_H_SYNC_END_0);
  1039. DUMPREG(HDMI_H_SYNC_END_1);
  1040. DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
  1041. DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
  1042. DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
  1043. DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
  1044. DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
  1045. DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
  1046. DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
  1047. DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
  1048. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
  1049. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
  1050. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
  1051. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
  1052. DUMPREG(HDMI_V_BLANK_F2_0);
  1053. DUMPREG(HDMI_V_BLANK_F2_1);
  1054. DUMPREG(HDMI_V_BLANK_F3_0);
  1055. DUMPREG(HDMI_V_BLANK_F3_1);
  1056. DUMPREG(HDMI_V_BLANK_F4_0);
  1057. DUMPREG(HDMI_V_BLANK_F4_1);
  1058. DUMPREG(HDMI_V_BLANK_F5_0);
  1059. DUMPREG(HDMI_V_BLANK_F5_1);
  1060. DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
  1061. DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
  1062. DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
  1063. DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
  1064. DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
  1065. DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
  1066. DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
  1067. DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
  1068. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
  1069. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
  1070. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
  1071. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
  1072. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
  1073. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
  1074. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
  1075. DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
  1076. DUMPREG(HDMI_VACT_SPACE_1_0);
  1077. DUMPREG(HDMI_VACT_SPACE_1_1);
  1078. DUMPREG(HDMI_VACT_SPACE_2_0);
  1079. DUMPREG(HDMI_VACT_SPACE_2_1);
  1080. DUMPREG(HDMI_VACT_SPACE_3_0);
  1081. DUMPREG(HDMI_VACT_SPACE_3_1);
  1082. DUMPREG(HDMI_VACT_SPACE_4_0);
  1083. DUMPREG(HDMI_VACT_SPACE_4_1);
  1084. DUMPREG(HDMI_VACT_SPACE_5_0);
  1085. DUMPREG(HDMI_VACT_SPACE_5_1);
  1086. DUMPREG(HDMI_VACT_SPACE_6_0);
  1087. DUMPREG(HDMI_VACT_SPACE_6_1);
  1088. DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
  1089. DUMPREG(HDMI_TG_CMD);
  1090. DUMPREG(HDMI_TG_H_FSZ_L);
  1091. DUMPREG(HDMI_TG_H_FSZ_H);
  1092. DUMPREG(HDMI_TG_HACT_ST_L);
  1093. DUMPREG(HDMI_TG_HACT_ST_H);
  1094. DUMPREG(HDMI_TG_HACT_SZ_L);
  1095. DUMPREG(HDMI_TG_HACT_SZ_H);
  1096. DUMPREG(HDMI_TG_V_FSZ_L);
  1097. DUMPREG(HDMI_TG_V_FSZ_H);
  1098. DUMPREG(HDMI_TG_VSYNC_L);
  1099. DUMPREG(HDMI_TG_VSYNC_H);
  1100. DUMPREG(HDMI_TG_VSYNC2_L);
  1101. DUMPREG(HDMI_TG_VSYNC2_H);
  1102. DUMPREG(HDMI_TG_VACT_ST_L);
  1103. DUMPREG(HDMI_TG_VACT_ST_H);
  1104. DUMPREG(HDMI_TG_VACT_SZ_L);
  1105. DUMPREG(HDMI_TG_VACT_SZ_H);
  1106. DUMPREG(HDMI_TG_FIELD_CHG_L);
  1107. DUMPREG(HDMI_TG_FIELD_CHG_H);
  1108. DUMPREG(HDMI_TG_VACT_ST2_L);
  1109. DUMPREG(HDMI_TG_VACT_ST2_H);
  1110. DUMPREG(HDMI_TG_VACT_ST3_L);
  1111. DUMPREG(HDMI_TG_VACT_ST3_H);
  1112. DUMPREG(HDMI_TG_VACT_ST4_L);
  1113. DUMPREG(HDMI_TG_VACT_ST4_H);
  1114. DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
  1115. DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
  1116. DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
  1117. DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
  1118. DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
  1119. DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
  1120. DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
  1121. DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
  1122. DUMPREG(HDMI_TG_3D);
  1123. DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
  1124. DUMPREG(HDMI_AVI_CON);
  1125. DUMPREG(HDMI_AVI_HEADER0);
  1126. DUMPREG(HDMI_AVI_HEADER1);
  1127. DUMPREG(HDMI_AVI_HEADER2);
  1128. DUMPREG(HDMI_AVI_CHECK_SUM);
  1129. DUMPREG(HDMI_VSI_CON);
  1130. DUMPREG(HDMI_VSI_HEADER0);
  1131. DUMPREG(HDMI_VSI_HEADER1);
  1132. DUMPREG(HDMI_VSI_HEADER2);
  1133. for (i = 0; i < 7; ++i)
  1134. DUMPREG(HDMI_VSI_DATA(i));
  1135. #undef DUMPREG
  1136. }
  1137. static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
  1138. {
  1139. if (hdata->is_v13)
  1140. hdmi_v13_regs_dump(hdata, prefix);
  1141. else
  1142. hdmi_v14_regs_dump(hdata, prefix);
  1143. }
  1144. static int hdmi_v13_conf_index(struct drm_display_mode *mode)
  1145. {
  1146. int i;
  1147. for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
  1148. if (hdmi_v13_confs[i].width == mode->hdisplay &&
  1149. hdmi_v13_confs[i].height == mode->vdisplay &&
  1150. hdmi_v13_confs[i].vrefresh == mode->vrefresh &&
  1151. hdmi_v13_confs[i].interlace ==
  1152. ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
  1153. true : false))
  1154. return i;
  1155. return -EINVAL;
  1156. }
  1157. static int hdmi_v14_conf_index(struct drm_display_mode *mode)
  1158. {
  1159. int i;
  1160. for (i = 0; i < ARRAY_SIZE(hdmi_confs); ++i)
  1161. if (hdmi_confs[i].width == mode->hdisplay &&
  1162. hdmi_confs[i].height == mode->vdisplay &&
  1163. hdmi_confs[i].vrefresh == mode->vrefresh &&
  1164. hdmi_confs[i].interlace ==
  1165. ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
  1166. true : false))
  1167. return i;
  1168. return -EINVAL;
  1169. }
  1170. static int hdmi_conf_index(struct hdmi_context *hdata,
  1171. struct drm_display_mode *mode)
  1172. {
  1173. if (hdata->is_v13)
  1174. return hdmi_v13_conf_index(mode);
  1175. return hdmi_v14_conf_index(mode);
  1176. }
  1177. static bool hdmi_is_connected(void *ctx)
  1178. {
  1179. struct hdmi_context *hdata = ctx;
  1180. return hdata->hpd;
  1181. }
  1182. static int hdmi_get_edid(void *ctx, struct drm_connector *connector,
  1183. u8 *edid, int len)
  1184. {
  1185. struct edid *raw_edid;
  1186. struct hdmi_context *hdata = ctx;
  1187. DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
  1188. if (!hdata->ddc_port)
  1189. return -ENODEV;
  1190. raw_edid = drm_get_edid(connector, hdata->ddc_port->adapter);
  1191. if (raw_edid) {
  1192. hdata->dvi_mode = !drm_detect_hdmi_monitor(raw_edid);
  1193. memcpy(edid, raw_edid, min((1 + raw_edid->extensions)
  1194. * EDID_LENGTH, len));
  1195. DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
  1196. (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
  1197. raw_edid->width_cm, raw_edid->height_cm);
  1198. } else {
  1199. return -ENODEV;
  1200. }
  1201. return 0;
  1202. }
  1203. static int hdmi_v13_check_timing(struct fb_videomode *check_timing)
  1204. {
  1205. int i;
  1206. DRM_DEBUG_KMS("valid mode : xres=%d, yres=%d, refresh=%d, intl=%d\n",
  1207. check_timing->xres, check_timing->yres,
  1208. check_timing->refresh, (check_timing->vmode &
  1209. FB_VMODE_INTERLACED) ? true : false);
  1210. for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
  1211. if (hdmi_v13_confs[i].width == check_timing->xres &&
  1212. hdmi_v13_confs[i].height == check_timing->yres &&
  1213. hdmi_v13_confs[i].vrefresh == check_timing->refresh &&
  1214. hdmi_v13_confs[i].interlace ==
  1215. ((check_timing->vmode & FB_VMODE_INTERLACED) ?
  1216. true : false))
  1217. return 0;
  1218. /* TODO */
  1219. return -EINVAL;
  1220. }
  1221. static int hdmi_v14_check_timing(struct fb_videomode *check_timing)
  1222. {
  1223. int i;
  1224. DRM_DEBUG_KMS("valid mode : xres=%d, yres=%d, refresh=%d, intl=%d\n",
  1225. check_timing->xres, check_timing->yres,
  1226. check_timing->refresh, (check_timing->vmode &
  1227. FB_VMODE_INTERLACED) ? true : false);
  1228. for (i = 0; i < ARRAY_SIZE(hdmi_confs); i++)
  1229. if (hdmi_confs[i].width == check_timing->xres &&
  1230. hdmi_confs[i].height == check_timing->yres &&
  1231. hdmi_confs[i].vrefresh == check_timing->refresh &&
  1232. hdmi_confs[i].interlace ==
  1233. ((check_timing->vmode & FB_VMODE_INTERLACED) ?
  1234. true : false))
  1235. return 0;
  1236. /* TODO */
  1237. return -EINVAL;
  1238. }
  1239. static int hdmi_check_timing(void *ctx, void *timing)
  1240. {
  1241. struct hdmi_context *hdata = ctx;
  1242. struct fb_videomode *check_timing = timing;
  1243. DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
  1244. DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", check_timing->xres,
  1245. check_timing->yres, check_timing->refresh,
  1246. check_timing->vmode);
  1247. if (hdata->is_v13)
  1248. return hdmi_v13_check_timing(check_timing);
  1249. else
  1250. return hdmi_v14_check_timing(check_timing);
  1251. }
  1252. static void hdmi_set_acr(u32 freq, u8 *acr)
  1253. {
  1254. u32 n, cts;
  1255. switch (freq) {
  1256. case 32000:
  1257. n = 4096;
  1258. cts = 27000;
  1259. break;
  1260. case 44100:
  1261. n = 6272;
  1262. cts = 30000;
  1263. break;
  1264. case 88200:
  1265. n = 12544;
  1266. cts = 30000;
  1267. break;
  1268. case 176400:
  1269. n = 25088;
  1270. cts = 30000;
  1271. break;
  1272. case 48000:
  1273. n = 6144;
  1274. cts = 27000;
  1275. break;
  1276. case 96000:
  1277. n = 12288;
  1278. cts = 27000;
  1279. break;
  1280. case 192000:
  1281. n = 24576;
  1282. cts = 27000;
  1283. break;
  1284. default:
  1285. n = 0;
  1286. cts = 0;
  1287. break;
  1288. }
  1289. acr[1] = cts >> 16;
  1290. acr[2] = cts >> 8 & 0xff;
  1291. acr[3] = cts & 0xff;
  1292. acr[4] = n >> 16;
  1293. acr[5] = n >> 8 & 0xff;
  1294. acr[6] = n & 0xff;
  1295. }
  1296. static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
  1297. {
  1298. hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
  1299. hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
  1300. hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
  1301. hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
  1302. hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
  1303. hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
  1304. hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
  1305. hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
  1306. hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
  1307. if (hdata->is_v13)
  1308. hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
  1309. else
  1310. hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
  1311. }
  1312. static void hdmi_audio_init(struct hdmi_context *hdata)
  1313. {
  1314. u32 sample_rate, bits_per_sample, frame_size_code;
  1315. u32 data_num, bit_ch, sample_frq;
  1316. u32 val;
  1317. u8 acr[7];
  1318. sample_rate = 44100;
  1319. bits_per_sample = 16;
  1320. frame_size_code = 0;
  1321. switch (bits_per_sample) {
  1322. case 20:
  1323. data_num = 2;
  1324. bit_ch = 1;
  1325. break;
  1326. case 24:
  1327. data_num = 3;
  1328. bit_ch = 1;
  1329. break;
  1330. default:
  1331. data_num = 1;
  1332. bit_ch = 0;
  1333. break;
  1334. }
  1335. hdmi_set_acr(sample_rate, acr);
  1336. hdmi_reg_acr(hdata, acr);
  1337. hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
  1338. | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
  1339. | HDMI_I2S_MUX_ENABLE);
  1340. hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
  1341. | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
  1342. hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
  1343. sample_frq = (sample_rate == 44100) ? 0 :
  1344. (sample_rate == 48000) ? 2 :
  1345. (sample_rate == 32000) ? 3 :
  1346. (sample_rate == 96000) ? 0xa : 0x0;
  1347. hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
  1348. hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
  1349. val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
  1350. hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
  1351. /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
  1352. hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
  1353. | HDMI_I2S_SEL_LRCK(6));
  1354. hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
  1355. | HDMI_I2S_SEL_SDATA2(4));
  1356. hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
  1357. | HDMI_I2S_SEL_SDATA2(2));
  1358. hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
  1359. /* I2S_CON_1 & 2 */
  1360. hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
  1361. | HDMI_I2S_L_CH_LOW_POL);
  1362. hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
  1363. | HDMI_I2S_SET_BIT_CH(bit_ch)
  1364. | HDMI_I2S_SET_SDATA_BIT(data_num)
  1365. | HDMI_I2S_BASIC_FORMAT);
  1366. /* Configure register related to CUV information */
  1367. hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
  1368. | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
  1369. | HDMI_I2S_COPYRIGHT
  1370. | HDMI_I2S_LINEAR_PCM
  1371. | HDMI_I2S_CONSUMER_FORMAT);
  1372. hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
  1373. hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
  1374. hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
  1375. | HDMI_I2S_SET_SMP_FREQ(sample_frq));
  1376. hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
  1377. HDMI_I2S_ORG_SMP_FREQ_44_1
  1378. | HDMI_I2S_WORD_LEN_MAX24_24BITS
  1379. | HDMI_I2S_WORD_LEN_MAX_24BITS);
  1380. hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
  1381. }
  1382. static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
  1383. {
  1384. if (hdata->dvi_mode)
  1385. return;
  1386. hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
  1387. hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
  1388. HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
  1389. }
  1390. static void hdmi_conf_reset(struct hdmi_context *hdata)
  1391. {
  1392. u32 reg;
  1393. if (hdata->is_v13)
  1394. reg = HDMI_V13_CORE_RSTOUT;
  1395. else
  1396. reg = HDMI_CORE_RSTOUT;
  1397. /* resetting HDMI core */
  1398. hdmi_reg_writemask(hdata, reg, 0, HDMI_CORE_SW_RSTOUT);
  1399. mdelay(10);
  1400. hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
  1401. mdelay(10);
  1402. }
  1403. static void hdmi_conf_init(struct hdmi_context *hdata)
  1404. {
  1405. /* enable HPD interrupts */
  1406. hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
  1407. HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
  1408. mdelay(10);
  1409. hdmi_reg_writemask(hdata, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
  1410. HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
  1411. /* choose HDMI mode */
  1412. hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
  1413. HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
  1414. /* disable bluescreen */
  1415. hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
  1416. if (hdata->dvi_mode) {
  1417. /* choose DVI mode */
  1418. hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
  1419. HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
  1420. hdmi_reg_writeb(hdata, HDMI_CON_2,
  1421. HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
  1422. }
  1423. if (hdata->is_v13) {
  1424. /* choose bluescreen (fecal) color */
  1425. hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
  1426. hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
  1427. hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
  1428. /* enable AVI packet every vsync, fixes purple line problem */
  1429. hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
  1430. /* force RGB, look to CEA-861-D, table 7 for more detail */
  1431. hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
  1432. hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
  1433. hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
  1434. hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
  1435. hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
  1436. } else {
  1437. /* enable AVI packet every vsync, fixes purple line problem */
  1438. hdmi_reg_writeb(hdata, HDMI_AVI_CON, 0x02);
  1439. hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 2 << 5);
  1440. hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
  1441. }
  1442. }
  1443. static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
  1444. {
  1445. const struct hdmi_v13_preset_conf *conf =
  1446. hdmi_v13_confs[hdata->cur_conf].conf;
  1447. const struct hdmi_v13_core_regs *core = &conf->core;
  1448. const struct hdmi_v13_tg_regs *tg = &conf->tg;
  1449. int tries;
  1450. /* setting core registers */
  1451. hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
  1452. hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
  1453. hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
  1454. hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
  1455. hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
  1456. hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
  1457. hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
  1458. hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
  1459. hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
  1460. hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
  1461. hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
  1462. hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
  1463. hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
  1464. hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
  1465. hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
  1466. hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
  1467. hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
  1468. hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
  1469. hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
  1470. hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
  1471. hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
  1472. hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
  1473. hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
  1474. hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
  1475. hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
  1476. /* Timing generator registers */
  1477. hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
  1478. hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
  1479. hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l);
  1480. hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h);
  1481. hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
  1482. hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
  1483. hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
  1484. hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
  1485. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l);
  1486. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h);
  1487. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l);
  1488. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h);
  1489. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l);
  1490. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h);
  1491. hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
  1492. hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
  1493. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
  1494. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
  1495. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
  1496. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
  1497. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
  1498. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
  1499. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
  1500. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
  1501. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
  1502. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
  1503. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
  1504. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
  1505. /* waiting for HDMIPHY's PLL to get to steady state */
  1506. for (tries = 100; tries; --tries) {
  1507. u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
  1508. if (val & HDMI_PHY_STATUS_READY)
  1509. break;
  1510. mdelay(1);
  1511. }
  1512. /* steady state not achieved */
  1513. if (tries == 0) {
  1514. DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
  1515. hdmi_regs_dump(hdata, "timing apply");
  1516. }
  1517. clk_disable(hdata->res.sclk_hdmi);
  1518. clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
  1519. clk_enable(hdata->res.sclk_hdmi);
  1520. /* enable HDMI and timing generator */
  1521. hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
  1522. if (core->int_pro_mode[0])
  1523. hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
  1524. HDMI_FIELD_EN);
  1525. else
  1526. hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
  1527. }
  1528. static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
  1529. {
  1530. const struct hdmi_preset_conf *conf = hdmi_confs[hdata->cur_conf].conf;
  1531. const struct hdmi_core_regs *core = &conf->core;
  1532. const struct hdmi_tg_regs *tg = &conf->tg;
  1533. int tries;
  1534. /* setting core registers */
  1535. hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
  1536. hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
  1537. hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
  1538. hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
  1539. hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
  1540. hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
  1541. hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
  1542. hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
  1543. hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
  1544. hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
  1545. hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
  1546. hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
  1547. hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
  1548. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
  1549. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
  1550. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
  1551. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
  1552. hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
  1553. hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
  1554. hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
  1555. hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
  1556. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
  1557. core->v_sync_line_bef_2[0]);
  1558. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
  1559. core->v_sync_line_bef_2[1]);
  1560. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
  1561. core->v_sync_line_bef_1[0]);
  1562. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
  1563. core->v_sync_line_bef_1[1]);
  1564. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
  1565. core->v_sync_line_aft_2[0]);
  1566. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
  1567. core->v_sync_line_aft_2[1]);
  1568. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
  1569. core->v_sync_line_aft_1[0]);
  1570. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
  1571. core->v_sync_line_aft_1[1]);
  1572. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
  1573. core->v_sync_line_aft_pxl_2[0]);
  1574. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
  1575. core->v_sync_line_aft_pxl_2[1]);
  1576. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
  1577. core->v_sync_line_aft_pxl_1[0]);
  1578. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
  1579. core->v_sync_line_aft_pxl_1[1]);
  1580. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
  1581. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
  1582. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
  1583. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
  1584. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
  1585. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
  1586. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
  1587. hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
  1588. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
  1589. core->v_sync_line_aft_3[0]);
  1590. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
  1591. core->v_sync_line_aft_3[1]);
  1592. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
  1593. core->v_sync_line_aft_4[0]);
  1594. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
  1595. core->v_sync_line_aft_4[1]);
  1596. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
  1597. core->v_sync_line_aft_5[0]);
  1598. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
  1599. core->v_sync_line_aft_5[1]);
  1600. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
  1601. core->v_sync_line_aft_6[0]);
  1602. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
  1603. core->v_sync_line_aft_6[1]);
  1604. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
  1605. core->v_sync_line_aft_pxl_3[0]);
  1606. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
  1607. core->v_sync_line_aft_pxl_3[1]);
  1608. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
  1609. core->v_sync_line_aft_pxl_4[0]);
  1610. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
  1611. core->v_sync_line_aft_pxl_4[1]);
  1612. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
  1613. core->v_sync_line_aft_pxl_5[0]);
  1614. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
  1615. core->v_sync_line_aft_pxl_5[1]);
  1616. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
  1617. core->v_sync_line_aft_pxl_6[0]);
  1618. hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
  1619. core->v_sync_line_aft_pxl_6[1]);
  1620. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
  1621. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
  1622. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
  1623. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
  1624. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
  1625. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
  1626. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
  1627. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
  1628. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
  1629. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
  1630. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
  1631. hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
  1632. /* Timing generator registers */
  1633. hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
  1634. hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
  1635. hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l);
  1636. hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h);
  1637. hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
  1638. hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
  1639. hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
  1640. hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
  1641. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l);
  1642. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h);
  1643. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l);
  1644. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h);
  1645. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l);
  1646. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h);
  1647. hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
  1648. hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
  1649. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
  1650. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
  1651. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
  1652. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
  1653. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3_l);
  1654. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3_h);
  1655. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4_l);
  1656. hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4_h);
  1657. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
  1658. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
  1659. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
  1660. hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
  1661. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
  1662. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
  1663. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
  1664. hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
  1665. hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d);
  1666. /* waiting for HDMIPHY's PLL to get to steady state */
  1667. for (tries = 100; tries; --tries) {
  1668. u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
  1669. if (val & HDMI_PHY_STATUS_READY)
  1670. break;
  1671. mdelay(1);
  1672. }
  1673. /* steady state not achieved */
  1674. if (tries == 0) {
  1675. DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
  1676. hdmi_regs_dump(hdata, "timing apply");
  1677. }
  1678. clk_disable(hdata->res.sclk_hdmi);
  1679. clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
  1680. clk_enable(hdata->res.sclk_hdmi);
  1681. /* enable HDMI and timing generator */
  1682. hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
  1683. if (core->int_pro_mode[0])
  1684. hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
  1685. HDMI_FIELD_EN);
  1686. else
  1687. hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
  1688. }
  1689. static void hdmi_timing_apply(struct hdmi_context *hdata)
  1690. {
  1691. if (hdata->is_v13)
  1692. hdmi_v13_timing_apply(hdata);
  1693. else
  1694. hdmi_v14_timing_apply(hdata);
  1695. }
  1696. static void hdmiphy_conf_reset(struct hdmi_context *hdata)
  1697. {
  1698. u8 buffer[2];
  1699. u32 reg;
  1700. clk_disable(hdata->res.sclk_hdmi);
  1701. clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
  1702. clk_enable(hdata->res.sclk_hdmi);
  1703. /* operation mode */
  1704. buffer[0] = 0x1f;
  1705. buffer[1] = 0x00;
  1706. if (hdata->hdmiphy_port)
  1707. i2c_master_send(hdata->hdmiphy_port, buffer, 2);
  1708. if (hdata->is_v13)
  1709. reg = HDMI_V13_PHY_RSTOUT;
  1710. else
  1711. reg = HDMI_PHY_RSTOUT;
  1712. /* reset hdmiphy */
  1713. hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
  1714. mdelay(10);
  1715. hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT);
  1716. mdelay(10);
  1717. }
  1718. static void hdmiphy_conf_apply(struct hdmi_context *hdata)
  1719. {
  1720. const u8 *hdmiphy_data;
  1721. u8 buffer[32];
  1722. u8 operation[2];
  1723. u8 read_buffer[32] = {0, };
  1724. int ret;
  1725. int i;
  1726. if (!hdata->hdmiphy_port) {
  1727. DRM_ERROR("hdmiphy is not attached\n");
  1728. return;
  1729. }
  1730. /* pixel clock */
  1731. if (hdata->is_v13)
  1732. hdmiphy_data = hdmi_v13_confs[hdata->cur_conf].hdmiphy_data;
  1733. else
  1734. hdmiphy_data = hdmi_confs[hdata->cur_conf].hdmiphy_data;
  1735. memcpy(buffer, hdmiphy_data, 32);
  1736. ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
  1737. if (ret != 32) {
  1738. DRM_ERROR("failed to configure HDMIPHY via I2C\n");
  1739. return;
  1740. }
  1741. mdelay(10);
  1742. /* operation mode */
  1743. operation[0] = 0x1f;
  1744. operation[1] = 0x80;
  1745. ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
  1746. if (ret != 2) {
  1747. DRM_ERROR("failed to enable hdmiphy\n");
  1748. return;
  1749. }
  1750. ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
  1751. if (ret < 0) {
  1752. DRM_ERROR("failed to read hdmiphy config\n");
  1753. return;
  1754. }
  1755. for (i = 0; i < ret; i++)
  1756. DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
  1757. "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
  1758. }
  1759. static void hdmi_conf_apply(struct hdmi_context *hdata)
  1760. {
  1761. DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
  1762. hdmiphy_conf_reset(hdata);
  1763. hdmiphy_conf_apply(hdata);
  1764. mutex_lock(&hdata->hdmi_mutex);
  1765. hdmi_conf_reset(hdata);
  1766. hdmi_conf_init(hdata);
  1767. mutex_unlock(&hdata->hdmi_mutex);
  1768. hdmi_audio_init(hdata);
  1769. /* setting core registers */
  1770. hdmi_timing_apply(hdata);
  1771. hdmi_audio_control(hdata, true);
  1772. hdmi_regs_dump(hdata, "start");
  1773. }
  1774. static void hdmi_mode_fixup(void *ctx, struct drm_connector *connector,
  1775. const struct drm_display_mode *mode,
  1776. struct drm_display_mode *adjusted_mode)
  1777. {
  1778. struct drm_display_mode *m;
  1779. struct hdmi_context *hdata = ctx;
  1780. int index;
  1781. DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
  1782. drm_mode_set_crtcinfo(adjusted_mode, 0);
  1783. if (hdata->is_v13)
  1784. index = hdmi_v13_conf_index(adjusted_mode);
  1785. else
  1786. index = hdmi_v14_conf_index(adjusted_mode);
  1787. /* just return if user desired mode exists. */
  1788. if (index >= 0)
  1789. return;
  1790. /*
  1791. * otherwise, find the most suitable mode among modes and change it
  1792. * to adjusted_mode.
  1793. */
  1794. list_for_each_entry(m, &connector->modes, head) {
  1795. if (hdata->is_v13)
  1796. index = hdmi_v13_conf_index(m);
  1797. else
  1798. index = hdmi_v14_conf_index(m);
  1799. if (index >= 0) {
  1800. DRM_INFO("desired mode doesn't exist so\n");
  1801. DRM_INFO("use the most suitable mode among modes.\n");
  1802. memcpy(adjusted_mode, m, sizeof(*m));
  1803. break;
  1804. }
  1805. }
  1806. }
  1807. static void hdmi_mode_set(void *ctx, void *mode)
  1808. {
  1809. struct hdmi_context *hdata = ctx;
  1810. int conf_idx;
  1811. DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
  1812. conf_idx = hdmi_conf_index(hdata, mode);
  1813. if (conf_idx >= 0)
  1814. hdata->cur_conf = conf_idx;
  1815. else
  1816. DRM_DEBUG_KMS("not supported mode\n");
  1817. }
  1818. static void hdmi_get_max_resol(void *ctx, unsigned int *width,
  1819. unsigned int *height)
  1820. {
  1821. DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
  1822. *width = MAX_WIDTH;
  1823. *height = MAX_HEIGHT;
  1824. }
  1825. static void hdmi_commit(void *ctx)
  1826. {
  1827. struct hdmi_context *hdata = ctx;
  1828. DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
  1829. hdmi_conf_apply(hdata);
  1830. }
  1831. static void hdmi_poweron(struct hdmi_context *hdata)
  1832. {
  1833. struct hdmi_resources *res = &hdata->res;
  1834. DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
  1835. mutex_lock(&hdata->hdmi_mutex);
  1836. if (hdata->powered) {
  1837. mutex_unlock(&hdata->hdmi_mutex);
  1838. return;
  1839. }
  1840. hdata->powered = true;
  1841. if (hdata->cfg_hpd)
  1842. hdata->cfg_hpd(true);
  1843. mutex_unlock(&hdata->hdmi_mutex);
  1844. pm_runtime_get_sync(hdata->dev);
  1845. regulator_bulk_enable(res->regul_count, res->regul_bulk);
  1846. clk_enable(res->hdmiphy);
  1847. clk_enable(res->hdmi);
  1848. clk_enable(res->sclk_hdmi);
  1849. }
  1850. static void hdmi_poweroff(struct hdmi_context *hdata)
  1851. {
  1852. struct hdmi_resources *res = &hdata->res;
  1853. DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
  1854. mutex_lock(&hdata->hdmi_mutex);
  1855. if (!hdata->powered)
  1856. goto out;
  1857. mutex_unlock(&hdata->hdmi_mutex);
  1858. /*
  1859. * The TV power domain needs any condition of hdmiphy to turn off and
  1860. * its reset state seems to meet the condition.
  1861. */
  1862. hdmiphy_conf_reset(hdata);
  1863. clk_disable(res->sclk_hdmi);
  1864. clk_disable(res->hdmi);
  1865. clk_disable(res->hdmiphy);
  1866. regulator_bulk_disable(res->regul_count, res->regul_bulk);
  1867. pm_runtime_put_sync(hdata->dev);
  1868. mutex_lock(&hdata->hdmi_mutex);
  1869. if (hdata->cfg_hpd)
  1870. hdata->cfg_hpd(false);
  1871. hdata->powered = false;
  1872. out:
  1873. mutex_unlock(&hdata->hdmi_mutex);
  1874. }
  1875. static void hdmi_dpms(void *ctx, int mode)
  1876. {
  1877. struct hdmi_context *hdata = ctx;
  1878. DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
  1879. switch (mode) {
  1880. case DRM_MODE_DPMS_ON:
  1881. hdmi_poweron(hdata);
  1882. break;
  1883. case DRM_MODE_DPMS_STANDBY:
  1884. case DRM_MODE_DPMS_SUSPEND:
  1885. case DRM_MODE_DPMS_OFF:
  1886. hdmi_poweroff(hdata);
  1887. break;
  1888. default:
  1889. DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
  1890. break;
  1891. }
  1892. }
  1893. static struct exynos_hdmi_ops hdmi_ops = {
  1894. /* display */
  1895. .is_connected = hdmi_is_connected,
  1896. .get_edid = hdmi_get_edid,
  1897. .check_timing = hdmi_check_timing,
  1898. /* manager */
  1899. .mode_fixup = hdmi_mode_fixup,
  1900. .mode_set = hdmi_mode_set,
  1901. .get_max_resol = hdmi_get_max_resol,
  1902. .commit = hdmi_commit,
  1903. .dpms = hdmi_dpms,
  1904. };
  1905. static irqreturn_t hdmi_external_irq_thread(int irq, void *arg)
  1906. {
  1907. struct exynos_drm_hdmi_context *ctx = arg;
  1908. struct hdmi_context *hdata = ctx->ctx;
  1909. if (!hdata->get_hpd)
  1910. goto out;
  1911. mutex_lock(&hdata->hdmi_mutex);
  1912. hdata->hpd = hdata->get_hpd();
  1913. mutex_unlock(&hdata->hdmi_mutex);
  1914. if (ctx->drm_dev)
  1915. drm_helper_hpd_irq_event(ctx->drm_dev);
  1916. out:
  1917. return IRQ_HANDLED;
  1918. }
  1919. static irqreturn_t hdmi_internal_irq_thread(int irq, void *arg)
  1920. {
  1921. struct exynos_drm_hdmi_context *ctx = arg;
  1922. struct hdmi_context *hdata = ctx->ctx;
  1923. u32 intc_flag;
  1924. intc_flag = hdmi_reg_read(hdata, HDMI_INTC_FLAG);
  1925. /* clearing flags for HPD plug/unplug */
  1926. if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
  1927. DRM_DEBUG_KMS("unplugged\n");
  1928. hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
  1929. HDMI_INTC_FLAG_HPD_UNPLUG);
  1930. }
  1931. if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
  1932. DRM_DEBUG_KMS("plugged\n");
  1933. hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
  1934. HDMI_INTC_FLAG_HPD_PLUG);
  1935. }
  1936. mutex_lock(&hdata->hdmi_mutex);
  1937. hdata->hpd = hdmi_reg_read(hdata, HDMI_HPD_STATUS);
  1938. if (hdata->powered && hdata->hpd) {
  1939. mutex_unlock(&hdata->hdmi_mutex);
  1940. goto out;
  1941. }
  1942. mutex_unlock(&hdata->hdmi_mutex);
  1943. if (ctx->drm_dev)
  1944. drm_helper_hpd_irq_event(ctx->drm_dev);
  1945. out:
  1946. return IRQ_HANDLED;
  1947. }
  1948. static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
  1949. {
  1950. struct device *dev = hdata->dev;
  1951. struct hdmi_resources *res = &hdata->res;
  1952. static char *supply[] = {
  1953. "hdmi-en",
  1954. "vdd",
  1955. "vdd_osc",
  1956. "vdd_pll",
  1957. };
  1958. int i, ret;
  1959. DRM_DEBUG_KMS("HDMI resource init\n");
  1960. memset(res, 0, sizeof(*res));
  1961. /* get clocks, power */
  1962. res->hdmi = clk_get(dev, "hdmi");
  1963. if (IS_ERR_OR_NULL(res->hdmi)) {
  1964. DRM_ERROR("failed to get clock 'hdmi'\n");
  1965. goto fail;
  1966. }
  1967. res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
  1968. if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
  1969. DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
  1970. goto fail;
  1971. }
  1972. res->sclk_pixel = clk_get(dev, "sclk_pixel");
  1973. if (IS_ERR_OR_NULL(res->sclk_pixel)) {
  1974. DRM_ERROR("failed to get clock 'sclk_pixel'\n");
  1975. goto fail;
  1976. }
  1977. res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
  1978. if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) {
  1979. DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
  1980. goto fail;
  1981. }
  1982. res->hdmiphy = clk_get(dev, "hdmiphy");
  1983. if (IS_ERR_OR_NULL(res->hdmiphy)) {
  1984. DRM_ERROR("failed to get clock 'hdmiphy'\n");
  1985. goto fail;
  1986. }
  1987. clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
  1988. res->regul_bulk = kzalloc(ARRAY_SIZE(supply) *
  1989. sizeof(res->regul_bulk[0]), GFP_KERNEL);
  1990. if (!res->regul_bulk) {
  1991. DRM_ERROR("failed to get memory for regulators\n");
  1992. goto fail;
  1993. }
  1994. for (i = 0; i < ARRAY_SIZE(supply); ++i) {
  1995. res->regul_bulk[i].supply = supply[i];
  1996. res->regul_bulk[i].consumer = NULL;
  1997. }
  1998. ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
  1999. if (ret) {
  2000. DRM_ERROR("failed to get regulators\n");
  2001. goto fail;
  2002. }
  2003. res->regul_count = ARRAY_SIZE(supply);
  2004. return 0;
  2005. fail:
  2006. DRM_ERROR("HDMI resource init - failed\n");
  2007. return -ENODEV;
  2008. }
  2009. static int hdmi_resources_cleanup(struct hdmi_context *hdata)
  2010. {
  2011. struct hdmi_resources *res = &hdata->res;
  2012. regulator_bulk_free(res->regul_count, res->regul_bulk);
  2013. /* kfree is NULL-safe */
  2014. kfree(res->regul_bulk);
  2015. if (!IS_ERR_OR_NULL(res->hdmiphy))
  2016. clk_put(res->hdmiphy);
  2017. if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
  2018. clk_put(res->sclk_hdmiphy);
  2019. if (!IS_ERR_OR_NULL(res->sclk_pixel))
  2020. clk_put(res->sclk_pixel);
  2021. if (!IS_ERR_OR_NULL(res->sclk_hdmi))
  2022. clk_put(res->sclk_hdmi);
  2023. if (!IS_ERR_OR_NULL(res->hdmi))
  2024. clk_put(res->hdmi);
  2025. memset(res, 0, sizeof(*res));
  2026. return 0;
  2027. }
  2028. static struct i2c_client *hdmi_ddc, *hdmi_hdmiphy;
  2029. void hdmi_attach_ddc_client(struct i2c_client *ddc)
  2030. {
  2031. if (ddc)
  2032. hdmi_ddc = ddc;
  2033. }
  2034. void hdmi_attach_hdmiphy_client(struct i2c_client *hdmiphy)
  2035. {
  2036. if (hdmiphy)
  2037. hdmi_hdmiphy = hdmiphy;
  2038. }
  2039. static int __devinit hdmi_probe(struct platform_device *pdev)
  2040. {
  2041. struct device *dev = &pdev->dev;
  2042. struct exynos_drm_hdmi_context *drm_hdmi_ctx;
  2043. struct hdmi_context *hdata;
  2044. struct exynos_drm_hdmi_pdata *pdata;
  2045. struct resource *res;
  2046. int ret;
  2047. DRM_DEBUG_KMS("[%d]\n", __LINE__);
  2048. pdata = pdev->dev.platform_data;
  2049. if (!pdata) {
  2050. DRM_ERROR("no platform data specified\n");
  2051. return -EINVAL;
  2052. }
  2053. drm_hdmi_ctx = devm_kzalloc(&pdev->dev, sizeof(*drm_hdmi_ctx),
  2054. GFP_KERNEL);
  2055. if (!drm_hdmi_ctx) {
  2056. DRM_ERROR("failed to allocate common hdmi context.\n");
  2057. return -ENOMEM;
  2058. }
  2059. hdata = devm_kzalloc(&pdev->dev, sizeof(struct hdmi_context),
  2060. GFP_KERNEL);
  2061. if (!hdata) {
  2062. DRM_ERROR("out of memory\n");
  2063. return -ENOMEM;
  2064. }
  2065. mutex_init(&hdata->hdmi_mutex);
  2066. drm_hdmi_ctx->ctx = (void *)hdata;
  2067. hdata->parent_ctx = (void *)drm_hdmi_ctx;
  2068. platform_set_drvdata(pdev, drm_hdmi_ctx);
  2069. hdata->is_v13 = pdata->is_v13;
  2070. hdata->cfg_hpd = pdata->cfg_hpd;
  2071. hdata->get_hpd = pdata->get_hpd;
  2072. hdata->dev = dev;
  2073. ret = hdmi_resources_init(hdata);
  2074. if (ret) {
  2075. ret = -EINVAL;
  2076. goto err_data;
  2077. }
  2078. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2079. hdata->regs = devm_request_and_ioremap(&pdev->dev, res);
  2080. if (!hdata->regs) {
  2081. DRM_ERROR("failed to map registers\n");
  2082. ret = -ENXIO;
  2083. goto err_resource;
  2084. }
  2085. /* DDC i2c driver */
  2086. if (i2c_add_driver(&ddc_driver)) {
  2087. DRM_ERROR("failed to register ddc i2c driver\n");
  2088. ret = -ENOENT;
  2089. goto err_resource;
  2090. }
  2091. hdata->ddc_port = hdmi_ddc;
  2092. /* hdmiphy i2c driver */
  2093. if (i2c_add_driver(&hdmiphy_driver)) {
  2094. DRM_ERROR("failed to register hdmiphy i2c driver\n");
  2095. ret = -ENOENT;
  2096. goto err_ddc;
  2097. }
  2098. hdata->hdmiphy_port = hdmi_hdmiphy;
  2099. hdata->external_irq = platform_get_irq_byname(pdev, "external_irq");
  2100. if (hdata->external_irq < 0) {
  2101. DRM_ERROR("failed to get platform irq\n");
  2102. ret = hdata->external_irq;
  2103. goto err_hdmiphy;
  2104. }
  2105. hdata->internal_irq = platform_get_irq_byname(pdev, "internal_irq");
  2106. if (hdata->internal_irq < 0) {
  2107. DRM_ERROR("failed to get platform internal irq\n");
  2108. ret = hdata->internal_irq;
  2109. goto err_hdmiphy;
  2110. }
  2111. ret = request_threaded_irq(hdata->external_irq, NULL,
  2112. hdmi_external_irq_thread, IRQF_TRIGGER_RISING |
  2113. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  2114. "hdmi_external", drm_hdmi_ctx);
  2115. if (ret) {
  2116. DRM_ERROR("failed to register hdmi internal interrupt\n");
  2117. goto err_hdmiphy;
  2118. }
  2119. if (hdata->cfg_hpd)
  2120. hdata->cfg_hpd(false);
  2121. ret = request_threaded_irq(hdata->internal_irq, NULL,
  2122. hdmi_internal_irq_thread, IRQF_ONESHOT,
  2123. "hdmi_internal", drm_hdmi_ctx);
  2124. if (ret) {
  2125. DRM_ERROR("failed to register hdmi internal interrupt\n");
  2126. goto err_free_irq;
  2127. }
  2128. /* register specific callbacks to common hdmi. */
  2129. exynos_hdmi_ops_register(&hdmi_ops);
  2130. pm_runtime_enable(dev);
  2131. return 0;
  2132. err_free_irq:
  2133. free_irq(hdata->external_irq, drm_hdmi_ctx);
  2134. err_hdmiphy:
  2135. i2c_del_driver(&hdmiphy_driver);
  2136. err_ddc:
  2137. i2c_del_driver(&ddc_driver);
  2138. err_resource:
  2139. hdmi_resources_cleanup(hdata);
  2140. err_data:
  2141. return ret;
  2142. }
  2143. static int __devexit hdmi_remove(struct platform_device *pdev)
  2144. {
  2145. struct device *dev = &pdev->dev;
  2146. struct exynos_drm_hdmi_context *ctx = platform_get_drvdata(pdev);
  2147. struct hdmi_context *hdata = ctx->ctx;
  2148. DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
  2149. pm_runtime_disable(dev);
  2150. free_irq(hdata->internal_irq, hdata);
  2151. hdmi_resources_cleanup(hdata);
  2152. /* hdmiphy i2c driver */
  2153. i2c_del_driver(&hdmiphy_driver);
  2154. /* DDC i2c driver */
  2155. i2c_del_driver(&ddc_driver);
  2156. return 0;
  2157. }
  2158. #ifdef CONFIG_PM_SLEEP
  2159. static int hdmi_suspend(struct device *dev)
  2160. {
  2161. struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
  2162. struct hdmi_context *hdata = ctx->ctx;
  2163. disable_irq(hdata->internal_irq);
  2164. disable_irq(hdata->external_irq);
  2165. hdata->hpd = false;
  2166. if (ctx->drm_dev)
  2167. drm_helper_hpd_irq_event(ctx->drm_dev);
  2168. hdmi_poweroff(hdata);
  2169. return 0;
  2170. }
  2171. static int hdmi_resume(struct device *dev)
  2172. {
  2173. struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
  2174. struct hdmi_context *hdata = ctx->ctx;
  2175. enable_irq(hdata->external_irq);
  2176. enable_irq(hdata->internal_irq);
  2177. return 0;
  2178. }
  2179. #endif
  2180. static SIMPLE_DEV_PM_OPS(hdmi_pm_ops, hdmi_suspend, hdmi_resume);
  2181. struct platform_driver hdmi_driver = {
  2182. .probe = hdmi_probe,
  2183. .remove = __devexit_p(hdmi_remove),
  2184. .driver = {
  2185. .name = "exynos4-hdmi",
  2186. .owner = THIS_MODULE,
  2187. .pm = &hdmi_pm_ops,
  2188. },
  2189. };