fusb300_udc.c 37 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560
  1. /*
  2. * Fusb300 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2010 Faraday Technology Corp.
  5. *
  6. * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. */
  12. #include <linux/dma-mapping.h>
  13. #include <linux/err.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/usb/ch9.h>
  18. #include <linux/usb/gadget.h>
  19. #include "fusb300_udc.h"
  20. MODULE_DESCRIPTION("FUSB300 USB gadget driver");
  21. MODULE_LICENSE("GPL");
  22. MODULE_AUTHOR("Yuan Hsin Chen <yhchen@faraday-tech.com>");
  23. MODULE_ALIAS("platform:fusb300_udc");
  24. #define DRIVER_VERSION "20 October 2010"
  25. static const char udc_name[] = "fusb300_udc";
  26. static const char * const fusb300_ep_name[] = {
  27. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7", "ep8", "ep9",
  28. "ep10", "ep11", "ep12", "ep13", "ep14", "ep15"
  29. };
  30. static void done(struct fusb300_ep *ep, struct fusb300_request *req,
  31. int status);
  32. static void fusb300_enable_bit(struct fusb300 *fusb300, u32 offset,
  33. u32 value)
  34. {
  35. u32 reg = ioread32(fusb300->reg + offset);
  36. reg |= value;
  37. iowrite32(reg, fusb300->reg + offset);
  38. }
  39. static void fusb300_disable_bit(struct fusb300 *fusb300, u32 offset,
  40. u32 value)
  41. {
  42. u32 reg = ioread32(fusb300->reg + offset);
  43. reg &= ~value;
  44. iowrite32(reg, fusb300->reg + offset);
  45. }
  46. static void fusb300_ep_setting(struct fusb300_ep *ep,
  47. struct fusb300_ep_info info)
  48. {
  49. ep->epnum = info.epnum;
  50. ep->type = info.type;
  51. }
  52. static int fusb300_ep_release(struct fusb300_ep *ep)
  53. {
  54. if (!ep->epnum)
  55. return 0;
  56. ep->epnum = 0;
  57. ep->stall = 0;
  58. ep->wedged = 0;
  59. return 0;
  60. }
  61. static void fusb300_set_fifo_entry(struct fusb300 *fusb300,
  62. u32 ep)
  63. {
  64. u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  65. val &= ~FUSB300_EPSET1_FIFOENTRY_MSK;
  66. val |= FUSB300_EPSET1_FIFOENTRY(FUSB300_FIFO_ENTRY_NUM);
  67. iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  68. }
  69. static void fusb300_set_start_entry(struct fusb300 *fusb300,
  70. u8 ep)
  71. {
  72. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  73. u32 start_entry = fusb300->fifo_entry_num * FUSB300_FIFO_ENTRY_NUM;
  74. reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ;
  75. reg |= FUSB300_EPSET1_START_ENTRY(start_entry);
  76. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  77. if (fusb300->fifo_entry_num == FUSB300_MAX_FIFO_ENTRY) {
  78. fusb300->fifo_entry_num = 0;
  79. fusb300->addrofs = 0;
  80. pr_err("fifo entry is over the maximum number!\n");
  81. } else
  82. fusb300->fifo_entry_num++;
  83. }
  84. /* set fusb300_set_start_entry first before fusb300_set_epaddrofs */
  85. static void fusb300_set_epaddrofs(struct fusb300 *fusb300,
  86. struct fusb300_ep_info info)
  87. {
  88. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  89. reg &= ~FUSB300_EPSET2_ADDROFS_MSK;
  90. reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs);
  91. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  92. fusb300->addrofs += (info.maxpacket + 7) / 8 * FUSB300_FIFO_ENTRY_NUM;
  93. }
  94. static void ep_fifo_setting(struct fusb300 *fusb300,
  95. struct fusb300_ep_info info)
  96. {
  97. fusb300_set_fifo_entry(fusb300, info.epnum);
  98. fusb300_set_start_entry(fusb300, info.epnum);
  99. fusb300_set_epaddrofs(fusb300, info);
  100. }
  101. static void fusb300_set_eptype(struct fusb300 *fusb300,
  102. struct fusb300_ep_info info)
  103. {
  104. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  105. reg &= ~FUSB300_EPSET1_TYPE_MSK;
  106. reg |= FUSB300_EPSET1_TYPE(info.type);
  107. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  108. }
  109. static void fusb300_set_epdir(struct fusb300 *fusb300,
  110. struct fusb300_ep_info info)
  111. {
  112. u32 reg;
  113. if (!info.dir_in)
  114. return;
  115. reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  116. reg &= ~FUSB300_EPSET1_DIR_MSK;
  117. reg |= FUSB300_EPSET1_DIRIN;
  118. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  119. }
  120. static void fusb300_set_ep_active(struct fusb300 *fusb300,
  121. u8 ep)
  122. {
  123. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  124. reg |= FUSB300_EPSET1_ACTEN;
  125. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  126. }
  127. static void fusb300_set_epmps(struct fusb300 *fusb300,
  128. struct fusb300_ep_info info)
  129. {
  130. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  131. reg &= ~FUSB300_EPSET2_MPS_MSK;
  132. reg |= FUSB300_EPSET2_MPS(info.maxpacket);
  133. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  134. }
  135. static void fusb300_set_interval(struct fusb300 *fusb300,
  136. struct fusb300_ep_info info)
  137. {
  138. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  139. reg &= ~FUSB300_EPSET1_INTERVAL(0x7);
  140. reg |= FUSB300_EPSET1_INTERVAL(info.interval);
  141. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  142. }
  143. static void fusb300_set_bwnum(struct fusb300 *fusb300,
  144. struct fusb300_ep_info info)
  145. {
  146. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  147. reg &= ~FUSB300_EPSET1_BWNUM(0x3);
  148. reg |= FUSB300_EPSET1_BWNUM(info.bw_num);
  149. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  150. }
  151. static void set_ep_reg(struct fusb300 *fusb300,
  152. struct fusb300_ep_info info)
  153. {
  154. fusb300_set_eptype(fusb300, info);
  155. fusb300_set_epdir(fusb300, info);
  156. fusb300_set_epmps(fusb300, info);
  157. if (info.interval)
  158. fusb300_set_interval(fusb300, info);
  159. if (info.bw_num)
  160. fusb300_set_bwnum(fusb300, info);
  161. fusb300_set_ep_active(fusb300, info.epnum);
  162. }
  163. static int config_ep(struct fusb300_ep *ep,
  164. const struct usb_endpoint_descriptor *desc)
  165. {
  166. struct fusb300 *fusb300 = ep->fusb300;
  167. struct fusb300_ep_info info;
  168. ep->desc = desc;
  169. info.interval = 0;
  170. info.addrofs = 0;
  171. info.bw_num = 0;
  172. info.type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  173. info.dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
  174. info.maxpacket = usb_endpoint_maxp(desc);
  175. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  176. if ((info.type == USB_ENDPOINT_XFER_INT) ||
  177. (info.type == USB_ENDPOINT_XFER_ISOC)) {
  178. info.interval = desc->bInterval;
  179. if (info.type == USB_ENDPOINT_XFER_ISOC)
  180. info.bw_num = ((desc->wMaxPacketSize & 0x1800) >> 11);
  181. }
  182. ep_fifo_setting(fusb300, info);
  183. set_ep_reg(fusb300, info);
  184. fusb300_ep_setting(ep, info);
  185. fusb300->ep[info.epnum] = ep;
  186. return 0;
  187. }
  188. static int fusb300_enable(struct usb_ep *_ep,
  189. const struct usb_endpoint_descriptor *desc)
  190. {
  191. struct fusb300_ep *ep;
  192. ep = container_of(_ep, struct fusb300_ep, ep);
  193. if (ep->fusb300->reenum) {
  194. ep->fusb300->fifo_entry_num = 0;
  195. ep->fusb300->addrofs = 0;
  196. ep->fusb300->reenum = 0;
  197. }
  198. return config_ep(ep, desc);
  199. }
  200. static int fusb300_disable(struct usb_ep *_ep)
  201. {
  202. struct fusb300_ep *ep;
  203. struct fusb300_request *req;
  204. unsigned long flags;
  205. ep = container_of(_ep, struct fusb300_ep, ep);
  206. BUG_ON(!ep);
  207. while (!list_empty(&ep->queue)) {
  208. req = list_entry(ep->queue.next, struct fusb300_request, queue);
  209. spin_lock_irqsave(&ep->fusb300->lock, flags);
  210. done(ep, req, -ECONNRESET);
  211. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  212. }
  213. return fusb300_ep_release(ep);
  214. }
  215. static struct usb_request *fusb300_alloc_request(struct usb_ep *_ep,
  216. gfp_t gfp_flags)
  217. {
  218. struct fusb300_request *req;
  219. req = kzalloc(sizeof(struct fusb300_request), gfp_flags);
  220. if (!req)
  221. return NULL;
  222. INIT_LIST_HEAD(&req->queue);
  223. return &req->req;
  224. }
  225. static void fusb300_free_request(struct usb_ep *_ep, struct usb_request *_req)
  226. {
  227. struct fusb300_request *req;
  228. req = container_of(_req, struct fusb300_request, req);
  229. kfree(req);
  230. }
  231. static int enable_fifo_int(struct fusb300_ep *ep)
  232. {
  233. struct fusb300 *fusb300 = ep->fusb300;
  234. if (ep->epnum) {
  235. fusb300_enable_bit(fusb300, FUSB300_OFFSET_IGER0,
  236. FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
  237. } else {
  238. pr_err("can't enable_fifo_int ep0\n");
  239. return -EINVAL;
  240. }
  241. return 0;
  242. }
  243. static int disable_fifo_int(struct fusb300_ep *ep)
  244. {
  245. struct fusb300 *fusb300 = ep->fusb300;
  246. if (ep->epnum) {
  247. fusb300_disable_bit(fusb300, FUSB300_OFFSET_IGER0,
  248. FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
  249. } else {
  250. pr_err("can't disable_fifo_int ep0\n");
  251. return -EINVAL;
  252. }
  253. return 0;
  254. }
  255. static void fusb300_set_cxlen(struct fusb300 *fusb300, u32 length)
  256. {
  257. u32 reg;
  258. reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
  259. reg &= ~FUSB300_CSR_LEN_MSK;
  260. reg |= FUSB300_CSR_LEN(length);
  261. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR);
  262. }
  263. /* write data to cx fifo */
  264. static void fusb300_wrcxf(struct fusb300_ep *ep,
  265. struct fusb300_request *req)
  266. {
  267. int i = 0;
  268. u8 *tmp;
  269. u32 data;
  270. struct fusb300 *fusb300 = ep->fusb300;
  271. u32 length = req->req.length - req->req.actual;
  272. tmp = req->req.buf + req->req.actual;
  273. if (length > SS_CTL_MAX_PACKET_SIZE) {
  274. fusb300_set_cxlen(fusb300, SS_CTL_MAX_PACKET_SIZE);
  275. for (i = (SS_CTL_MAX_PACKET_SIZE >> 2); i > 0; i--) {
  276. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
  277. *(tmp + 3) << 24;
  278. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  279. tmp += 4;
  280. }
  281. req->req.actual += SS_CTL_MAX_PACKET_SIZE;
  282. } else { /* length is less than max packet size */
  283. fusb300_set_cxlen(fusb300, length);
  284. for (i = length >> 2; i > 0; i--) {
  285. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
  286. *(tmp + 3) << 24;
  287. printk(KERN_DEBUG " 0x%x\n", data);
  288. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  289. tmp = tmp + 4;
  290. }
  291. switch (length % 4) {
  292. case 1:
  293. data = *tmp;
  294. printk(KERN_DEBUG " 0x%x\n", data);
  295. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  296. break;
  297. case 2:
  298. data = *tmp | *(tmp + 1) << 8;
  299. printk(KERN_DEBUG " 0x%x\n", data);
  300. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  301. break;
  302. case 3:
  303. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
  304. printk(KERN_DEBUG " 0x%x\n", data);
  305. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  306. break;
  307. default:
  308. break;
  309. }
  310. req->req.actual += length;
  311. }
  312. }
  313. static void fusb300_set_epnstall(struct fusb300 *fusb300, u8 ep)
  314. {
  315. fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
  316. FUSB300_EPSET0_STL);
  317. }
  318. static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep)
  319. {
  320. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  321. if (reg & FUSB300_EPSET0_STL) {
  322. printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep);
  323. reg &= ~FUSB300_EPSET0_STL;
  324. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  325. }
  326. }
  327. static void ep0_queue(struct fusb300_ep *ep, struct fusb300_request *req)
  328. {
  329. if (ep->fusb300->ep0_dir) { /* if IN */
  330. if (req->req.length) {
  331. fusb300_wrcxf(ep, req);
  332. } else
  333. printk(KERN_DEBUG "%s : req->req.length = 0x%x\n",
  334. __func__, req->req.length);
  335. if ((req->req.length == req->req.actual) ||
  336. (req->req.actual < ep->ep.maxpacket))
  337. done(ep, req, 0);
  338. } else { /* OUT */
  339. if (!req->req.length)
  340. done(ep, req, 0);
  341. else
  342. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER1,
  343. FUSB300_IGER1_CX_OUT_INT);
  344. }
  345. }
  346. static int fusb300_queue(struct usb_ep *_ep, struct usb_request *_req,
  347. gfp_t gfp_flags)
  348. {
  349. struct fusb300_ep *ep;
  350. struct fusb300_request *req;
  351. unsigned long flags;
  352. int request = 0;
  353. ep = container_of(_ep, struct fusb300_ep, ep);
  354. req = container_of(_req, struct fusb300_request, req);
  355. if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
  356. return -ESHUTDOWN;
  357. spin_lock_irqsave(&ep->fusb300->lock, flags);
  358. if (list_empty(&ep->queue))
  359. request = 1;
  360. list_add_tail(&req->queue, &ep->queue);
  361. req->req.actual = 0;
  362. req->req.status = -EINPROGRESS;
  363. if (ep->desc == NULL) /* ep0 */
  364. ep0_queue(ep, req);
  365. else if (request && !ep->stall)
  366. enable_fifo_int(ep);
  367. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  368. return 0;
  369. }
  370. static int fusb300_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  371. {
  372. struct fusb300_ep *ep;
  373. struct fusb300_request *req;
  374. unsigned long flags;
  375. ep = container_of(_ep, struct fusb300_ep, ep);
  376. req = container_of(_req, struct fusb300_request, req);
  377. spin_lock_irqsave(&ep->fusb300->lock, flags);
  378. if (!list_empty(&ep->queue))
  379. done(ep, req, -ECONNRESET);
  380. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  381. return 0;
  382. }
  383. static int fusb300_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
  384. {
  385. struct fusb300_ep *ep;
  386. struct fusb300 *fusb300;
  387. unsigned long flags;
  388. int ret = 0;
  389. ep = container_of(_ep, struct fusb300_ep, ep);
  390. fusb300 = ep->fusb300;
  391. spin_lock_irqsave(&ep->fusb300->lock, flags);
  392. if (!list_empty(&ep->queue)) {
  393. ret = -EAGAIN;
  394. goto out;
  395. }
  396. if (value) {
  397. fusb300_set_epnstall(fusb300, ep->epnum);
  398. ep->stall = 1;
  399. if (wedge)
  400. ep->wedged = 1;
  401. } else {
  402. fusb300_clear_epnstall(fusb300, ep->epnum);
  403. ep->stall = 0;
  404. ep->wedged = 0;
  405. }
  406. out:
  407. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  408. return ret;
  409. }
  410. static int fusb300_set_halt(struct usb_ep *_ep, int value)
  411. {
  412. return fusb300_set_halt_and_wedge(_ep, value, 0);
  413. }
  414. static int fusb300_set_wedge(struct usb_ep *_ep)
  415. {
  416. return fusb300_set_halt_and_wedge(_ep, 1, 1);
  417. }
  418. static void fusb300_fifo_flush(struct usb_ep *_ep)
  419. {
  420. }
  421. static struct usb_ep_ops fusb300_ep_ops = {
  422. .enable = fusb300_enable,
  423. .disable = fusb300_disable,
  424. .alloc_request = fusb300_alloc_request,
  425. .free_request = fusb300_free_request,
  426. .queue = fusb300_queue,
  427. .dequeue = fusb300_dequeue,
  428. .set_halt = fusb300_set_halt,
  429. .fifo_flush = fusb300_fifo_flush,
  430. .set_wedge = fusb300_set_wedge,
  431. };
  432. /*****************************************************************************/
  433. static void fusb300_clear_int(struct fusb300 *fusb300, u32 offset,
  434. u32 value)
  435. {
  436. iowrite32(value, fusb300->reg + offset);
  437. }
  438. static void fusb300_reset(void)
  439. {
  440. }
  441. static void fusb300_set_cxstall(struct fusb300 *fusb300)
  442. {
  443. fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
  444. FUSB300_CSR_STL);
  445. }
  446. static void fusb300_set_cxdone(struct fusb300 *fusb300)
  447. {
  448. fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
  449. FUSB300_CSR_DONE);
  450. }
  451. /* read data from cx fifo */
  452. void fusb300_rdcxf(struct fusb300 *fusb300,
  453. u8 *buffer, u32 length)
  454. {
  455. int i = 0;
  456. u8 *tmp;
  457. u32 data;
  458. tmp = buffer;
  459. for (i = (length >> 2); i > 0; i--) {
  460. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  461. printk(KERN_DEBUG " 0x%x\n", data);
  462. *tmp = data & 0xFF;
  463. *(tmp + 1) = (data >> 8) & 0xFF;
  464. *(tmp + 2) = (data >> 16) & 0xFF;
  465. *(tmp + 3) = (data >> 24) & 0xFF;
  466. tmp = tmp + 4;
  467. }
  468. switch (length % 4) {
  469. case 1:
  470. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  471. printk(KERN_DEBUG " 0x%x\n", data);
  472. *tmp = data & 0xFF;
  473. break;
  474. case 2:
  475. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  476. printk(KERN_DEBUG " 0x%x\n", data);
  477. *tmp = data & 0xFF;
  478. *(tmp + 1) = (data >> 8) & 0xFF;
  479. break;
  480. case 3:
  481. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  482. printk(KERN_DEBUG " 0x%x\n", data);
  483. *tmp = data & 0xFF;
  484. *(tmp + 1) = (data >> 8) & 0xFF;
  485. *(tmp + 2) = (data >> 16) & 0xFF;
  486. break;
  487. default:
  488. break;
  489. }
  490. }
  491. static void fusb300_rdfifo(struct fusb300_ep *ep,
  492. struct fusb300_request *req,
  493. u32 length)
  494. {
  495. int i = 0;
  496. u8 *tmp;
  497. u32 data, reg;
  498. struct fusb300 *fusb300 = ep->fusb300;
  499. tmp = req->req.buf + req->req.actual;
  500. req->req.actual += length;
  501. if (req->req.actual > req->req.length)
  502. printk(KERN_DEBUG "req->req.actual > req->req.length\n");
  503. for (i = (length >> 2); i > 0; i--) {
  504. data = ioread32(fusb300->reg +
  505. FUSB300_OFFSET_EPPORT(ep->epnum));
  506. *tmp = data & 0xFF;
  507. *(tmp + 1) = (data >> 8) & 0xFF;
  508. *(tmp + 2) = (data >> 16) & 0xFF;
  509. *(tmp + 3) = (data >> 24) & 0xFF;
  510. tmp = tmp + 4;
  511. }
  512. switch (length % 4) {
  513. case 1:
  514. data = ioread32(fusb300->reg +
  515. FUSB300_OFFSET_EPPORT(ep->epnum));
  516. *tmp = data & 0xFF;
  517. break;
  518. case 2:
  519. data = ioread32(fusb300->reg +
  520. FUSB300_OFFSET_EPPORT(ep->epnum));
  521. *tmp = data & 0xFF;
  522. *(tmp + 1) = (data >> 8) & 0xFF;
  523. break;
  524. case 3:
  525. data = ioread32(fusb300->reg +
  526. FUSB300_OFFSET_EPPORT(ep->epnum));
  527. *tmp = data & 0xFF;
  528. *(tmp + 1) = (data >> 8) & 0xFF;
  529. *(tmp + 2) = (data >> 16) & 0xFF;
  530. break;
  531. default:
  532. break;
  533. }
  534. do {
  535. reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
  536. reg &= FUSB300_IGR1_SYNF0_EMPTY_INT;
  537. if (i)
  538. printk(KERN_INFO "sync fifo is not empty!\n");
  539. i++;
  540. } while (!reg);
  541. }
  542. static u8 fusb300_get_epnstall(struct fusb300 *fusb300, u8 ep)
  543. {
  544. u8 value;
  545. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  546. value = reg & FUSB300_EPSET0_STL;
  547. return value;
  548. }
  549. static u8 fusb300_get_cxstall(struct fusb300 *fusb300)
  550. {
  551. u8 value;
  552. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
  553. value = (reg & FUSB300_CSR_STL) >> 1;
  554. return value;
  555. }
  556. static void request_error(struct fusb300 *fusb300)
  557. {
  558. fusb300_set_cxstall(fusb300);
  559. printk(KERN_DEBUG "request error!!\n");
  560. }
  561. static void get_status(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  562. __releases(fusb300->lock)
  563. __acquires(fusb300->lock)
  564. {
  565. u8 ep;
  566. u16 status = 0;
  567. u16 w_index = ctrl->wIndex;
  568. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  569. case USB_RECIP_DEVICE:
  570. status = 1 << USB_DEVICE_SELF_POWERED;
  571. break;
  572. case USB_RECIP_INTERFACE:
  573. status = 0;
  574. break;
  575. case USB_RECIP_ENDPOINT:
  576. ep = w_index & USB_ENDPOINT_NUMBER_MASK;
  577. if (ep) {
  578. if (fusb300_get_epnstall(fusb300, ep))
  579. status = 1 << USB_ENDPOINT_HALT;
  580. } else {
  581. if (fusb300_get_cxstall(fusb300))
  582. status = 0;
  583. }
  584. break;
  585. default:
  586. request_error(fusb300);
  587. return; /* exit */
  588. }
  589. fusb300->ep0_data = cpu_to_le16(status);
  590. fusb300->ep0_req->buf = &fusb300->ep0_data;
  591. fusb300->ep0_req->length = 2;
  592. spin_unlock(&fusb300->lock);
  593. fusb300_queue(fusb300->gadget.ep0, fusb300->ep0_req, GFP_KERNEL);
  594. spin_lock(&fusb300->lock);
  595. }
  596. static void set_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  597. {
  598. u8 ep;
  599. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  600. case USB_RECIP_DEVICE:
  601. fusb300_set_cxdone(fusb300);
  602. break;
  603. case USB_RECIP_INTERFACE:
  604. fusb300_set_cxdone(fusb300);
  605. break;
  606. case USB_RECIP_ENDPOINT: {
  607. u16 w_index = le16_to_cpu(ctrl->wIndex);
  608. ep = w_index & USB_ENDPOINT_NUMBER_MASK;
  609. if (ep)
  610. fusb300_set_epnstall(fusb300, ep);
  611. else
  612. fusb300_set_cxstall(fusb300);
  613. fusb300_set_cxdone(fusb300);
  614. }
  615. break;
  616. default:
  617. request_error(fusb300);
  618. break;
  619. }
  620. }
  621. static void fusb300_clear_seqnum(struct fusb300 *fusb300, u8 ep)
  622. {
  623. fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
  624. FUSB300_EPSET0_CLRSEQNUM);
  625. }
  626. static void clear_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  627. {
  628. struct fusb300_ep *ep =
  629. fusb300->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
  630. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  631. case USB_RECIP_DEVICE:
  632. fusb300_set_cxdone(fusb300);
  633. break;
  634. case USB_RECIP_INTERFACE:
  635. fusb300_set_cxdone(fusb300);
  636. break;
  637. case USB_RECIP_ENDPOINT:
  638. if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
  639. if (ep->wedged) {
  640. fusb300_set_cxdone(fusb300);
  641. break;
  642. }
  643. if (ep->stall) {
  644. ep->stall = 0;
  645. fusb300_clear_seqnum(fusb300, ep->epnum);
  646. fusb300_clear_epnstall(fusb300, ep->epnum);
  647. if (!list_empty(&ep->queue))
  648. enable_fifo_int(ep);
  649. }
  650. }
  651. fusb300_set_cxdone(fusb300);
  652. break;
  653. default:
  654. request_error(fusb300);
  655. break;
  656. }
  657. }
  658. static void fusb300_set_dev_addr(struct fusb300 *fusb300, u16 addr)
  659. {
  660. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR);
  661. reg &= ~FUSB300_DAR_DRVADDR_MSK;
  662. reg |= FUSB300_DAR_DRVADDR(addr);
  663. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR);
  664. }
  665. static void set_address(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  666. {
  667. if (ctrl->wValue >= 0x0100)
  668. request_error(fusb300);
  669. else {
  670. fusb300_set_dev_addr(fusb300, ctrl->wValue);
  671. fusb300_set_cxdone(fusb300);
  672. }
  673. }
  674. #define UVC_COPY_DESCRIPTORS(mem, src) \
  675. do { \
  676. const struct usb_descriptor_header * const *__src; \
  677. for (__src = src; *__src; ++__src) { \
  678. memcpy(mem, *__src, (*__src)->bLength); \
  679. mem += (*__src)->bLength; \
  680. } \
  681. } while (0)
  682. static int setup_packet(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  683. {
  684. u8 *p = (u8 *)ctrl;
  685. u8 ret = 0;
  686. u8 i = 0;
  687. fusb300_rdcxf(fusb300, p, 8);
  688. fusb300->ep0_dir = ctrl->bRequestType & USB_DIR_IN;
  689. fusb300->ep0_length = ctrl->wLength;
  690. /* check request */
  691. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  692. switch (ctrl->bRequest) {
  693. case USB_REQ_GET_STATUS:
  694. get_status(fusb300, ctrl);
  695. break;
  696. case USB_REQ_CLEAR_FEATURE:
  697. clear_feature(fusb300, ctrl);
  698. break;
  699. case USB_REQ_SET_FEATURE:
  700. set_feature(fusb300, ctrl);
  701. break;
  702. case USB_REQ_SET_ADDRESS:
  703. set_address(fusb300, ctrl);
  704. break;
  705. case USB_REQ_SET_CONFIGURATION:
  706. fusb300_enable_bit(fusb300, FUSB300_OFFSET_DAR,
  707. FUSB300_DAR_SETCONFG);
  708. /* clear sequence number */
  709. for (i = 1; i <= FUSB300_MAX_NUM_EP; i++)
  710. fusb300_clear_seqnum(fusb300, i);
  711. fusb300->reenum = 1;
  712. ret = 1;
  713. break;
  714. default:
  715. ret = 1;
  716. break;
  717. }
  718. } else
  719. ret = 1;
  720. return ret;
  721. }
  722. static void done(struct fusb300_ep *ep, struct fusb300_request *req,
  723. int status)
  724. {
  725. list_del_init(&req->queue);
  726. /* don't modify queue heads during completion callback */
  727. if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
  728. req->req.status = -ESHUTDOWN;
  729. else
  730. req->req.status = status;
  731. spin_unlock(&ep->fusb300->lock);
  732. req->req.complete(&ep->ep, &req->req);
  733. spin_lock(&ep->fusb300->lock);
  734. if (ep->epnum) {
  735. disable_fifo_int(ep);
  736. if (!list_empty(&ep->queue))
  737. enable_fifo_int(ep);
  738. } else
  739. fusb300_set_cxdone(ep->fusb300);
  740. }
  741. static void fusb300_fill_idma_prdtbl(struct fusb300_ep *ep, dma_addr_t d,
  742. u32 len)
  743. {
  744. u32 value;
  745. u32 reg;
  746. /* wait SW owner */
  747. do {
  748. reg = ioread32(ep->fusb300->reg +
  749. FUSB300_OFFSET_EPPRD_W0(ep->epnum));
  750. reg &= FUSB300_EPPRD0_H;
  751. } while (reg);
  752. iowrite32(d, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W1(ep->epnum));
  753. value = FUSB300_EPPRD0_BTC(len) | FUSB300_EPPRD0_H |
  754. FUSB300_EPPRD0_F | FUSB300_EPPRD0_L | FUSB300_EPPRD0_I;
  755. iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum));
  756. iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum));
  757. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_EPPRDRDY,
  758. FUSB300_EPPRDR_EP_PRD_RDY(ep->epnum));
  759. }
  760. static void fusb300_wait_idma_finished(struct fusb300_ep *ep)
  761. {
  762. u32 reg;
  763. do {
  764. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1);
  765. if ((reg & FUSB300_IGR1_VBUS_CHG_INT) ||
  766. (reg & FUSB300_IGR1_WARM_RST_INT) ||
  767. (reg & FUSB300_IGR1_HOT_RST_INT) ||
  768. (reg & FUSB300_IGR1_USBRST_INT)
  769. )
  770. goto IDMA_RESET;
  771. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0);
  772. reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum);
  773. } while (!reg);
  774. fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGR0,
  775. FUSB300_IGR0_EPn_PRD_INT(ep->epnum));
  776. IDMA_RESET:
  777. fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGER0,
  778. FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
  779. }
  780. static void fusb300_set_idma(struct fusb300_ep *ep,
  781. struct fusb300_request *req)
  782. {
  783. dma_addr_t d;
  784. d = dma_map_single(NULL, req->req.buf, req->req.length, DMA_TO_DEVICE);
  785. if (dma_mapping_error(NULL, d)) {
  786. printk(KERN_DEBUG "dma_mapping_error\n");
  787. return;
  788. }
  789. dma_sync_single_for_device(NULL, d, req->req.length, DMA_TO_DEVICE);
  790. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER0,
  791. FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
  792. fusb300_fill_idma_prdtbl(ep, d, req->req.length);
  793. /* check idma is done */
  794. fusb300_wait_idma_finished(ep);
  795. dma_unmap_single(NULL, d, req->req.length, DMA_TO_DEVICE);
  796. }
  797. static void in_ep_fifo_handler(struct fusb300_ep *ep)
  798. {
  799. struct fusb300_request *req = list_entry(ep->queue.next,
  800. struct fusb300_request, queue);
  801. if (req->req.length)
  802. fusb300_set_idma(ep, req);
  803. done(ep, req, 0);
  804. }
  805. static void out_ep_fifo_handler(struct fusb300_ep *ep)
  806. {
  807. struct fusb300 *fusb300 = ep->fusb300;
  808. struct fusb300_request *req = list_entry(ep->queue.next,
  809. struct fusb300_request, queue);
  810. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
  811. u32 length = reg & FUSB300_FFR_BYCNT;
  812. fusb300_rdfifo(ep, req, length);
  813. /* finish out transfer */
  814. if ((req->req.length == req->req.actual) || (length < ep->ep.maxpacket))
  815. done(ep, req, 0);
  816. }
  817. static void check_device_mode(struct fusb300 *fusb300)
  818. {
  819. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR);
  820. switch (reg & FUSB300_GCR_DEVEN_MSK) {
  821. case FUSB300_GCR_DEVEN_SS:
  822. fusb300->gadget.speed = USB_SPEED_SUPER;
  823. break;
  824. case FUSB300_GCR_DEVEN_HS:
  825. fusb300->gadget.speed = USB_SPEED_HIGH;
  826. break;
  827. case FUSB300_GCR_DEVEN_FS:
  828. fusb300->gadget.speed = USB_SPEED_FULL;
  829. break;
  830. default:
  831. fusb300->gadget.speed = USB_SPEED_UNKNOWN;
  832. break;
  833. }
  834. printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK));
  835. }
  836. static void fusb300_ep0out(struct fusb300 *fusb300)
  837. {
  838. struct fusb300_ep *ep = fusb300->ep[0];
  839. u32 reg;
  840. if (!list_empty(&ep->queue)) {
  841. struct fusb300_request *req;
  842. req = list_first_entry(&ep->queue,
  843. struct fusb300_request, queue);
  844. if (req->req.length)
  845. fusb300_rdcxf(ep->fusb300, req->req.buf,
  846. req->req.length);
  847. done(ep, req, 0);
  848. reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
  849. reg &= ~FUSB300_IGER1_CX_OUT_INT;
  850. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1);
  851. } else
  852. pr_err("%s : empty queue\n", __func__);
  853. }
  854. static void fusb300_ep0in(struct fusb300 *fusb300)
  855. {
  856. struct fusb300_request *req;
  857. struct fusb300_ep *ep = fusb300->ep[0];
  858. if ((!list_empty(&ep->queue)) && (fusb300->ep0_dir)) {
  859. req = list_entry(ep->queue.next,
  860. struct fusb300_request, queue);
  861. if (req->req.length)
  862. fusb300_wrcxf(ep, req);
  863. if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
  864. done(ep, req, 0);
  865. } else
  866. fusb300_set_cxdone(fusb300);
  867. }
  868. static void fusb300_grp2_handler(void)
  869. {
  870. }
  871. static void fusb300_grp3_handler(void)
  872. {
  873. }
  874. static void fusb300_grp4_handler(void)
  875. {
  876. }
  877. static void fusb300_grp5_handler(void)
  878. {
  879. }
  880. static irqreturn_t fusb300_irq(int irq, void *_fusb300)
  881. {
  882. struct fusb300 *fusb300 = _fusb300;
  883. u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
  884. u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
  885. u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0);
  886. u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0);
  887. struct usb_ctrlrequest ctrl;
  888. u8 in;
  889. u32 reg;
  890. int i;
  891. spin_lock(&fusb300->lock);
  892. int_grp1 &= int_grp1_en;
  893. int_grp0 &= int_grp0_en;
  894. if (int_grp1 & FUSB300_IGR1_WARM_RST_INT) {
  895. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  896. FUSB300_IGR1_WARM_RST_INT);
  897. printk(KERN_INFO"fusb300_warmreset\n");
  898. fusb300_reset();
  899. }
  900. if (int_grp1 & FUSB300_IGR1_HOT_RST_INT) {
  901. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  902. FUSB300_IGR1_HOT_RST_INT);
  903. printk(KERN_INFO"fusb300_hotreset\n");
  904. fusb300_reset();
  905. }
  906. if (int_grp1 & FUSB300_IGR1_USBRST_INT) {
  907. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  908. FUSB300_IGR1_USBRST_INT);
  909. fusb300_reset();
  910. }
  911. /* COMABT_INT has a highest priority */
  912. if (int_grp1 & FUSB300_IGR1_CX_COMABT_INT) {
  913. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  914. FUSB300_IGR1_CX_COMABT_INT);
  915. printk(KERN_INFO"fusb300_ep0abt\n");
  916. }
  917. if (int_grp1 & FUSB300_IGR1_VBUS_CHG_INT) {
  918. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  919. FUSB300_IGR1_VBUS_CHG_INT);
  920. printk(KERN_INFO"fusb300_vbus_change\n");
  921. }
  922. if (int_grp1 & FUSB300_IGR1_U3_EXIT_FAIL_INT) {
  923. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  924. FUSB300_IGR1_U3_EXIT_FAIL_INT);
  925. }
  926. if (int_grp1 & FUSB300_IGR1_U2_EXIT_FAIL_INT) {
  927. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  928. FUSB300_IGR1_U2_EXIT_FAIL_INT);
  929. }
  930. if (int_grp1 & FUSB300_IGR1_U1_EXIT_FAIL_INT) {
  931. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  932. FUSB300_IGR1_U1_EXIT_FAIL_INT);
  933. }
  934. if (int_grp1 & FUSB300_IGR1_U2_ENTRY_FAIL_INT) {
  935. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  936. FUSB300_IGR1_U2_ENTRY_FAIL_INT);
  937. }
  938. if (int_grp1 & FUSB300_IGR1_U1_ENTRY_FAIL_INT) {
  939. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  940. FUSB300_IGR1_U1_ENTRY_FAIL_INT);
  941. }
  942. if (int_grp1 & FUSB300_IGR1_U3_EXIT_INT) {
  943. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  944. FUSB300_IGR1_U3_EXIT_INT);
  945. printk(KERN_INFO "FUSB300_IGR1_U3_EXIT_INT\n");
  946. }
  947. if (int_grp1 & FUSB300_IGR1_U2_EXIT_INT) {
  948. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  949. FUSB300_IGR1_U2_EXIT_INT);
  950. printk(KERN_INFO "FUSB300_IGR1_U2_EXIT_INT\n");
  951. }
  952. if (int_grp1 & FUSB300_IGR1_U1_EXIT_INT) {
  953. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  954. FUSB300_IGR1_U1_EXIT_INT);
  955. printk(KERN_INFO "FUSB300_IGR1_U1_EXIT_INT\n");
  956. }
  957. if (int_grp1 & FUSB300_IGR1_U3_ENTRY_INT) {
  958. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  959. FUSB300_IGR1_U3_ENTRY_INT);
  960. printk(KERN_INFO "FUSB300_IGR1_U3_ENTRY_INT\n");
  961. fusb300_enable_bit(fusb300, FUSB300_OFFSET_SSCR1,
  962. FUSB300_SSCR1_GO_U3_DONE);
  963. }
  964. if (int_grp1 & FUSB300_IGR1_U2_ENTRY_INT) {
  965. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  966. FUSB300_IGR1_U2_ENTRY_INT);
  967. printk(KERN_INFO "FUSB300_IGR1_U2_ENTRY_INT\n");
  968. }
  969. if (int_grp1 & FUSB300_IGR1_U1_ENTRY_INT) {
  970. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  971. FUSB300_IGR1_U1_ENTRY_INT);
  972. printk(KERN_INFO "FUSB300_IGR1_U1_ENTRY_INT\n");
  973. }
  974. if (int_grp1 & FUSB300_IGR1_RESM_INT) {
  975. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  976. FUSB300_IGR1_RESM_INT);
  977. printk(KERN_INFO "fusb300_resume\n");
  978. }
  979. if (int_grp1 & FUSB300_IGR1_SUSP_INT) {
  980. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  981. FUSB300_IGR1_SUSP_INT);
  982. printk(KERN_INFO "fusb300_suspend\n");
  983. }
  984. if (int_grp1 & FUSB300_IGR1_HS_LPM_INT) {
  985. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  986. FUSB300_IGR1_HS_LPM_INT);
  987. printk(KERN_INFO "fusb300_HS_LPM_INT\n");
  988. }
  989. if (int_grp1 & FUSB300_IGR1_DEV_MODE_CHG_INT) {
  990. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  991. FUSB300_IGR1_DEV_MODE_CHG_INT);
  992. check_device_mode(fusb300);
  993. }
  994. if (int_grp1 & FUSB300_IGR1_CX_COMFAIL_INT) {
  995. fusb300_set_cxstall(fusb300);
  996. printk(KERN_INFO "fusb300_ep0fail\n");
  997. }
  998. if (int_grp1 & FUSB300_IGR1_CX_SETUP_INT) {
  999. printk(KERN_INFO "fusb300_ep0setup\n");
  1000. if (setup_packet(fusb300, &ctrl)) {
  1001. spin_unlock(&fusb300->lock);
  1002. if (fusb300->driver->setup(&fusb300->gadget, &ctrl) < 0)
  1003. fusb300_set_cxstall(fusb300);
  1004. spin_lock(&fusb300->lock);
  1005. }
  1006. }
  1007. if (int_grp1 & FUSB300_IGR1_CX_CMDEND_INT)
  1008. printk(KERN_INFO "fusb300_cmdend\n");
  1009. if (int_grp1 & FUSB300_IGR1_CX_OUT_INT) {
  1010. printk(KERN_INFO "fusb300_cxout\n");
  1011. fusb300_ep0out(fusb300);
  1012. }
  1013. if (int_grp1 & FUSB300_IGR1_CX_IN_INT) {
  1014. printk(KERN_INFO "fusb300_cxin\n");
  1015. fusb300_ep0in(fusb300);
  1016. }
  1017. if (int_grp1 & FUSB300_IGR1_INTGRP5)
  1018. fusb300_grp5_handler();
  1019. if (int_grp1 & FUSB300_IGR1_INTGRP4)
  1020. fusb300_grp4_handler();
  1021. if (int_grp1 & FUSB300_IGR1_INTGRP3)
  1022. fusb300_grp3_handler();
  1023. if (int_grp1 & FUSB300_IGR1_INTGRP2)
  1024. fusb300_grp2_handler();
  1025. if (int_grp0) {
  1026. for (i = 1; i < FUSB300_MAX_NUM_EP; i++) {
  1027. if (int_grp0 & FUSB300_IGR0_EPn_FIFO_INT(i)) {
  1028. reg = ioread32(fusb300->reg +
  1029. FUSB300_OFFSET_EPSET1(i));
  1030. in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0;
  1031. if (in)
  1032. in_ep_fifo_handler(fusb300->ep[i]);
  1033. else
  1034. out_ep_fifo_handler(fusb300->ep[i]);
  1035. }
  1036. }
  1037. }
  1038. spin_unlock(&fusb300->lock);
  1039. return IRQ_HANDLED;
  1040. }
  1041. static void fusb300_set_u2_timeout(struct fusb300 *fusb300,
  1042. u32 time)
  1043. {
  1044. u32 reg;
  1045. reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
  1046. reg &= ~0xff;
  1047. reg |= FUSB300_SSCR2_U2TIMEOUT(time);
  1048. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
  1049. }
  1050. static void fusb300_set_u1_timeout(struct fusb300 *fusb300,
  1051. u32 time)
  1052. {
  1053. u32 reg;
  1054. reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
  1055. reg &= ~(0xff << 8);
  1056. reg |= FUSB300_SSCR2_U1TIMEOUT(time);
  1057. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
  1058. }
  1059. static void init_controller(struct fusb300 *fusb300)
  1060. {
  1061. u32 reg;
  1062. u32 mask = 0;
  1063. u32 val = 0;
  1064. /* split on */
  1065. mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON;
  1066. reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR);
  1067. reg &= ~mask;
  1068. reg |= val;
  1069. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR);
  1070. /* enable high-speed LPM */
  1071. mask = val = FUSB300_HSCR_HS_LPM_PERMIT;
  1072. reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR);
  1073. reg &= ~mask;
  1074. reg |= val;
  1075. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR);
  1076. /*set u1 u2 timmer*/
  1077. fusb300_set_u2_timeout(fusb300, 0xff);
  1078. fusb300_set_u1_timeout(fusb300, 0xff);
  1079. /* enable all grp1 interrupt */
  1080. iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1);
  1081. }
  1082. /*------------------------------------------------------------------------*/
  1083. static struct fusb300 *the_controller;
  1084. static int fusb300_udc_start(struct usb_gadget_driver *driver,
  1085. int (*bind)(struct usb_gadget *))
  1086. {
  1087. struct fusb300 *fusb300 = the_controller;
  1088. int retval;
  1089. if (!driver
  1090. || driver->speed < USB_SPEED_FULL
  1091. || !bind
  1092. || !driver->setup)
  1093. return -EINVAL;
  1094. if (!fusb300)
  1095. return -ENODEV;
  1096. if (fusb300->driver)
  1097. return -EBUSY;
  1098. /* hook up the driver */
  1099. driver->driver.bus = NULL;
  1100. fusb300->driver = driver;
  1101. fusb300->gadget.dev.driver = &driver->driver;
  1102. retval = device_add(&fusb300->gadget.dev);
  1103. if (retval) {
  1104. pr_err("device_add error (%d)\n", retval);
  1105. goto error;
  1106. }
  1107. retval = bind(&fusb300->gadget);
  1108. if (retval) {
  1109. pr_err("bind to driver error (%d)\n", retval);
  1110. device_del(&fusb300->gadget.dev);
  1111. goto error;
  1112. }
  1113. return 0;
  1114. error:
  1115. fusb300->driver = NULL;
  1116. fusb300->gadget.dev.driver = NULL;
  1117. return retval;
  1118. }
  1119. static int fusb300_udc_stop(struct usb_gadget_driver *driver)
  1120. {
  1121. struct fusb300 *fusb300 = the_controller;
  1122. if (driver != fusb300->driver || !driver->unbind)
  1123. return -EINVAL;
  1124. driver->unbind(&fusb300->gadget);
  1125. fusb300->gadget.dev.driver = NULL;
  1126. init_controller(fusb300);
  1127. device_del(&fusb300->gadget.dev);
  1128. fusb300->driver = NULL;
  1129. return 0;
  1130. }
  1131. /*--------------------------------------------------------------------------*/
  1132. static int fusb300_udc_pullup(struct usb_gadget *_gadget, int is_active)
  1133. {
  1134. return 0;
  1135. }
  1136. static struct usb_gadget_ops fusb300_gadget_ops = {
  1137. .pullup = fusb300_udc_pullup,
  1138. .start = fusb300_udc_start,
  1139. .stop = fusb300_udc_stop,
  1140. };
  1141. static int __exit fusb300_remove(struct platform_device *pdev)
  1142. {
  1143. struct fusb300 *fusb300 = dev_get_drvdata(&pdev->dev);
  1144. usb_del_gadget_udc(&fusb300->gadget);
  1145. iounmap(fusb300->reg);
  1146. free_irq(platform_get_irq(pdev, 0), fusb300);
  1147. fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
  1148. kfree(fusb300);
  1149. return 0;
  1150. }
  1151. static int __init fusb300_probe(struct platform_device *pdev)
  1152. {
  1153. struct resource *res, *ires, *ires1;
  1154. void __iomem *reg = NULL;
  1155. struct fusb300 *fusb300 = NULL;
  1156. struct fusb300_ep *_ep[FUSB300_MAX_NUM_EP];
  1157. int ret = 0;
  1158. int i;
  1159. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1160. if (!res) {
  1161. ret = -ENODEV;
  1162. pr_err("platform_get_resource error.\n");
  1163. goto clean_up;
  1164. }
  1165. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1166. if (!ires) {
  1167. ret = -ENODEV;
  1168. dev_err(&pdev->dev,
  1169. "platform_get_resource IORESOURCE_IRQ error.\n");
  1170. goto clean_up;
  1171. }
  1172. ires1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
  1173. if (!ires1) {
  1174. ret = -ENODEV;
  1175. dev_err(&pdev->dev,
  1176. "platform_get_resource IORESOURCE_IRQ 1 error.\n");
  1177. goto clean_up;
  1178. }
  1179. reg = ioremap(res->start, resource_size(res));
  1180. if (reg == NULL) {
  1181. ret = -ENOMEM;
  1182. pr_err("ioremap error.\n");
  1183. goto clean_up;
  1184. }
  1185. /* initialize udc */
  1186. fusb300 = kzalloc(sizeof(struct fusb300), GFP_KERNEL);
  1187. if (fusb300 == NULL) {
  1188. pr_err("kzalloc error\n");
  1189. goto clean_up;
  1190. }
  1191. for (i = 0; i < FUSB300_MAX_NUM_EP; i++) {
  1192. _ep[i] = kzalloc(sizeof(struct fusb300_ep), GFP_KERNEL);
  1193. if (_ep[i] == NULL) {
  1194. pr_err("_ep kzalloc error\n");
  1195. goto clean_up;
  1196. }
  1197. fusb300->ep[i] = _ep[i];
  1198. }
  1199. spin_lock_init(&fusb300->lock);
  1200. dev_set_drvdata(&pdev->dev, fusb300);
  1201. fusb300->gadget.ops = &fusb300_gadget_ops;
  1202. device_initialize(&fusb300->gadget.dev);
  1203. dev_set_name(&fusb300->gadget.dev, "gadget");
  1204. fusb300->gadget.is_dualspeed = 1;
  1205. fusb300->gadget.dev.parent = &pdev->dev;
  1206. fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1207. fusb300->gadget.dev.release = pdev->dev.release;
  1208. fusb300->gadget.name = udc_name;
  1209. fusb300->reg = reg;
  1210. ret = request_irq(ires->start, fusb300_irq, IRQF_DISABLED | IRQF_SHARED,
  1211. udc_name, fusb300);
  1212. if (ret < 0) {
  1213. pr_err("request_irq error (%d)\n", ret);
  1214. goto clean_up;
  1215. }
  1216. ret = request_irq(ires1->start, fusb300_irq,
  1217. IRQF_DISABLED | IRQF_SHARED, udc_name, fusb300);
  1218. if (ret < 0) {
  1219. pr_err("request_irq1 error (%d)\n", ret);
  1220. goto clean_up;
  1221. }
  1222. INIT_LIST_HEAD(&fusb300->gadget.ep_list);
  1223. for (i = 0; i < FUSB300_MAX_NUM_EP ; i++) {
  1224. struct fusb300_ep *ep = fusb300->ep[i];
  1225. if (i != 0) {
  1226. INIT_LIST_HEAD(&fusb300->ep[i]->ep.ep_list);
  1227. list_add_tail(&fusb300->ep[i]->ep.ep_list,
  1228. &fusb300->gadget.ep_list);
  1229. }
  1230. ep->fusb300 = fusb300;
  1231. INIT_LIST_HEAD(&ep->queue);
  1232. ep->ep.name = fusb300_ep_name[i];
  1233. ep->ep.ops = &fusb300_ep_ops;
  1234. ep->ep.maxpacket = HS_BULK_MAX_PACKET_SIZE;
  1235. }
  1236. fusb300->ep[0]->ep.maxpacket = HS_CTL_MAX_PACKET_SIZE;
  1237. fusb300->ep[0]->epnum = 0;
  1238. fusb300->gadget.ep0 = &fusb300->ep[0]->ep;
  1239. INIT_LIST_HEAD(&fusb300->gadget.ep0->ep_list);
  1240. the_controller = fusb300;
  1241. fusb300->ep0_req = fusb300_alloc_request(&fusb300->ep[0]->ep,
  1242. GFP_KERNEL);
  1243. if (fusb300->ep0_req == NULL)
  1244. goto clean_up3;
  1245. init_controller(fusb300);
  1246. ret = usb_add_gadget_udc(&pdev->dev, &fusb300->gadget);
  1247. if (ret)
  1248. goto err_add_udc;
  1249. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1250. return 0;
  1251. err_add_udc:
  1252. fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
  1253. clean_up3:
  1254. free_irq(ires->start, fusb300);
  1255. clean_up:
  1256. if (fusb300) {
  1257. if (fusb300->ep0_req)
  1258. fusb300_free_request(&fusb300->ep[0]->ep,
  1259. fusb300->ep0_req);
  1260. kfree(fusb300);
  1261. }
  1262. if (reg)
  1263. iounmap(reg);
  1264. return ret;
  1265. }
  1266. static struct platform_driver fusb300_driver = {
  1267. .remove = __exit_p(fusb300_remove),
  1268. .driver = {
  1269. .name = (char *) udc_name,
  1270. .owner = THIS_MODULE,
  1271. },
  1272. };
  1273. static int __init fusb300_udc_init(void)
  1274. {
  1275. return platform_driver_probe(&fusb300_driver, fusb300_probe);
  1276. }
  1277. module_init(fusb300_udc_init);
  1278. static void __exit fusb300_udc_cleanup(void)
  1279. {
  1280. platform_driver_unregister(&fusb300_driver);
  1281. }
  1282. module_exit(fusb300_udc_cleanup);