bf5xx-ac97-pcm.c 14 KB

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  1. /*
  2. * File: sound/soc/blackfin/bf5xx-ac97-pcm.c
  3. * Author: Cliff Cai <Cliff.Cai@analog.com>
  4. *
  5. * Created: Tue June 06 2008
  6. * Description: DMA Driver for AC97 sound chip
  7. *
  8. * Modified:
  9. * Copyright 2008 Analog Devices Inc.
  10. *
  11. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, see the file COPYING, or write
  25. * to the Free Software Foundation, Inc.,
  26. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  27. */
  28. #include <linux/module.h>
  29. #include <linux/init.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/gfp.h>
  33. #include <sound/core.h>
  34. #include <sound/pcm.h>
  35. #include <sound/pcm_params.h>
  36. #include <sound/soc.h>
  37. #include <asm/dma.h>
  38. #include "bf5xx-ac97.h"
  39. #include "bf5xx-sport.h"
  40. static unsigned int ac97_chan_mask[] = {
  41. SP_FL, /* Mono */
  42. SP_STEREO, /* Stereo */
  43. SP_2DOT1, /* 2.1*/
  44. SP_QUAD,/*Quadraquic*/
  45. SP_FL | SP_FR | SP_FC | SP_SL | SP_SR,/*5 channels */
  46. SP_5DOT1, /* 5.1 */
  47. };
  48. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  49. static void bf5xx_mmap_copy(struct snd_pcm_substream *substream,
  50. snd_pcm_uframes_t count)
  51. {
  52. struct snd_pcm_runtime *runtime = substream->runtime;
  53. struct sport_device *sport = runtime->private_data;
  54. unsigned int chan_mask = ac97_chan_mask[runtime->channels - 1];
  55. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  56. bf5xx_pcm_to_ac97((struct ac97_frame *)sport->tx_dma_buf +
  57. sport->tx_pos, (__u16 *)runtime->dma_area + sport->tx_pos *
  58. runtime->channels, count, chan_mask);
  59. sport->tx_pos += runtime->period_size;
  60. if (sport->tx_pos >= runtime->buffer_size)
  61. sport->tx_pos %= runtime->buffer_size;
  62. sport->tx_delay_pos = sport->tx_pos;
  63. } else {
  64. bf5xx_ac97_to_pcm((struct ac97_frame *)sport->rx_dma_buf +
  65. sport->rx_pos, (__u16 *)runtime->dma_area + sport->rx_pos *
  66. runtime->channels, count);
  67. sport->rx_pos += runtime->period_size;
  68. if (sport->rx_pos >= runtime->buffer_size)
  69. sport->rx_pos %= runtime->buffer_size;
  70. }
  71. }
  72. #endif
  73. static void bf5xx_dma_irq(void *data)
  74. {
  75. struct snd_pcm_substream *pcm = data;
  76. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  77. struct snd_pcm_runtime *runtime = pcm->runtime;
  78. struct sport_device *sport = runtime->private_data;
  79. bf5xx_mmap_copy(pcm, runtime->period_size);
  80. if (pcm->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  81. if (sport->once == 0) {
  82. snd_pcm_period_elapsed(pcm);
  83. bf5xx_mmap_copy(pcm, runtime->period_size);
  84. sport->once = 1;
  85. }
  86. }
  87. #endif
  88. snd_pcm_period_elapsed(pcm);
  89. }
  90. /* The memory size for pure pcm data is 128*1024 = 0x20000 bytes.
  91. * The total rx/tx buffer is for ac97 frame to hold all pcm data
  92. * is 0x20000 * sizeof(struct ac97_frame) / 4.
  93. */
  94. static const struct snd_pcm_hardware bf5xx_pcm_hardware = {
  95. .info = SNDRV_PCM_INFO_INTERLEAVED |
  96. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  97. SNDRV_PCM_INFO_MMAP |
  98. SNDRV_PCM_INFO_MMAP_VALID |
  99. #endif
  100. SNDRV_PCM_INFO_BLOCK_TRANSFER,
  101. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  102. .period_bytes_min = 32,
  103. .period_bytes_max = 0x10000,
  104. .periods_min = 1,
  105. .periods_max = PAGE_SIZE/32,
  106. .buffer_bytes_max = 0x20000, /* 128 kbytes */
  107. .fifo_size = 16,
  108. };
  109. static int bf5xx_pcm_hw_params(struct snd_pcm_substream *substream,
  110. struct snd_pcm_hw_params *params)
  111. {
  112. size_t size = bf5xx_pcm_hardware.buffer_bytes_max
  113. * sizeof(struct ac97_frame) / 4;
  114. snd_pcm_lib_malloc_pages(substream, size);
  115. return 0;
  116. }
  117. static int bf5xx_pcm_hw_free(struct snd_pcm_substream *substream)
  118. {
  119. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  120. struct snd_pcm_runtime *runtime = substream->runtime;
  121. struct sport_device *sport = runtime->private_data;
  122. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  123. sport->once = 0;
  124. if (runtime->dma_area)
  125. memset(runtime->dma_area, 0, runtime->buffer_size);
  126. memset(sport->tx_dma_buf, 0, runtime->buffer_size *
  127. sizeof(struct ac97_frame));
  128. } else
  129. memset(sport->rx_dma_buf, 0, runtime->buffer_size *
  130. sizeof(struct ac97_frame));
  131. #endif
  132. snd_pcm_lib_free_pages(substream);
  133. return 0;
  134. }
  135. static int bf5xx_pcm_prepare(struct snd_pcm_substream *substream)
  136. {
  137. struct snd_pcm_runtime *runtime = substream->runtime;
  138. struct sport_device *sport = runtime->private_data;
  139. /* An intermediate buffer is introduced for implementing mmap for
  140. * SPORT working in TMD mode(include AC97).
  141. */
  142. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  143. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  144. sport_set_tx_callback(sport, bf5xx_dma_irq, substream);
  145. sport_config_tx_dma(sport, sport->tx_dma_buf, runtime->periods,
  146. runtime->period_size * sizeof(struct ac97_frame));
  147. } else {
  148. sport_set_rx_callback(sport, bf5xx_dma_irq, substream);
  149. sport_config_rx_dma(sport, sport->rx_dma_buf, runtime->periods,
  150. runtime->period_size * sizeof(struct ac97_frame));
  151. }
  152. #else
  153. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  154. sport_set_tx_callback(sport, bf5xx_dma_irq, substream);
  155. sport_config_tx_dma(sport, runtime->dma_area, runtime->periods,
  156. runtime->period_size * sizeof(struct ac97_frame));
  157. } else {
  158. sport_set_rx_callback(sport, bf5xx_dma_irq, substream);
  159. sport_config_rx_dma(sport, runtime->dma_area, runtime->periods,
  160. runtime->period_size * sizeof(struct ac97_frame));
  161. }
  162. #endif
  163. return 0;
  164. }
  165. static int bf5xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  166. {
  167. struct snd_pcm_runtime *runtime = substream->runtime;
  168. struct sport_device *sport = runtime->private_data;
  169. int ret = 0;
  170. pr_debug("%s enter\n", __func__);
  171. switch (cmd) {
  172. case SNDRV_PCM_TRIGGER_START:
  173. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  174. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  175. bf5xx_mmap_copy(substream, runtime->period_size);
  176. sport->tx_delay_pos = 0;
  177. #endif
  178. sport_tx_start(sport);
  179. } else
  180. sport_rx_start(sport);
  181. break;
  182. case SNDRV_PCM_TRIGGER_STOP:
  183. case SNDRV_PCM_TRIGGER_SUSPEND:
  184. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  185. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  186. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  187. sport->tx_pos = 0;
  188. #endif
  189. sport_tx_stop(sport);
  190. } else {
  191. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  192. sport->rx_pos = 0;
  193. #endif
  194. sport_rx_stop(sport);
  195. }
  196. break;
  197. default:
  198. ret = -EINVAL;
  199. }
  200. return ret;
  201. }
  202. static snd_pcm_uframes_t bf5xx_pcm_pointer(struct snd_pcm_substream *substream)
  203. {
  204. struct snd_pcm_runtime *runtime = substream->runtime;
  205. struct sport_device *sport = runtime->private_data;
  206. unsigned int curr;
  207. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  208. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  209. curr = sport->tx_delay_pos;
  210. else
  211. curr = sport->rx_pos;
  212. #else
  213. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  214. curr = sport_curr_offset_tx(sport) / sizeof(struct ac97_frame);
  215. else
  216. curr = sport_curr_offset_rx(sport) / sizeof(struct ac97_frame);
  217. #endif
  218. return curr;
  219. }
  220. static int bf5xx_pcm_open(struct snd_pcm_substream *substream)
  221. {
  222. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  223. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  224. struct sport_device *sport_handle = snd_soc_dai_get_drvdata(cpu_dai);
  225. struct snd_pcm_runtime *runtime = substream->runtime;
  226. int ret;
  227. pr_debug("%s enter\n", __func__);
  228. snd_soc_set_runtime_hwparams(substream, &bf5xx_pcm_hardware);
  229. ret = snd_pcm_hw_constraint_integer(runtime,
  230. SNDRV_PCM_HW_PARAM_PERIODS);
  231. if (ret < 0)
  232. goto out;
  233. if (sport_handle != NULL)
  234. runtime->private_data = sport_handle;
  235. else {
  236. pr_err("sport_handle is NULL\n");
  237. return -1;
  238. }
  239. return 0;
  240. out:
  241. return ret;
  242. }
  243. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  244. static int bf5xx_pcm_mmap(struct snd_pcm_substream *substream,
  245. struct vm_area_struct *vma)
  246. {
  247. struct snd_pcm_runtime *runtime = substream->runtime;
  248. size_t size = vma->vm_end - vma->vm_start;
  249. vma->vm_start = (unsigned long)runtime->dma_area;
  250. vma->vm_end = vma->vm_start + size;
  251. vma->vm_flags |= VM_SHARED;
  252. return 0 ;
  253. }
  254. #else
  255. static int bf5xx_pcm_copy(struct snd_pcm_substream *substream, int channel,
  256. snd_pcm_uframes_t pos,
  257. void __user *buf, snd_pcm_uframes_t count)
  258. {
  259. struct snd_pcm_runtime *runtime = substream->runtime;
  260. unsigned int chan_mask = ac97_chan_mask[runtime->channels - 1];
  261. pr_debug("%s copy pos:0x%lx count:0x%lx\n",
  262. substream->stream ? "Capture" : "Playback", pos, count);
  263. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  264. bf5xx_pcm_to_ac97((struct ac97_frame *)runtime->dma_area + pos,
  265. (__u16 *)buf, count, chan_mask);
  266. else
  267. bf5xx_ac97_to_pcm((struct ac97_frame *)runtime->dma_area + pos,
  268. (__u16 *)buf, count);
  269. return 0;
  270. }
  271. #endif
  272. static struct snd_pcm_ops bf5xx_pcm_ac97_ops = {
  273. .open = bf5xx_pcm_open,
  274. .ioctl = snd_pcm_lib_ioctl,
  275. .hw_params = bf5xx_pcm_hw_params,
  276. .hw_free = bf5xx_pcm_hw_free,
  277. .prepare = bf5xx_pcm_prepare,
  278. .trigger = bf5xx_pcm_trigger,
  279. .pointer = bf5xx_pcm_pointer,
  280. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  281. .mmap = bf5xx_pcm_mmap,
  282. #else
  283. .copy = bf5xx_pcm_copy,
  284. #endif
  285. };
  286. static int bf5xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
  287. {
  288. struct snd_soc_pcm_runtime *rtd = pcm->private_data;
  289. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  290. struct sport_device *sport_handle = snd_soc_dai_get_drvdata(cpu_dai);
  291. struct snd_pcm_substream *substream = pcm->streams[stream].substream;
  292. struct snd_dma_buffer *buf = &substream->dma_buffer;
  293. size_t size = bf5xx_pcm_hardware.buffer_bytes_max
  294. * sizeof(struct ac97_frame) / 4;
  295. buf->dev.type = SNDRV_DMA_TYPE_DEV;
  296. buf->dev.dev = pcm->card->dev;
  297. buf->private_data = NULL;
  298. buf->area = dma_alloc_coherent(pcm->card->dev, size,
  299. &buf->addr, GFP_KERNEL);
  300. if (!buf->area) {
  301. pr_err("Failed to allocate dma memory\n");
  302. pr_err("Please increase uncached DMA memory region\n");
  303. return -ENOMEM;
  304. }
  305. buf->bytes = size;
  306. pr_debug("%s, area:%p, size:0x%08lx\n", __func__,
  307. buf->area, buf->bytes);
  308. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  309. sport_handle->tx_buf = buf->area;
  310. else
  311. sport_handle->rx_buf = buf->area;
  312. /*
  313. * Need to allocate local buffer when enable
  314. * MMAP for SPORT working in TMD mode (include AC97).
  315. */
  316. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  317. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  318. if (!sport_handle->tx_dma_buf) {
  319. sport_handle->tx_dma_buf = dma_alloc_coherent(NULL, \
  320. size, &sport_handle->tx_dma_phy, GFP_KERNEL);
  321. if (!sport_handle->tx_dma_buf) {
  322. pr_err("Failed to allocate memory for tx dma buf - Please increase uncached DMA memory region\n");
  323. return -ENOMEM;
  324. } else
  325. memset(sport_handle->tx_dma_buf, 0, size);
  326. } else
  327. memset(sport_handle->tx_dma_buf, 0, size);
  328. } else {
  329. if (!sport_handle->rx_dma_buf) {
  330. sport_handle->rx_dma_buf = dma_alloc_coherent(NULL, \
  331. size, &sport_handle->rx_dma_phy, GFP_KERNEL);
  332. if (!sport_handle->rx_dma_buf) {
  333. pr_err("Failed to allocate memory for rx dma buf - Please increase uncached DMA memory region\n");
  334. return -ENOMEM;
  335. } else
  336. memset(sport_handle->rx_dma_buf, 0, size);
  337. } else
  338. memset(sport_handle->rx_dma_buf, 0, size);
  339. }
  340. #endif
  341. return 0;
  342. }
  343. static void bf5xx_pcm_free_dma_buffers(struct snd_pcm *pcm)
  344. {
  345. struct snd_pcm_substream *substream;
  346. struct snd_dma_buffer *buf;
  347. int stream;
  348. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  349. struct snd_soc_pcm_runtime *rtd = pcm->private_data;
  350. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  351. struct sport_device *sport_handle = snd_soc_dai_get_drvdata(cpu_dai);
  352. size_t size = bf5xx_pcm_hardware.buffer_bytes_max *
  353. sizeof(struct ac97_frame) / 4;
  354. #endif
  355. for (stream = 0; stream < 2; stream++) {
  356. substream = pcm->streams[stream].substream;
  357. if (!substream)
  358. continue;
  359. buf = &substream->dma_buffer;
  360. if (!buf->area)
  361. continue;
  362. dma_free_coherent(NULL, buf->bytes, buf->area, 0);
  363. buf->area = NULL;
  364. #if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
  365. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  366. if (sport_handle->tx_dma_buf)
  367. dma_free_coherent(NULL, size, \
  368. sport_handle->tx_dma_buf, 0);
  369. sport_handle->tx_dma_buf = NULL;
  370. } else {
  371. if (sport_handle->rx_dma_buf)
  372. dma_free_coherent(NULL, size, \
  373. sport_handle->rx_dma_buf, 0);
  374. sport_handle->rx_dma_buf = NULL;
  375. }
  376. #endif
  377. }
  378. }
  379. static u64 bf5xx_pcm_dmamask = DMA_BIT_MASK(32);
  380. static int bf5xx_pcm_ac97_new(struct snd_soc_pcm_runtime *rtd)
  381. {
  382. struct snd_card *card = rtd->card->snd_card;
  383. struct snd_pcm *pcm = rtd->pcm;
  384. int ret = 0;
  385. pr_debug("%s enter\n", __func__);
  386. if (!card->dev->dma_mask)
  387. card->dev->dma_mask = &bf5xx_pcm_dmamask;
  388. if (!card->dev->coherent_dma_mask)
  389. card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
  390. if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
  391. ret = bf5xx_pcm_preallocate_dma_buffer(pcm,
  392. SNDRV_PCM_STREAM_PLAYBACK);
  393. if (ret)
  394. goto out;
  395. }
  396. if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
  397. ret = bf5xx_pcm_preallocate_dma_buffer(pcm,
  398. SNDRV_PCM_STREAM_CAPTURE);
  399. if (ret)
  400. goto out;
  401. }
  402. out:
  403. return ret;
  404. }
  405. static struct snd_soc_platform_driver bf5xx_ac97_soc_platform = {
  406. .ops = &bf5xx_pcm_ac97_ops,
  407. .pcm_new = bf5xx_pcm_ac97_new,
  408. .pcm_free = bf5xx_pcm_free_dma_buffers,
  409. };
  410. static int bf5xx_soc_platform_probe(struct platform_device *pdev)
  411. {
  412. return snd_soc_register_platform(&pdev->dev, &bf5xx_ac97_soc_platform);
  413. }
  414. static int bf5xx_soc_platform_remove(struct platform_device *pdev)
  415. {
  416. snd_soc_unregister_platform(&pdev->dev);
  417. return 0;
  418. }
  419. static struct platform_driver bf5xx_pcm_driver = {
  420. .driver = {
  421. .name = "bfin-ac97-pcm-audio",
  422. .owner = THIS_MODULE,
  423. },
  424. .probe = bf5xx_soc_platform_probe,
  425. .remove = bf5xx_soc_platform_remove,
  426. };
  427. module_platform_driver(bf5xx_pcm_driver);
  428. MODULE_AUTHOR("Cliff Cai");
  429. MODULE_DESCRIPTION("ADI Blackfin AC97 PCM DMA module");
  430. MODULE_LICENSE("GPL");