atmel_lcdfb.c 34 KB

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  1. /*
  2. * Driver for AT91/AT32 LCD Controller
  3. *
  4. * Copyright (C) 2007 Atmel Corporation
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file COPYING in the main directory of this archive for
  8. * more details.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/clk.h>
  15. #include <linux/fb.h>
  16. #include <linux/init.h>
  17. #include <linux/delay.h>
  18. #include <linux/backlight.h>
  19. #include <linux/gfp.h>
  20. #include <linux/module.h>
  21. #include <linux/platform_data/atmel.h>
  22. #include <mach/cpu.h>
  23. #include <asm/gpio.h>
  24. #include <video/atmel_lcdc.h>
  25. #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
  26. #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
  27. /* configurable parameters */
  28. #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
  29. #define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */
  30. #define ATMEL_LCDC_FIFO_SIZE 512 /* words */
  31. struct atmel_lcdfb_config {
  32. bool have_alt_pixclock;
  33. bool have_hozval;
  34. bool have_intensity_bit;
  35. };
  36. static struct atmel_lcdfb_config at91sam9261_config = {
  37. .have_hozval = true,
  38. .have_intensity_bit = true,
  39. };
  40. static struct atmel_lcdfb_config at91sam9263_config = {
  41. .have_intensity_bit = true,
  42. };
  43. static struct atmel_lcdfb_config at91sam9g10_config = {
  44. .have_hozval = true,
  45. };
  46. static struct atmel_lcdfb_config at91sam9g45_config = {
  47. .have_alt_pixclock = true,
  48. };
  49. static struct atmel_lcdfb_config at91sam9g45es_config = {
  50. };
  51. static struct atmel_lcdfb_config at91sam9rl_config = {
  52. .have_intensity_bit = true,
  53. };
  54. static struct atmel_lcdfb_config at32ap_config = {
  55. .have_hozval = true,
  56. };
  57. static const struct platform_device_id atmel_lcdfb_devtypes[] = {
  58. {
  59. .name = "at91sam9261-lcdfb",
  60. .driver_data = (unsigned long)&at91sam9261_config,
  61. }, {
  62. .name = "at91sam9263-lcdfb",
  63. .driver_data = (unsigned long)&at91sam9263_config,
  64. }, {
  65. .name = "at91sam9g10-lcdfb",
  66. .driver_data = (unsigned long)&at91sam9g10_config,
  67. }, {
  68. .name = "at91sam9g45-lcdfb",
  69. .driver_data = (unsigned long)&at91sam9g45_config,
  70. }, {
  71. .name = "at91sam9g45es-lcdfb",
  72. .driver_data = (unsigned long)&at91sam9g45es_config,
  73. }, {
  74. .name = "at91sam9rl-lcdfb",
  75. .driver_data = (unsigned long)&at91sam9rl_config,
  76. }, {
  77. .name = "at32ap-lcdfb",
  78. .driver_data = (unsigned long)&at32ap_config,
  79. }, {
  80. /* terminator */
  81. }
  82. };
  83. static struct atmel_lcdfb_config *
  84. atmel_lcdfb_get_config(struct platform_device *pdev)
  85. {
  86. unsigned long data;
  87. data = platform_get_device_id(pdev)->driver_data;
  88. return (struct atmel_lcdfb_config *)data;
  89. }
  90. #if defined(CONFIG_ARCH_AT91)
  91. #define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
  92. | FBINFO_PARTIAL_PAN_OK \
  93. | FBINFO_HWACCEL_YPAN)
  94. static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
  95. struct fb_var_screeninfo *var,
  96. struct fb_info *info)
  97. {
  98. }
  99. #elif defined(CONFIG_AVR32)
  100. #define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
  101. | FBINFO_PARTIAL_PAN_OK \
  102. | FBINFO_HWACCEL_XPAN \
  103. | FBINFO_HWACCEL_YPAN)
  104. static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
  105. struct fb_var_screeninfo *var,
  106. struct fb_info *info)
  107. {
  108. u32 dma2dcfg;
  109. u32 pixeloff;
  110. pixeloff = (var->xoffset * info->var.bits_per_pixel) & 0x1f;
  111. dma2dcfg = (info->var.xres_virtual - info->var.xres)
  112. * info->var.bits_per_pixel / 8;
  113. dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
  114. lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
  115. /* Update configuration */
  116. lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
  117. lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
  118. | ATMEL_LCDC_DMAUPDT);
  119. }
  120. #endif
  121. static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
  122. | ATMEL_LCDC_POL_POSITIVE
  123. | ATMEL_LCDC_ENA_PWMENABLE;
  124. #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
  125. /* some bl->props field just changed */
  126. static int atmel_bl_update_status(struct backlight_device *bl)
  127. {
  128. struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
  129. int power = sinfo->bl_power;
  130. int brightness = bl->props.brightness;
  131. /* REVISIT there may be a meaningful difference between
  132. * fb_blank and power ... there seem to be some cases
  133. * this doesn't handle correctly.
  134. */
  135. if (bl->props.fb_blank != sinfo->bl_power)
  136. power = bl->props.fb_blank;
  137. else if (bl->props.power != sinfo->bl_power)
  138. power = bl->props.power;
  139. if (brightness < 0 && power == FB_BLANK_UNBLANK)
  140. brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
  141. else if (power != FB_BLANK_UNBLANK)
  142. brightness = 0;
  143. lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
  144. if (contrast_ctr & ATMEL_LCDC_POL_POSITIVE)
  145. lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
  146. brightness ? contrast_ctr : 0);
  147. else
  148. lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
  149. bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
  150. return 0;
  151. }
  152. static int atmel_bl_get_brightness(struct backlight_device *bl)
  153. {
  154. struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
  155. return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
  156. }
  157. static const struct backlight_ops atmel_lcdc_bl_ops = {
  158. .update_status = atmel_bl_update_status,
  159. .get_brightness = atmel_bl_get_brightness,
  160. };
  161. static void init_backlight(struct atmel_lcdfb_info *sinfo)
  162. {
  163. struct backlight_properties props;
  164. struct backlight_device *bl;
  165. sinfo->bl_power = FB_BLANK_UNBLANK;
  166. if (sinfo->backlight)
  167. return;
  168. memset(&props, 0, sizeof(struct backlight_properties));
  169. props.type = BACKLIGHT_RAW;
  170. props.max_brightness = 0xff;
  171. bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo,
  172. &atmel_lcdc_bl_ops, &props);
  173. if (IS_ERR(bl)) {
  174. dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
  175. PTR_ERR(bl));
  176. return;
  177. }
  178. sinfo->backlight = bl;
  179. bl->props.power = FB_BLANK_UNBLANK;
  180. bl->props.fb_blank = FB_BLANK_UNBLANK;
  181. bl->props.brightness = atmel_bl_get_brightness(bl);
  182. }
  183. static void exit_backlight(struct atmel_lcdfb_info *sinfo)
  184. {
  185. if (!sinfo->backlight)
  186. return;
  187. if (sinfo->backlight->ops) {
  188. sinfo->backlight->props.power = FB_BLANK_POWERDOWN;
  189. sinfo->backlight->ops->update_status(sinfo->backlight);
  190. }
  191. backlight_device_unregister(sinfo->backlight);
  192. }
  193. #else
  194. static void init_backlight(struct atmel_lcdfb_info *sinfo)
  195. {
  196. dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
  197. }
  198. static void exit_backlight(struct atmel_lcdfb_info *sinfo)
  199. {
  200. }
  201. #endif
  202. static void init_contrast(struct atmel_lcdfb_info *sinfo)
  203. {
  204. /* contrast pwm can be 'inverted' */
  205. if (sinfo->lcdcon_pol_negative)
  206. contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
  207. /* have some default contrast/backlight settings */
  208. lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
  209. lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
  210. if (sinfo->lcdcon_is_backlight)
  211. init_backlight(sinfo);
  212. }
  213. static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
  214. .type = FB_TYPE_PACKED_PIXELS,
  215. .visual = FB_VISUAL_TRUECOLOR,
  216. .xpanstep = 0,
  217. .ypanstep = 1,
  218. .ywrapstep = 0,
  219. .accel = FB_ACCEL_NONE,
  220. };
  221. static unsigned long compute_hozval(struct atmel_lcdfb_info *sinfo,
  222. unsigned long xres)
  223. {
  224. unsigned long lcdcon2;
  225. unsigned long value;
  226. if (!sinfo->config->have_hozval)
  227. return xres;
  228. lcdcon2 = lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2);
  229. value = xres;
  230. if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
  231. /* STN display */
  232. if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
  233. value *= 3;
  234. }
  235. if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
  236. || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
  237. && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
  238. value = DIV_ROUND_UP(value, 4);
  239. else
  240. value = DIV_ROUND_UP(value, 8);
  241. }
  242. return value;
  243. }
  244. static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
  245. {
  246. /* Turn off the LCD controller and the DMA controller */
  247. lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
  248. sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
  249. /* Wait for the LCDC core to become idle */
  250. while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
  251. msleep(10);
  252. lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
  253. }
  254. static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
  255. {
  256. atmel_lcdfb_stop_nowait(sinfo);
  257. /* Wait for DMA engine to become idle... */
  258. while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
  259. msleep(10);
  260. }
  261. static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
  262. {
  263. lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
  264. lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
  265. (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
  266. | ATMEL_LCDC_PWR);
  267. }
  268. static void atmel_lcdfb_update_dma(struct fb_info *info,
  269. struct fb_var_screeninfo *var)
  270. {
  271. struct atmel_lcdfb_info *sinfo = info->par;
  272. struct fb_fix_screeninfo *fix = &info->fix;
  273. unsigned long dma_addr;
  274. dma_addr = (fix->smem_start + var->yoffset * fix->line_length
  275. + var->xoffset * info->var.bits_per_pixel / 8);
  276. dma_addr &= ~3UL;
  277. /* Set framebuffer DMA base address and pixel offset */
  278. lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
  279. atmel_lcdfb_update_dma2d(sinfo, var, info);
  280. }
  281. static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
  282. {
  283. struct fb_info *info = sinfo->info;
  284. dma_free_writecombine(info->device, info->fix.smem_len,
  285. info->screen_base, info->fix.smem_start);
  286. }
  287. /**
  288. * atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
  289. * @sinfo: the frame buffer to allocate memory for
  290. *
  291. * This function is called only from the atmel_lcdfb_probe()
  292. * so no locking by fb_info->mm_lock around smem_len setting is needed.
  293. */
  294. static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
  295. {
  296. struct fb_info *info = sinfo->info;
  297. struct fb_var_screeninfo *var = &info->var;
  298. unsigned int smem_len;
  299. smem_len = (var->xres_virtual * var->yres_virtual
  300. * ((var->bits_per_pixel + 7) / 8));
  301. info->fix.smem_len = max(smem_len, sinfo->smem_len);
  302. info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len,
  303. (dma_addr_t *)&info->fix.smem_start, GFP_KERNEL);
  304. if (!info->screen_base) {
  305. return -ENOMEM;
  306. }
  307. memset(info->screen_base, 0, info->fix.smem_len);
  308. return 0;
  309. }
  310. static const struct fb_videomode *atmel_lcdfb_choose_mode(struct fb_var_screeninfo *var,
  311. struct fb_info *info)
  312. {
  313. struct fb_videomode varfbmode;
  314. const struct fb_videomode *fbmode = NULL;
  315. fb_var_to_videomode(&varfbmode, var);
  316. fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist);
  317. if (fbmode)
  318. fb_videomode_to_var(var, fbmode);
  319. return fbmode;
  320. }
  321. /**
  322. * atmel_lcdfb_check_var - Validates a var passed in.
  323. * @var: frame buffer variable screen structure
  324. * @info: frame buffer structure that represents a single frame buffer
  325. *
  326. * Checks to see if the hardware supports the state requested by
  327. * var passed in. This function does not alter the hardware
  328. * state!!! This means the data stored in struct fb_info and
  329. * struct atmel_lcdfb_info do not change. This includes the var
  330. * inside of struct fb_info. Do NOT change these. This function
  331. * can be called on its own if we intent to only test a mode and
  332. * not actually set it. The stuff in modedb.c is a example of
  333. * this. If the var passed in is slightly off by what the
  334. * hardware can support then we alter the var PASSED in to what
  335. * we can do. If the hardware doesn't support mode change a
  336. * -EINVAL will be returned by the upper layers. You don't need
  337. * to implement this function then. If you hardware doesn't
  338. * support changing the resolution then this function is not
  339. * needed. In this case the driver would just provide a var that
  340. * represents the static state the screen is in.
  341. *
  342. * Returns negative errno on error, or zero on success.
  343. */
  344. static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
  345. struct fb_info *info)
  346. {
  347. struct device *dev = info->device;
  348. struct atmel_lcdfb_info *sinfo = info->par;
  349. unsigned long clk_value_khz;
  350. clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
  351. dev_dbg(dev, "%s:\n", __func__);
  352. if (!(var->pixclock && var->bits_per_pixel)) {
  353. /* choose a suitable mode if possible */
  354. if (!atmel_lcdfb_choose_mode(var, info)) {
  355. dev_err(dev, "needed value not specified\n");
  356. return -EINVAL;
  357. }
  358. }
  359. dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres);
  360. dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock));
  361. dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel);
  362. dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz);
  363. if (PICOS2KHZ(var->pixclock) > clk_value_khz) {
  364. dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
  365. return -EINVAL;
  366. }
  367. /* Do not allow to have real resoulution larger than virtual */
  368. if (var->xres > var->xres_virtual)
  369. var->xres_virtual = var->xres;
  370. if (var->yres > var->yres_virtual)
  371. var->yres_virtual = var->yres;
  372. /* Force same alignment for each line */
  373. var->xres = (var->xres + 3) & ~3UL;
  374. var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
  375. var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
  376. var->transp.msb_right = 0;
  377. var->transp.offset = var->transp.length = 0;
  378. var->xoffset = var->yoffset = 0;
  379. if (info->fix.smem_len) {
  380. unsigned int smem_len = (var->xres_virtual * var->yres_virtual
  381. * ((var->bits_per_pixel + 7) / 8));
  382. if (smem_len > info->fix.smem_len) {
  383. dev_err(dev, "Frame buffer is too small (%u) for screen size (need at least %u)\n",
  384. info->fix.smem_len, smem_len);
  385. return -EINVAL;
  386. }
  387. }
  388. /* Saturate vertical and horizontal timings at maximum values */
  389. var->vsync_len = min_t(u32, var->vsync_len,
  390. (ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
  391. var->upper_margin = min_t(u32, var->upper_margin,
  392. ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
  393. var->lower_margin = min_t(u32, var->lower_margin,
  394. ATMEL_LCDC_VFP);
  395. var->right_margin = min_t(u32, var->right_margin,
  396. (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
  397. var->hsync_len = min_t(u32, var->hsync_len,
  398. (ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
  399. var->left_margin = min_t(u32, var->left_margin,
  400. ATMEL_LCDC_HBP + 1);
  401. /* Some parameters can't be zero */
  402. var->vsync_len = max_t(u32, var->vsync_len, 1);
  403. var->right_margin = max_t(u32, var->right_margin, 1);
  404. var->hsync_len = max_t(u32, var->hsync_len, 1);
  405. var->left_margin = max_t(u32, var->left_margin, 1);
  406. switch (var->bits_per_pixel) {
  407. case 1:
  408. case 2:
  409. case 4:
  410. case 8:
  411. var->red.offset = var->green.offset = var->blue.offset = 0;
  412. var->red.length = var->green.length = var->blue.length
  413. = var->bits_per_pixel;
  414. break;
  415. case 16:
  416. /* Older SOCs use IBGR:555 rather than BGR:565. */
  417. if (sinfo->config->have_intensity_bit)
  418. var->green.length = 5;
  419. else
  420. var->green.length = 6;
  421. if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
  422. /* RGB:5X5 mode */
  423. var->red.offset = var->green.length + 5;
  424. var->blue.offset = 0;
  425. } else {
  426. /* BGR:5X5 mode */
  427. var->red.offset = 0;
  428. var->blue.offset = var->green.length + 5;
  429. }
  430. var->green.offset = 5;
  431. var->red.length = var->blue.length = 5;
  432. break;
  433. case 32:
  434. var->transp.offset = 24;
  435. var->transp.length = 8;
  436. /* fall through */
  437. case 24:
  438. if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
  439. /* RGB:888 mode */
  440. var->red.offset = 16;
  441. var->blue.offset = 0;
  442. } else {
  443. /* BGR:888 mode */
  444. var->red.offset = 0;
  445. var->blue.offset = 16;
  446. }
  447. var->green.offset = 8;
  448. var->red.length = var->green.length = var->blue.length = 8;
  449. break;
  450. default:
  451. dev_err(dev, "color depth %d not supported\n",
  452. var->bits_per_pixel);
  453. return -EINVAL;
  454. }
  455. return 0;
  456. }
  457. /*
  458. * LCD reset sequence
  459. */
  460. static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
  461. {
  462. might_sleep();
  463. atmel_lcdfb_stop(sinfo);
  464. atmel_lcdfb_start(sinfo);
  465. }
  466. /**
  467. * atmel_lcdfb_set_par - Alters the hardware state.
  468. * @info: frame buffer structure that represents a single frame buffer
  469. *
  470. * Using the fb_var_screeninfo in fb_info we set the resolution
  471. * of the this particular framebuffer. This function alters the
  472. * par AND the fb_fix_screeninfo stored in fb_info. It doesn't
  473. * not alter var in fb_info since we are using that data. This
  474. * means we depend on the data in var inside fb_info to be
  475. * supported by the hardware. atmel_lcdfb_check_var is always called
  476. * before atmel_lcdfb_set_par to ensure this. Again if you can't
  477. * change the resolution you don't need this function.
  478. *
  479. */
  480. static int atmel_lcdfb_set_par(struct fb_info *info)
  481. {
  482. struct atmel_lcdfb_info *sinfo = info->par;
  483. unsigned long hozval_linesz;
  484. unsigned long value;
  485. unsigned long clk_value_khz;
  486. unsigned long bits_per_line;
  487. unsigned long pix_factor = 2;
  488. might_sleep();
  489. dev_dbg(info->device, "%s:\n", __func__);
  490. dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
  491. info->var.xres, info->var.yres,
  492. info->var.xres_virtual, info->var.yres_virtual);
  493. atmel_lcdfb_stop_nowait(sinfo);
  494. if (info->var.bits_per_pixel == 1)
  495. info->fix.visual = FB_VISUAL_MONO01;
  496. else if (info->var.bits_per_pixel <= 8)
  497. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  498. else
  499. info->fix.visual = FB_VISUAL_TRUECOLOR;
  500. bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
  501. info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
  502. /* Re-initialize the DMA engine... */
  503. dev_dbg(info->device, " * update DMA engine\n");
  504. atmel_lcdfb_update_dma(info, &info->var);
  505. /* ...set frame size and burst length = 8 words (?) */
  506. value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
  507. value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
  508. lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
  509. /* Now, the LCDC core... */
  510. /* Set pixel clock */
  511. if (sinfo->config->have_alt_pixclock)
  512. pix_factor = 1;
  513. clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
  514. value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
  515. if (value < pix_factor) {
  516. dev_notice(info->device, "Bypassing pixel clock divider\n");
  517. lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
  518. } else {
  519. value = (value / pix_factor) - 1;
  520. dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n",
  521. value);
  522. lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
  523. value << ATMEL_LCDC_CLKVAL_OFFSET);
  524. info->var.pixclock =
  525. KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
  526. dev_dbg(info->device, " updated pixclk: %lu KHz\n",
  527. PICOS2KHZ(info->var.pixclock));
  528. }
  529. /* Initialize control register 2 */
  530. value = sinfo->default_lcdcon2;
  531. if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
  532. value |= ATMEL_LCDC_INVLINE_INVERTED;
  533. if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
  534. value |= ATMEL_LCDC_INVFRAME_INVERTED;
  535. switch (info->var.bits_per_pixel) {
  536. case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break;
  537. case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
  538. case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
  539. case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
  540. case 15: /* fall through */
  541. case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
  542. case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
  543. case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
  544. default: BUG(); break;
  545. }
  546. dev_dbg(info->device, " * LCDCON2 = %08lx\n", value);
  547. lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
  548. /* Vertical timing */
  549. value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
  550. value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
  551. value |= info->var.lower_margin;
  552. dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value);
  553. lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
  554. /* Horizontal timing */
  555. value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
  556. value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
  557. value |= (info->var.left_margin - 1);
  558. dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
  559. lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
  560. /* Horizontal value (aka line size) */
  561. hozval_linesz = compute_hozval(sinfo, info->var.xres);
  562. /* Display size */
  563. value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
  564. value |= info->var.yres - 1;
  565. dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value);
  566. lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
  567. /* FIFO Threshold: Use formula from data sheet */
  568. value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
  569. lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
  570. /* Toggle LCD_MODE every frame */
  571. lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
  572. /* Disable all interrupts */
  573. lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
  574. /* Enable FIFO & DMA errors */
  575. lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
  576. /* ...wait for DMA engine to become idle... */
  577. while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
  578. msleep(10);
  579. atmel_lcdfb_start(sinfo);
  580. dev_dbg(info->device, " * DONE\n");
  581. return 0;
  582. }
  583. static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
  584. {
  585. chan &= 0xffff;
  586. chan >>= 16 - bf->length;
  587. return chan << bf->offset;
  588. }
  589. /**
  590. * atmel_lcdfb_setcolreg - Optional function. Sets a color register.
  591. * @regno: Which register in the CLUT we are programming
  592. * @red: The red value which can be up to 16 bits wide
  593. * @green: The green value which can be up to 16 bits wide
  594. * @blue: The blue value which can be up to 16 bits wide.
  595. * @transp: If supported the alpha value which can be up to 16 bits wide.
  596. * @info: frame buffer info structure
  597. *
  598. * Set a single color register. The values supplied have a 16 bit
  599. * magnitude which needs to be scaled in this function for the hardware.
  600. * Things to take into consideration are how many color registers, if
  601. * any, are supported with the current color visual. With truecolor mode
  602. * no color palettes are supported. Here a pseudo palette is created
  603. * which we store the value in pseudo_palette in struct fb_info. For
  604. * pseudocolor mode we have a limited color palette. To deal with this
  605. * we can program what color is displayed for a particular pixel value.
  606. * DirectColor is similar in that we can program each color field. If
  607. * we have a static colormap we don't need to implement this function.
  608. *
  609. * Returns negative errno on error, or zero on success. In an
  610. * ideal world, this would have been the case, but as it turns
  611. * out, the other drivers return 1 on failure, so that's what
  612. * we're going to do.
  613. */
  614. static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
  615. unsigned int green, unsigned int blue,
  616. unsigned int transp, struct fb_info *info)
  617. {
  618. struct atmel_lcdfb_info *sinfo = info->par;
  619. unsigned int val;
  620. u32 *pal;
  621. int ret = 1;
  622. if (info->var.grayscale)
  623. red = green = blue = (19595 * red + 38470 * green
  624. + 7471 * blue) >> 16;
  625. switch (info->fix.visual) {
  626. case FB_VISUAL_TRUECOLOR:
  627. if (regno < 16) {
  628. pal = info->pseudo_palette;
  629. val = chan_to_field(red, &info->var.red);
  630. val |= chan_to_field(green, &info->var.green);
  631. val |= chan_to_field(blue, &info->var.blue);
  632. pal[regno] = val;
  633. ret = 0;
  634. }
  635. break;
  636. case FB_VISUAL_PSEUDOCOLOR:
  637. if (regno < 256) {
  638. if (sinfo->config->have_intensity_bit) {
  639. /* old style I+BGR:555 */
  640. val = ((red >> 11) & 0x001f);
  641. val |= ((green >> 6) & 0x03e0);
  642. val |= ((blue >> 1) & 0x7c00);
  643. /*
  644. * TODO: intensity bit. Maybe something like
  645. * ~(red[10] ^ green[10] ^ blue[10]) & 1
  646. */
  647. } else {
  648. /* new style BGR:565 / RGB:565 */
  649. if (sinfo->lcd_wiring_mode ==
  650. ATMEL_LCDC_WIRING_RGB) {
  651. val = ((blue >> 11) & 0x001f);
  652. val |= ((red >> 0) & 0xf800);
  653. } else {
  654. val = ((red >> 11) & 0x001f);
  655. val |= ((blue >> 0) & 0xf800);
  656. }
  657. val |= ((green >> 5) & 0x07e0);
  658. }
  659. lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
  660. ret = 0;
  661. }
  662. break;
  663. case FB_VISUAL_MONO01:
  664. if (regno < 2) {
  665. val = (regno == 0) ? 0x00 : 0x1F;
  666. lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
  667. ret = 0;
  668. }
  669. break;
  670. }
  671. return ret;
  672. }
  673. static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
  674. struct fb_info *info)
  675. {
  676. dev_dbg(info->device, "%s\n", __func__);
  677. atmel_lcdfb_update_dma(info, var);
  678. return 0;
  679. }
  680. static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info)
  681. {
  682. struct atmel_lcdfb_info *sinfo = info->par;
  683. switch (blank_mode) {
  684. case FB_BLANK_UNBLANK:
  685. case FB_BLANK_NORMAL:
  686. atmel_lcdfb_start(sinfo);
  687. break;
  688. case FB_BLANK_VSYNC_SUSPEND:
  689. case FB_BLANK_HSYNC_SUSPEND:
  690. break;
  691. case FB_BLANK_POWERDOWN:
  692. atmel_lcdfb_stop(sinfo);
  693. break;
  694. default:
  695. return -EINVAL;
  696. }
  697. /* let fbcon do a soft blank for us */
  698. return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
  699. }
  700. static struct fb_ops atmel_lcdfb_ops = {
  701. .owner = THIS_MODULE,
  702. .fb_check_var = atmel_lcdfb_check_var,
  703. .fb_set_par = atmel_lcdfb_set_par,
  704. .fb_setcolreg = atmel_lcdfb_setcolreg,
  705. .fb_blank = atmel_lcdfb_blank,
  706. .fb_pan_display = atmel_lcdfb_pan_display,
  707. .fb_fillrect = cfb_fillrect,
  708. .fb_copyarea = cfb_copyarea,
  709. .fb_imageblit = cfb_imageblit,
  710. };
  711. static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
  712. {
  713. struct fb_info *info = dev_id;
  714. struct atmel_lcdfb_info *sinfo = info->par;
  715. u32 status;
  716. status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
  717. if (status & ATMEL_LCDC_UFLWI) {
  718. dev_warn(info->device, "FIFO underflow %#x\n", status);
  719. /* reset DMA and FIFO to avoid screen shifting */
  720. schedule_work(&sinfo->task);
  721. }
  722. lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
  723. return IRQ_HANDLED;
  724. }
  725. /*
  726. * LCD controller task (to reset the LCD)
  727. */
  728. static void atmel_lcdfb_task(struct work_struct *work)
  729. {
  730. struct atmel_lcdfb_info *sinfo =
  731. container_of(work, struct atmel_lcdfb_info, task);
  732. atmel_lcdfb_reset(sinfo);
  733. }
  734. static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
  735. {
  736. struct fb_info *info = sinfo->info;
  737. int ret = 0;
  738. info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
  739. dev_info(info->device,
  740. "%luKiB frame buffer at %08lx (mapped at %p)\n",
  741. (unsigned long)info->fix.smem_len / 1024,
  742. (unsigned long)info->fix.smem_start,
  743. info->screen_base);
  744. /* Allocate colormap */
  745. ret = fb_alloc_cmap(&info->cmap, 256, 0);
  746. if (ret < 0)
  747. dev_err(info->device, "Alloc color map failed\n");
  748. return ret;
  749. }
  750. static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
  751. {
  752. clk_prepare_enable(sinfo->bus_clk);
  753. clk_prepare_enable(sinfo->lcdc_clk);
  754. }
  755. static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
  756. {
  757. clk_disable_unprepare(sinfo->bus_clk);
  758. clk_disable_unprepare(sinfo->lcdc_clk);
  759. }
  760. static int __init atmel_lcdfb_probe(struct platform_device *pdev)
  761. {
  762. struct device *dev = &pdev->dev;
  763. struct fb_info *info;
  764. struct atmel_lcdfb_info *sinfo;
  765. struct atmel_lcdfb_info *pdata_sinfo;
  766. struct fb_videomode fbmode;
  767. struct resource *regs = NULL;
  768. struct resource *map = NULL;
  769. int ret;
  770. dev_dbg(dev, "%s BEGIN\n", __func__);
  771. ret = -ENOMEM;
  772. info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
  773. if (!info) {
  774. dev_err(dev, "cannot allocate memory\n");
  775. goto out;
  776. }
  777. sinfo = info->par;
  778. if (dev->platform_data) {
  779. pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data;
  780. sinfo->default_bpp = pdata_sinfo->default_bpp;
  781. sinfo->default_dmacon = pdata_sinfo->default_dmacon;
  782. sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2;
  783. sinfo->default_monspecs = pdata_sinfo->default_monspecs;
  784. sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control;
  785. sinfo->guard_time = pdata_sinfo->guard_time;
  786. sinfo->smem_len = pdata_sinfo->smem_len;
  787. sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight;
  788. sinfo->lcdcon_pol_negative = pdata_sinfo->lcdcon_pol_negative;
  789. sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode;
  790. } else {
  791. dev_err(dev, "cannot get default configuration\n");
  792. goto free_info;
  793. }
  794. sinfo->info = info;
  795. sinfo->pdev = pdev;
  796. sinfo->config = atmel_lcdfb_get_config(pdev);
  797. if (!sinfo->config)
  798. goto free_info;
  799. strcpy(info->fix.id, sinfo->pdev->name);
  800. info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
  801. info->pseudo_palette = sinfo->pseudo_palette;
  802. info->fbops = &atmel_lcdfb_ops;
  803. memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
  804. info->fix = atmel_lcdfb_fix;
  805. /* Enable LCDC Clocks */
  806. sinfo->bus_clk = clk_get(dev, "hclk");
  807. if (IS_ERR(sinfo->bus_clk)) {
  808. ret = PTR_ERR(sinfo->bus_clk);
  809. goto free_info;
  810. }
  811. sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
  812. if (IS_ERR(sinfo->lcdc_clk)) {
  813. ret = PTR_ERR(sinfo->lcdc_clk);
  814. goto put_bus_clk;
  815. }
  816. atmel_lcdfb_start_clock(sinfo);
  817. ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
  818. info->monspecs.modedb_len, info->monspecs.modedb,
  819. sinfo->default_bpp);
  820. if (!ret) {
  821. dev_err(dev, "no suitable video mode found\n");
  822. goto stop_clk;
  823. }
  824. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  825. if (!regs) {
  826. dev_err(dev, "resources unusable\n");
  827. ret = -ENXIO;
  828. goto stop_clk;
  829. }
  830. sinfo->irq_base = platform_get_irq(pdev, 0);
  831. if (sinfo->irq_base < 0) {
  832. dev_err(dev, "unable to get irq\n");
  833. ret = sinfo->irq_base;
  834. goto stop_clk;
  835. }
  836. /* Initialize video memory */
  837. map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  838. if (map) {
  839. /* use a pre-allocated memory buffer */
  840. info->fix.smem_start = map->start;
  841. info->fix.smem_len = resource_size(map);
  842. if (!request_mem_region(info->fix.smem_start,
  843. info->fix.smem_len, pdev->name)) {
  844. ret = -EBUSY;
  845. goto stop_clk;
  846. }
  847. info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
  848. if (!info->screen_base) {
  849. ret = -ENOMEM;
  850. goto release_intmem;
  851. }
  852. /*
  853. * Don't clear the framebuffer -- someone may have set
  854. * up a splash image.
  855. */
  856. } else {
  857. /* allocate memory buffer */
  858. ret = atmel_lcdfb_alloc_video_memory(sinfo);
  859. if (ret < 0) {
  860. dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
  861. goto stop_clk;
  862. }
  863. }
  864. /* LCDC registers */
  865. info->fix.mmio_start = regs->start;
  866. info->fix.mmio_len = resource_size(regs);
  867. if (!request_mem_region(info->fix.mmio_start,
  868. info->fix.mmio_len, pdev->name)) {
  869. ret = -EBUSY;
  870. goto free_fb;
  871. }
  872. sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
  873. if (!sinfo->mmio) {
  874. dev_err(dev, "cannot map LCDC registers\n");
  875. ret = -ENOMEM;
  876. goto release_mem;
  877. }
  878. /* Initialize PWM for contrast or backlight ("off") */
  879. init_contrast(sinfo);
  880. /* interrupt */
  881. ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
  882. if (ret) {
  883. dev_err(dev, "request_irq failed: %d\n", ret);
  884. goto unmap_mmio;
  885. }
  886. /* Some operations on the LCDC might sleep and
  887. * require a preemptible task context */
  888. INIT_WORK(&sinfo->task, atmel_lcdfb_task);
  889. ret = atmel_lcdfb_init_fbinfo(sinfo);
  890. if (ret < 0) {
  891. dev_err(dev, "init fbinfo failed: %d\n", ret);
  892. goto unregister_irqs;
  893. }
  894. /*
  895. * This makes sure that our colour bitfield
  896. * descriptors are correctly initialised.
  897. */
  898. atmel_lcdfb_check_var(&info->var, info);
  899. ret = fb_set_var(info, &info->var);
  900. if (ret) {
  901. dev_warn(dev, "unable to set display parameters\n");
  902. goto free_cmap;
  903. }
  904. dev_set_drvdata(dev, info);
  905. /*
  906. * Tell the world that we're ready to go
  907. */
  908. ret = register_framebuffer(info);
  909. if (ret < 0) {
  910. dev_err(dev, "failed to register framebuffer device: %d\n", ret);
  911. goto reset_drvdata;
  912. }
  913. /* add selected videomode to modelist */
  914. fb_var_to_videomode(&fbmode, &info->var);
  915. fb_add_videomode(&fbmode, &info->modelist);
  916. /* Power up the LCDC screen */
  917. if (sinfo->atmel_lcdfb_power_control)
  918. sinfo->atmel_lcdfb_power_control(1);
  919. dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n",
  920. info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
  921. return 0;
  922. reset_drvdata:
  923. dev_set_drvdata(dev, NULL);
  924. free_cmap:
  925. fb_dealloc_cmap(&info->cmap);
  926. unregister_irqs:
  927. cancel_work_sync(&sinfo->task);
  928. free_irq(sinfo->irq_base, info);
  929. unmap_mmio:
  930. exit_backlight(sinfo);
  931. iounmap(sinfo->mmio);
  932. release_mem:
  933. release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
  934. free_fb:
  935. if (map)
  936. iounmap(info->screen_base);
  937. else
  938. atmel_lcdfb_free_video_memory(sinfo);
  939. release_intmem:
  940. if (map)
  941. release_mem_region(info->fix.smem_start, info->fix.smem_len);
  942. stop_clk:
  943. atmel_lcdfb_stop_clock(sinfo);
  944. clk_put(sinfo->lcdc_clk);
  945. put_bus_clk:
  946. clk_put(sinfo->bus_clk);
  947. free_info:
  948. framebuffer_release(info);
  949. out:
  950. dev_dbg(dev, "%s FAILED\n", __func__);
  951. return ret;
  952. }
  953. static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
  954. {
  955. struct device *dev = &pdev->dev;
  956. struct fb_info *info = dev_get_drvdata(dev);
  957. struct atmel_lcdfb_info *sinfo;
  958. if (!info || !info->par)
  959. return 0;
  960. sinfo = info->par;
  961. cancel_work_sync(&sinfo->task);
  962. exit_backlight(sinfo);
  963. if (sinfo->atmel_lcdfb_power_control)
  964. sinfo->atmel_lcdfb_power_control(0);
  965. unregister_framebuffer(info);
  966. atmel_lcdfb_stop_clock(sinfo);
  967. clk_put(sinfo->lcdc_clk);
  968. clk_put(sinfo->bus_clk);
  969. fb_dealloc_cmap(&info->cmap);
  970. free_irq(sinfo->irq_base, info);
  971. iounmap(sinfo->mmio);
  972. release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
  973. if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
  974. iounmap(info->screen_base);
  975. release_mem_region(info->fix.smem_start, info->fix.smem_len);
  976. } else {
  977. atmel_lcdfb_free_video_memory(sinfo);
  978. }
  979. dev_set_drvdata(dev, NULL);
  980. framebuffer_release(info);
  981. return 0;
  982. }
  983. #ifdef CONFIG_PM
  984. static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
  985. {
  986. struct fb_info *info = platform_get_drvdata(pdev);
  987. struct atmel_lcdfb_info *sinfo = info->par;
  988. /*
  989. * We don't want to handle interrupts while the clock is
  990. * stopped. It may take forever.
  991. */
  992. lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
  993. sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_CTR);
  994. lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
  995. if (sinfo->atmel_lcdfb_power_control)
  996. sinfo->atmel_lcdfb_power_control(0);
  997. atmel_lcdfb_stop(sinfo);
  998. atmel_lcdfb_stop_clock(sinfo);
  999. return 0;
  1000. }
  1001. static int atmel_lcdfb_resume(struct platform_device *pdev)
  1002. {
  1003. struct fb_info *info = platform_get_drvdata(pdev);
  1004. struct atmel_lcdfb_info *sinfo = info->par;
  1005. atmel_lcdfb_start_clock(sinfo);
  1006. atmel_lcdfb_start(sinfo);
  1007. if (sinfo->atmel_lcdfb_power_control)
  1008. sinfo->atmel_lcdfb_power_control(1);
  1009. lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
  1010. /* Enable FIFO & DMA errors */
  1011. lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI
  1012. | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
  1013. return 0;
  1014. }
  1015. #else
  1016. #define atmel_lcdfb_suspend NULL
  1017. #define atmel_lcdfb_resume NULL
  1018. #endif
  1019. static struct platform_driver atmel_lcdfb_driver = {
  1020. .remove = __exit_p(atmel_lcdfb_remove),
  1021. .suspend = atmel_lcdfb_suspend,
  1022. .resume = atmel_lcdfb_resume,
  1023. .id_table = atmel_lcdfb_devtypes,
  1024. .driver = {
  1025. .name = "atmel_lcdfb",
  1026. .owner = THIS_MODULE,
  1027. },
  1028. };
  1029. module_platform_driver_probe(atmel_lcdfb_driver, atmel_lcdfb_probe);
  1030. MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver");
  1031. MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
  1032. MODULE_LICENSE("GPL");