qeth_core_main.c 157 KB

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  1. /*
  2. * Copyright IBM Corp. 2007, 2009
  3. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  4. * Frank Pavlic <fpavlic@de.ibm.com>,
  5. * Thomas Spatzier <tspat@de.ibm.com>,
  6. * Frank Blaschka <frank.blaschka@de.ibm.com>
  7. */
  8. #define KMSG_COMPONENT "qeth"
  9. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/tcp.h>
  17. #include <linux/mii.h>
  18. #include <linux/kthread.h>
  19. #include <linux/slab.h>
  20. #include <net/iucv/af_iucv.h>
  21. #include <asm/ebcdic.h>
  22. #include <asm/io.h>
  23. #include <asm/sysinfo.h>
  24. #include <asm/compat.h>
  25. #include "qeth_core.h"
  26. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  27. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  28. /* N P A M L V H */
  29. [QETH_DBF_SETUP] = {"qeth_setup",
  30. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_MSG] = {"qeth_msg",
  32. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  33. [QETH_DBF_CTRL] = {"qeth_control",
  34. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  35. };
  36. EXPORT_SYMBOL_GPL(qeth_dbf);
  37. struct qeth_card_list_struct qeth_core_card_list;
  38. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  39. struct kmem_cache *qeth_core_header_cache;
  40. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  41. static struct kmem_cache *qeth_qdio_outbuf_cache;
  42. static struct device *qeth_core_root_dev;
  43. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  44. static struct lock_class_key qdio_out_skb_queue_key;
  45. static struct mutex qeth_mod_mutex;
  46. static void qeth_send_control_data_cb(struct qeth_channel *,
  47. struct qeth_cmd_buffer *);
  48. static int qeth_issue_next_read(struct qeth_card *);
  49. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  50. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  51. static void qeth_free_buffer_pool(struct qeth_card *);
  52. static int qeth_qdio_establish(struct qeth_card *);
  53. static void qeth_free_qdio_buffers(struct qeth_card *);
  54. static void qeth_notify_skbs(struct qeth_qdio_out_q *queue,
  55. struct qeth_qdio_out_buffer *buf,
  56. enum iucv_tx_notify notification);
  57. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf);
  58. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  59. struct qeth_qdio_out_buffer *buf,
  60. enum qeth_qdio_buffer_states newbufstate);
  61. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *, int);
  62. static struct workqueue_struct *qeth_wq;
  63. static void qeth_close_dev_handler(struct work_struct *work)
  64. {
  65. struct qeth_card *card;
  66. card = container_of(work, struct qeth_card, close_dev_work);
  67. QETH_CARD_TEXT(card, 2, "cldevhdl");
  68. rtnl_lock();
  69. dev_close(card->dev);
  70. rtnl_unlock();
  71. ccwgroup_set_offline(card->gdev);
  72. }
  73. void qeth_close_dev(struct qeth_card *card)
  74. {
  75. QETH_CARD_TEXT(card, 2, "cldevsubm");
  76. queue_work(qeth_wq, &card->close_dev_work);
  77. }
  78. EXPORT_SYMBOL_GPL(qeth_close_dev);
  79. static inline const char *qeth_get_cardname(struct qeth_card *card)
  80. {
  81. if (card->info.guestlan) {
  82. switch (card->info.type) {
  83. case QETH_CARD_TYPE_OSD:
  84. return " Virtual NIC QDIO";
  85. case QETH_CARD_TYPE_IQD:
  86. return " Virtual NIC Hiper";
  87. case QETH_CARD_TYPE_OSM:
  88. return " Virtual NIC QDIO - OSM";
  89. case QETH_CARD_TYPE_OSX:
  90. return " Virtual NIC QDIO - OSX";
  91. default:
  92. return " unknown";
  93. }
  94. } else {
  95. switch (card->info.type) {
  96. case QETH_CARD_TYPE_OSD:
  97. return " OSD Express";
  98. case QETH_CARD_TYPE_IQD:
  99. return " HiperSockets";
  100. case QETH_CARD_TYPE_OSN:
  101. return " OSN QDIO";
  102. case QETH_CARD_TYPE_OSM:
  103. return " OSM QDIO";
  104. case QETH_CARD_TYPE_OSX:
  105. return " OSX QDIO";
  106. default:
  107. return " unknown";
  108. }
  109. }
  110. return " n/a";
  111. }
  112. /* max length to be returned: 14 */
  113. const char *qeth_get_cardname_short(struct qeth_card *card)
  114. {
  115. if (card->info.guestlan) {
  116. switch (card->info.type) {
  117. case QETH_CARD_TYPE_OSD:
  118. return "Virt.NIC QDIO";
  119. case QETH_CARD_TYPE_IQD:
  120. return "Virt.NIC Hiper";
  121. case QETH_CARD_TYPE_OSM:
  122. return "Virt.NIC OSM";
  123. case QETH_CARD_TYPE_OSX:
  124. return "Virt.NIC OSX";
  125. default:
  126. return "unknown";
  127. }
  128. } else {
  129. switch (card->info.type) {
  130. case QETH_CARD_TYPE_OSD:
  131. switch (card->info.link_type) {
  132. case QETH_LINK_TYPE_FAST_ETH:
  133. return "OSD_100";
  134. case QETH_LINK_TYPE_HSTR:
  135. return "HSTR";
  136. case QETH_LINK_TYPE_GBIT_ETH:
  137. return "OSD_1000";
  138. case QETH_LINK_TYPE_10GBIT_ETH:
  139. return "OSD_10GIG";
  140. case QETH_LINK_TYPE_LANE_ETH100:
  141. return "OSD_FE_LANE";
  142. case QETH_LINK_TYPE_LANE_TR:
  143. return "OSD_TR_LANE";
  144. case QETH_LINK_TYPE_LANE_ETH1000:
  145. return "OSD_GbE_LANE";
  146. case QETH_LINK_TYPE_LANE:
  147. return "OSD_ATM_LANE";
  148. default:
  149. return "OSD_Express";
  150. }
  151. case QETH_CARD_TYPE_IQD:
  152. return "HiperSockets";
  153. case QETH_CARD_TYPE_OSN:
  154. return "OSN";
  155. case QETH_CARD_TYPE_OSM:
  156. return "OSM_1000";
  157. case QETH_CARD_TYPE_OSX:
  158. return "OSX_10GIG";
  159. default:
  160. return "unknown";
  161. }
  162. }
  163. return "n/a";
  164. }
  165. void qeth_set_recovery_task(struct qeth_card *card)
  166. {
  167. card->recovery_task = current;
  168. }
  169. EXPORT_SYMBOL_GPL(qeth_set_recovery_task);
  170. void qeth_clear_recovery_task(struct qeth_card *card)
  171. {
  172. card->recovery_task = NULL;
  173. }
  174. EXPORT_SYMBOL_GPL(qeth_clear_recovery_task);
  175. static bool qeth_is_recovery_task(const struct qeth_card *card)
  176. {
  177. return card->recovery_task == current;
  178. }
  179. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  180. int clear_start_mask)
  181. {
  182. unsigned long flags;
  183. spin_lock_irqsave(&card->thread_mask_lock, flags);
  184. card->thread_allowed_mask = threads;
  185. if (clear_start_mask)
  186. card->thread_start_mask &= threads;
  187. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  188. wake_up(&card->wait_q);
  189. }
  190. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  191. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  192. {
  193. unsigned long flags;
  194. int rc = 0;
  195. spin_lock_irqsave(&card->thread_mask_lock, flags);
  196. rc = (card->thread_running_mask & threads);
  197. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  198. return rc;
  199. }
  200. EXPORT_SYMBOL_GPL(qeth_threads_running);
  201. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  202. {
  203. if (qeth_is_recovery_task(card))
  204. return 0;
  205. return wait_event_interruptible(card->wait_q,
  206. qeth_threads_running(card, threads) == 0);
  207. }
  208. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  209. void qeth_clear_working_pool_list(struct qeth_card *card)
  210. {
  211. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  212. QETH_CARD_TEXT(card, 5, "clwrklst");
  213. list_for_each_entry_safe(pool_entry, tmp,
  214. &card->qdio.in_buf_pool.entry_list, list){
  215. list_del(&pool_entry->list);
  216. }
  217. }
  218. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  219. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  220. {
  221. struct qeth_buffer_pool_entry *pool_entry;
  222. void *ptr;
  223. int i, j;
  224. QETH_CARD_TEXT(card, 5, "alocpool");
  225. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  226. pool_entry = kzalloc(sizeof(*pool_entry), GFP_KERNEL);
  227. if (!pool_entry) {
  228. qeth_free_buffer_pool(card);
  229. return -ENOMEM;
  230. }
  231. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  232. ptr = (void *) __get_free_page(GFP_KERNEL);
  233. if (!ptr) {
  234. while (j > 0)
  235. free_page((unsigned long)
  236. pool_entry->elements[--j]);
  237. kfree(pool_entry);
  238. qeth_free_buffer_pool(card);
  239. return -ENOMEM;
  240. }
  241. pool_entry->elements[j] = ptr;
  242. }
  243. list_add(&pool_entry->init_list,
  244. &card->qdio.init_pool.entry_list);
  245. }
  246. return 0;
  247. }
  248. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  249. {
  250. QETH_CARD_TEXT(card, 2, "realcbp");
  251. if ((card->state != CARD_STATE_DOWN) &&
  252. (card->state != CARD_STATE_RECOVER))
  253. return -EPERM;
  254. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  255. qeth_clear_working_pool_list(card);
  256. qeth_free_buffer_pool(card);
  257. card->qdio.in_buf_pool.buf_count = bufcnt;
  258. card->qdio.init_pool.buf_count = bufcnt;
  259. return qeth_alloc_buffer_pool(card);
  260. }
  261. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  262. static inline int qeth_cq_init(struct qeth_card *card)
  263. {
  264. int rc;
  265. if (card->options.cq == QETH_CQ_ENABLED) {
  266. QETH_DBF_TEXT(SETUP, 2, "cqinit");
  267. memset(card->qdio.c_q->qdio_bufs, 0,
  268. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  269. card->qdio.c_q->next_buf_to_init = 127;
  270. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT,
  271. card->qdio.no_in_queues - 1, 0,
  272. 127);
  273. if (rc) {
  274. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  275. goto out;
  276. }
  277. }
  278. rc = 0;
  279. out:
  280. return rc;
  281. }
  282. static inline int qeth_alloc_cq(struct qeth_card *card)
  283. {
  284. int rc;
  285. if (card->options.cq == QETH_CQ_ENABLED) {
  286. int i;
  287. struct qdio_outbuf_state *outbuf_states;
  288. QETH_DBF_TEXT(SETUP, 2, "cqon");
  289. card->qdio.c_q = kzalloc(sizeof(struct qeth_qdio_q),
  290. GFP_KERNEL);
  291. if (!card->qdio.c_q) {
  292. rc = -1;
  293. goto kmsg_out;
  294. }
  295. QETH_DBF_HEX(SETUP, 2, &card->qdio.c_q, sizeof(void *));
  296. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  297. card->qdio.c_q->bufs[i].buffer =
  298. &card->qdio.c_q->qdio_bufs[i];
  299. }
  300. card->qdio.no_in_queues = 2;
  301. card->qdio.out_bufstates =
  302. kzalloc(card->qdio.no_out_queues *
  303. QDIO_MAX_BUFFERS_PER_Q *
  304. sizeof(struct qdio_outbuf_state), GFP_KERNEL);
  305. outbuf_states = card->qdio.out_bufstates;
  306. if (outbuf_states == NULL) {
  307. rc = -1;
  308. goto free_cq_out;
  309. }
  310. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  311. card->qdio.out_qs[i]->bufstates = outbuf_states;
  312. outbuf_states += QDIO_MAX_BUFFERS_PER_Q;
  313. }
  314. } else {
  315. QETH_DBF_TEXT(SETUP, 2, "nocq");
  316. card->qdio.c_q = NULL;
  317. card->qdio.no_in_queues = 1;
  318. }
  319. QETH_DBF_TEXT_(SETUP, 2, "iqc%d", card->qdio.no_in_queues);
  320. rc = 0;
  321. out:
  322. return rc;
  323. free_cq_out:
  324. kfree(card->qdio.c_q);
  325. card->qdio.c_q = NULL;
  326. kmsg_out:
  327. dev_err(&card->gdev->dev, "Failed to create completion queue\n");
  328. goto out;
  329. }
  330. static inline void qeth_free_cq(struct qeth_card *card)
  331. {
  332. if (card->qdio.c_q) {
  333. --card->qdio.no_in_queues;
  334. kfree(card->qdio.c_q);
  335. card->qdio.c_q = NULL;
  336. }
  337. kfree(card->qdio.out_bufstates);
  338. card->qdio.out_bufstates = NULL;
  339. }
  340. static inline enum iucv_tx_notify qeth_compute_cq_notification(int sbalf15,
  341. int delayed) {
  342. enum iucv_tx_notify n;
  343. switch (sbalf15) {
  344. case 0:
  345. n = delayed ? TX_NOTIFY_DELAYED_OK : TX_NOTIFY_OK;
  346. break;
  347. case 4:
  348. case 16:
  349. case 17:
  350. case 18:
  351. n = delayed ? TX_NOTIFY_DELAYED_UNREACHABLE :
  352. TX_NOTIFY_UNREACHABLE;
  353. break;
  354. default:
  355. n = delayed ? TX_NOTIFY_DELAYED_GENERALERROR :
  356. TX_NOTIFY_GENERALERROR;
  357. break;
  358. }
  359. return n;
  360. }
  361. static inline void qeth_cleanup_handled_pending(struct qeth_qdio_out_q *q,
  362. int bidx, int forced_cleanup)
  363. {
  364. if (q->card->options.cq != QETH_CQ_ENABLED)
  365. return;
  366. if (q->bufs[bidx]->next_pending != NULL) {
  367. struct qeth_qdio_out_buffer *head = q->bufs[bidx];
  368. struct qeth_qdio_out_buffer *c = q->bufs[bidx]->next_pending;
  369. while (c) {
  370. if (forced_cleanup ||
  371. atomic_read(&c->state) ==
  372. QETH_QDIO_BUF_HANDLED_DELAYED) {
  373. struct qeth_qdio_out_buffer *f = c;
  374. QETH_CARD_TEXT(f->q->card, 5, "fp");
  375. QETH_CARD_TEXT_(f->q->card, 5, "%lx", (long) f);
  376. /* release here to avoid interleaving between
  377. outbound tasklet and inbound tasklet
  378. regarding notifications and lifecycle */
  379. qeth_release_skbs(c);
  380. c = f->next_pending;
  381. WARN_ON_ONCE(head->next_pending != f);
  382. head->next_pending = c;
  383. kmem_cache_free(qeth_qdio_outbuf_cache, f);
  384. } else {
  385. head = c;
  386. c = c->next_pending;
  387. }
  388. }
  389. }
  390. if (forced_cleanup && (atomic_read(&(q->bufs[bidx]->state)) ==
  391. QETH_QDIO_BUF_HANDLED_DELAYED)) {
  392. /* for recovery situations */
  393. q->bufs[bidx]->aob = q->bufstates[bidx].aob;
  394. qeth_init_qdio_out_buf(q, bidx);
  395. QETH_CARD_TEXT(q->card, 2, "clprecov");
  396. }
  397. }
  398. static inline void qeth_qdio_handle_aob(struct qeth_card *card,
  399. unsigned long phys_aob_addr) {
  400. struct qaob *aob;
  401. struct qeth_qdio_out_buffer *buffer;
  402. enum iucv_tx_notify notification;
  403. aob = (struct qaob *) phys_to_virt(phys_aob_addr);
  404. QETH_CARD_TEXT(card, 5, "haob");
  405. QETH_CARD_TEXT_(card, 5, "%lx", phys_aob_addr);
  406. buffer = (struct qeth_qdio_out_buffer *) aob->user1;
  407. QETH_CARD_TEXT_(card, 5, "%lx", aob->user1);
  408. if (atomic_cmpxchg(&buffer->state, QETH_QDIO_BUF_PRIMED,
  409. QETH_QDIO_BUF_IN_CQ) == QETH_QDIO_BUF_PRIMED) {
  410. notification = TX_NOTIFY_OK;
  411. } else {
  412. WARN_ON_ONCE(atomic_read(&buffer->state) !=
  413. QETH_QDIO_BUF_PENDING);
  414. atomic_set(&buffer->state, QETH_QDIO_BUF_IN_CQ);
  415. notification = TX_NOTIFY_DELAYED_OK;
  416. }
  417. if (aob->aorc != 0) {
  418. QETH_CARD_TEXT_(card, 2, "aorc%02X", aob->aorc);
  419. notification = qeth_compute_cq_notification(aob->aorc, 1);
  420. }
  421. qeth_notify_skbs(buffer->q, buffer, notification);
  422. buffer->aob = NULL;
  423. qeth_clear_output_buffer(buffer->q, buffer,
  424. QETH_QDIO_BUF_HANDLED_DELAYED);
  425. /* from here on: do not touch buffer anymore */
  426. qdio_release_aob(aob);
  427. }
  428. static inline int qeth_is_cq(struct qeth_card *card, unsigned int queue)
  429. {
  430. return card->options.cq == QETH_CQ_ENABLED &&
  431. card->qdio.c_q != NULL &&
  432. queue != 0 &&
  433. queue == card->qdio.no_in_queues - 1;
  434. }
  435. static int qeth_issue_next_read(struct qeth_card *card)
  436. {
  437. int rc;
  438. struct qeth_cmd_buffer *iob;
  439. QETH_CARD_TEXT(card, 5, "issnxrd");
  440. if (card->read.state != CH_STATE_UP)
  441. return -EIO;
  442. iob = qeth_get_buffer(&card->read);
  443. if (!iob) {
  444. dev_warn(&card->gdev->dev, "The qeth device driver "
  445. "failed to recover an error on the device\n");
  446. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  447. "available\n", dev_name(&card->gdev->dev));
  448. return -ENOMEM;
  449. }
  450. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  451. QETH_CARD_TEXT(card, 6, "noirqpnd");
  452. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  453. (addr_t) iob, 0, 0);
  454. if (rc) {
  455. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  456. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  457. atomic_set(&card->read.irq_pending, 0);
  458. card->read_or_write_problem = 1;
  459. qeth_schedule_recovery(card);
  460. wake_up(&card->wait_q);
  461. }
  462. return rc;
  463. }
  464. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  465. {
  466. struct qeth_reply *reply;
  467. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  468. if (reply) {
  469. atomic_set(&reply->refcnt, 1);
  470. atomic_set(&reply->received, 0);
  471. reply->card = card;
  472. }
  473. return reply;
  474. }
  475. static void qeth_get_reply(struct qeth_reply *reply)
  476. {
  477. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  478. atomic_inc(&reply->refcnt);
  479. }
  480. static void qeth_put_reply(struct qeth_reply *reply)
  481. {
  482. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  483. if (atomic_dec_and_test(&reply->refcnt))
  484. kfree(reply);
  485. }
  486. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  487. struct qeth_card *card)
  488. {
  489. char *ipa_name;
  490. int com = cmd->hdr.command;
  491. ipa_name = qeth_get_ipa_cmd_name(com);
  492. if (rc)
  493. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  494. "x%X \"%s\"\n",
  495. ipa_name, com, dev_name(&card->gdev->dev),
  496. QETH_CARD_IFNAME(card), rc,
  497. qeth_get_ipa_msg(rc));
  498. else
  499. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  500. ipa_name, com, dev_name(&card->gdev->dev),
  501. QETH_CARD_IFNAME(card));
  502. }
  503. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  504. struct qeth_cmd_buffer *iob)
  505. {
  506. struct qeth_ipa_cmd *cmd = NULL;
  507. QETH_CARD_TEXT(card, 5, "chkipad");
  508. if (IS_IPA(iob->data)) {
  509. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  510. if (IS_IPA_REPLY(cmd)) {
  511. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  512. cmd->hdr.command != IPA_CMD_DELCCID &&
  513. cmd->hdr.command != IPA_CMD_MODCCID &&
  514. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  515. qeth_issue_ipa_msg(cmd,
  516. cmd->hdr.return_code, card);
  517. return cmd;
  518. } else {
  519. switch (cmd->hdr.command) {
  520. case IPA_CMD_STOPLAN:
  521. if (cmd->hdr.return_code ==
  522. IPA_RC_VEPA_TO_VEB_TRANSITION) {
  523. dev_err(&card->gdev->dev,
  524. "Interface %s is down because the "
  525. "adjacent port is no longer in "
  526. "reflective relay mode\n",
  527. QETH_CARD_IFNAME(card));
  528. qeth_close_dev(card);
  529. } else {
  530. dev_warn(&card->gdev->dev,
  531. "The link for interface %s on CHPID"
  532. " 0x%X failed\n",
  533. QETH_CARD_IFNAME(card),
  534. card->info.chpid);
  535. qeth_issue_ipa_msg(cmd,
  536. cmd->hdr.return_code, card);
  537. }
  538. card->lan_online = 0;
  539. if (card->dev && netif_carrier_ok(card->dev))
  540. netif_carrier_off(card->dev);
  541. return NULL;
  542. case IPA_CMD_STARTLAN:
  543. dev_info(&card->gdev->dev,
  544. "The link for %s on CHPID 0x%X has"
  545. " been restored\n",
  546. QETH_CARD_IFNAME(card),
  547. card->info.chpid);
  548. netif_carrier_on(card->dev);
  549. card->lan_online = 1;
  550. if (card->info.hwtrap)
  551. card->info.hwtrap = 2;
  552. qeth_schedule_recovery(card);
  553. return NULL;
  554. case IPA_CMD_MODCCID:
  555. return cmd;
  556. case IPA_CMD_REGISTER_LOCAL_ADDR:
  557. QETH_CARD_TEXT(card, 3, "irla");
  558. break;
  559. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  560. QETH_CARD_TEXT(card, 3, "urla");
  561. break;
  562. default:
  563. QETH_DBF_MESSAGE(2, "Received data is IPA "
  564. "but not a reply!\n");
  565. break;
  566. }
  567. }
  568. }
  569. return cmd;
  570. }
  571. void qeth_clear_ipacmd_list(struct qeth_card *card)
  572. {
  573. struct qeth_reply *reply, *r;
  574. unsigned long flags;
  575. QETH_CARD_TEXT(card, 4, "clipalst");
  576. spin_lock_irqsave(&card->lock, flags);
  577. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  578. qeth_get_reply(reply);
  579. reply->rc = -EIO;
  580. atomic_inc(&reply->received);
  581. list_del_init(&reply->list);
  582. wake_up(&reply->wait_q);
  583. qeth_put_reply(reply);
  584. }
  585. spin_unlock_irqrestore(&card->lock, flags);
  586. atomic_set(&card->write.irq_pending, 0);
  587. }
  588. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  589. static int qeth_check_idx_response(struct qeth_card *card,
  590. unsigned char *buffer)
  591. {
  592. if (!buffer)
  593. return 0;
  594. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  595. if ((buffer[2] & 0xc0) == 0xc0) {
  596. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  597. "with cause code 0x%02x%s\n",
  598. buffer[4],
  599. ((buffer[4] == 0x22) ?
  600. " -- try another portname" : ""));
  601. QETH_CARD_TEXT(card, 2, "ckidxres");
  602. QETH_CARD_TEXT(card, 2, " idxterm");
  603. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  604. if (buffer[4] == 0xf6) {
  605. dev_err(&card->gdev->dev,
  606. "The qeth device is not configured "
  607. "for the OSI layer required by z/VM\n");
  608. return -EPERM;
  609. }
  610. return -EIO;
  611. }
  612. return 0;
  613. }
  614. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  615. __u32 len)
  616. {
  617. struct qeth_card *card;
  618. card = CARD_FROM_CDEV(channel->ccwdev);
  619. QETH_CARD_TEXT(card, 4, "setupccw");
  620. if (channel == &card->read)
  621. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  622. else
  623. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  624. channel->ccw.count = len;
  625. channel->ccw.cda = (__u32) __pa(iob);
  626. }
  627. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  628. {
  629. __u8 index;
  630. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  631. index = channel->io_buf_no;
  632. do {
  633. if (channel->iob[index].state == BUF_STATE_FREE) {
  634. channel->iob[index].state = BUF_STATE_LOCKED;
  635. channel->io_buf_no = (channel->io_buf_no + 1) %
  636. QETH_CMD_BUFFER_NO;
  637. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  638. return channel->iob + index;
  639. }
  640. index = (index + 1) % QETH_CMD_BUFFER_NO;
  641. } while (index != channel->io_buf_no);
  642. return NULL;
  643. }
  644. void qeth_release_buffer(struct qeth_channel *channel,
  645. struct qeth_cmd_buffer *iob)
  646. {
  647. unsigned long flags;
  648. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  649. spin_lock_irqsave(&channel->iob_lock, flags);
  650. memset(iob->data, 0, QETH_BUFSIZE);
  651. iob->state = BUF_STATE_FREE;
  652. iob->callback = qeth_send_control_data_cb;
  653. iob->rc = 0;
  654. spin_unlock_irqrestore(&channel->iob_lock, flags);
  655. wake_up(&channel->wait_q);
  656. }
  657. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  658. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  659. {
  660. struct qeth_cmd_buffer *buffer = NULL;
  661. unsigned long flags;
  662. spin_lock_irqsave(&channel->iob_lock, flags);
  663. buffer = __qeth_get_buffer(channel);
  664. spin_unlock_irqrestore(&channel->iob_lock, flags);
  665. return buffer;
  666. }
  667. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  668. {
  669. struct qeth_cmd_buffer *buffer;
  670. wait_event(channel->wait_q,
  671. ((buffer = qeth_get_buffer(channel)) != NULL));
  672. return buffer;
  673. }
  674. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  675. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  676. {
  677. int cnt;
  678. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  679. qeth_release_buffer(channel, &channel->iob[cnt]);
  680. channel->buf_no = 0;
  681. channel->io_buf_no = 0;
  682. }
  683. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  684. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  685. struct qeth_cmd_buffer *iob)
  686. {
  687. struct qeth_card *card;
  688. struct qeth_reply *reply, *r;
  689. struct qeth_ipa_cmd *cmd;
  690. unsigned long flags;
  691. int keep_reply;
  692. int rc = 0;
  693. card = CARD_FROM_CDEV(channel->ccwdev);
  694. QETH_CARD_TEXT(card, 4, "sndctlcb");
  695. rc = qeth_check_idx_response(card, iob->data);
  696. switch (rc) {
  697. case 0:
  698. break;
  699. case -EIO:
  700. qeth_clear_ipacmd_list(card);
  701. qeth_schedule_recovery(card);
  702. /* fall through */
  703. default:
  704. goto out;
  705. }
  706. cmd = qeth_check_ipa_data(card, iob);
  707. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  708. goto out;
  709. /*in case of OSN : check if cmd is set */
  710. if (card->info.type == QETH_CARD_TYPE_OSN &&
  711. cmd &&
  712. cmd->hdr.command != IPA_CMD_STARTLAN &&
  713. card->osn_info.assist_cb != NULL) {
  714. card->osn_info.assist_cb(card->dev, cmd);
  715. goto out;
  716. }
  717. spin_lock_irqsave(&card->lock, flags);
  718. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  719. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  720. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  721. qeth_get_reply(reply);
  722. list_del_init(&reply->list);
  723. spin_unlock_irqrestore(&card->lock, flags);
  724. keep_reply = 0;
  725. if (reply->callback != NULL) {
  726. if (cmd) {
  727. reply->offset = (__u16)((char *)cmd -
  728. (char *)iob->data);
  729. keep_reply = reply->callback(card,
  730. reply,
  731. (unsigned long)cmd);
  732. } else
  733. keep_reply = reply->callback(card,
  734. reply,
  735. (unsigned long)iob);
  736. }
  737. if (cmd)
  738. reply->rc = (u16) cmd->hdr.return_code;
  739. else if (iob->rc)
  740. reply->rc = iob->rc;
  741. if (keep_reply) {
  742. spin_lock_irqsave(&card->lock, flags);
  743. list_add_tail(&reply->list,
  744. &card->cmd_waiter_list);
  745. spin_unlock_irqrestore(&card->lock, flags);
  746. } else {
  747. atomic_inc(&reply->received);
  748. wake_up(&reply->wait_q);
  749. }
  750. qeth_put_reply(reply);
  751. goto out;
  752. }
  753. }
  754. spin_unlock_irqrestore(&card->lock, flags);
  755. out:
  756. memcpy(&card->seqno.pdu_hdr_ack,
  757. QETH_PDU_HEADER_SEQ_NO(iob->data),
  758. QETH_SEQ_NO_LENGTH);
  759. qeth_release_buffer(channel, iob);
  760. }
  761. static int qeth_setup_channel(struct qeth_channel *channel)
  762. {
  763. int cnt;
  764. QETH_DBF_TEXT(SETUP, 2, "setupch");
  765. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  766. channel->iob[cnt].data =
  767. kzalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  768. if (channel->iob[cnt].data == NULL)
  769. break;
  770. channel->iob[cnt].state = BUF_STATE_FREE;
  771. channel->iob[cnt].channel = channel;
  772. channel->iob[cnt].callback = qeth_send_control_data_cb;
  773. channel->iob[cnt].rc = 0;
  774. }
  775. if (cnt < QETH_CMD_BUFFER_NO) {
  776. while (cnt-- > 0)
  777. kfree(channel->iob[cnt].data);
  778. return -ENOMEM;
  779. }
  780. channel->buf_no = 0;
  781. channel->io_buf_no = 0;
  782. atomic_set(&channel->irq_pending, 0);
  783. spin_lock_init(&channel->iob_lock);
  784. init_waitqueue_head(&channel->wait_q);
  785. return 0;
  786. }
  787. static int qeth_set_thread_start_bit(struct qeth_card *card,
  788. unsigned long thread)
  789. {
  790. unsigned long flags;
  791. spin_lock_irqsave(&card->thread_mask_lock, flags);
  792. if (!(card->thread_allowed_mask & thread) ||
  793. (card->thread_start_mask & thread)) {
  794. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  795. return -EPERM;
  796. }
  797. card->thread_start_mask |= thread;
  798. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  799. return 0;
  800. }
  801. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  802. {
  803. unsigned long flags;
  804. spin_lock_irqsave(&card->thread_mask_lock, flags);
  805. card->thread_start_mask &= ~thread;
  806. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  807. wake_up(&card->wait_q);
  808. }
  809. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  810. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  811. {
  812. unsigned long flags;
  813. spin_lock_irqsave(&card->thread_mask_lock, flags);
  814. card->thread_running_mask &= ~thread;
  815. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  816. wake_up(&card->wait_q);
  817. }
  818. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  819. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  820. {
  821. unsigned long flags;
  822. int rc = 0;
  823. spin_lock_irqsave(&card->thread_mask_lock, flags);
  824. if (card->thread_start_mask & thread) {
  825. if ((card->thread_allowed_mask & thread) &&
  826. !(card->thread_running_mask & thread)) {
  827. rc = 1;
  828. card->thread_start_mask &= ~thread;
  829. card->thread_running_mask |= thread;
  830. } else
  831. rc = -EPERM;
  832. }
  833. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  834. return rc;
  835. }
  836. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  837. {
  838. int rc = 0;
  839. wait_event(card->wait_q,
  840. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  841. return rc;
  842. }
  843. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  844. void qeth_schedule_recovery(struct qeth_card *card)
  845. {
  846. QETH_CARD_TEXT(card, 2, "startrec");
  847. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  848. schedule_work(&card->kernel_thread_starter);
  849. }
  850. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  851. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  852. {
  853. int dstat, cstat;
  854. char *sense;
  855. struct qeth_card *card;
  856. sense = (char *) irb->ecw;
  857. cstat = irb->scsw.cmd.cstat;
  858. dstat = irb->scsw.cmd.dstat;
  859. card = CARD_FROM_CDEV(cdev);
  860. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  861. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  862. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  863. QETH_CARD_TEXT(card, 2, "CGENCHK");
  864. dev_warn(&cdev->dev, "The qeth device driver "
  865. "failed to recover an error on the device\n");
  866. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  867. dev_name(&cdev->dev), dstat, cstat);
  868. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  869. 16, 1, irb, 64, 1);
  870. return 1;
  871. }
  872. if (dstat & DEV_STAT_UNIT_CHECK) {
  873. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  874. SENSE_RESETTING_EVENT_FLAG) {
  875. QETH_CARD_TEXT(card, 2, "REVIND");
  876. return 1;
  877. }
  878. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  879. SENSE_COMMAND_REJECT_FLAG) {
  880. QETH_CARD_TEXT(card, 2, "CMDREJi");
  881. return 1;
  882. }
  883. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  884. QETH_CARD_TEXT(card, 2, "AFFE");
  885. return 1;
  886. }
  887. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  888. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  889. return 0;
  890. }
  891. QETH_CARD_TEXT(card, 2, "DGENCHK");
  892. return 1;
  893. }
  894. return 0;
  895. }
  896. static long __qeth_check_irb_error(struct ccw_device *cdev,
  897. unsigned long intparm, struct irb *irb)
  898. {
  899. struct qeth_card *card;
  900. card = CARD_FROM_CDEV(cdev);
  901. if (!IS_ERR(irb))
  902. return 0;
  903. switch (PTR_ERR(irb)) {
  904. case -EIO:
  905. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  906. dev_name(&cdev->dev));
  907. QETH_CARD_TEXT(card, 2, "ckirberr");
  908. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  909. break;
  910. case -ETIMEDOUT:
  911. dev_warn(&cdev->dev, "A hardware operation timed out"
  912. " on the device\n");
  913. QETH_CARD_TEXT(card, 2, "ckirberr");
  914. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  915. if (intparm == QETH_RCD_PARM) {
  916. if (card && (card->data.ccwdev == cdev)) {
  917. card->data.state = CH_STATE_DOWN;
  918. wake_up(&card->wait_q);
  919. }
  920. }
  921. break;
  922. default:
  923. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  924. dev_name(&cdev->dev), PTR_ERR(irb));
  925. QETH_CARD_TEXT(card, 2, "ckirberr");
  926. QETH_CARD_TEXT(card, 2, " rc???");
  927. }
  928. return PTR_ERR(irb);
  929. }
  930. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  931. struct irb *irb)
  932. {
  933. int rc;
  934. int cstat, dstat;
  935. struct qeth_cmd_buffer *buffer;
  936. struct qeth_channel *channel;
  937. struct qeth_card *card;
  938. struct qeth_cmd_buffer *iob;
  939. __u8 index;
  940. if (__qeth_check_irb_error(cdev, intparm, irb))
  941. return;
  942. cstat = irb->scsw.cmd.cstat;
  943. dstat = irb->scsw.cmd.dstat;
  944. card = CARD_FROM_CDEV(cdev);
  945. if (!card)
  946. return;
  947. QETH_CARD_TEXT(card, 5, "irq");
  948. if (card->read.ccwdev == cdev) {
  949. channel = &card->read;
  950. QETH_CARD_TEXT(card, 5, "read");
  951. } else if (card->write.ccwdev == cdev) {
  952. channel = &card->write;
  953. QETH_CARD_TEXT(card, 5, "write");
  954. } else {
  955. channel = &card->data;
  956. QETH_CARD_TEXT(card, 5, "data");
  957. }
  958. atomic_set(&channel->irq_pending, 0);
  959. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  960. channel->state = CH_STATE_STOPPED;
  961. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  962. channel->state = CH_STATE_HALTED;
  963. /*let's wake up immediately on data channel*/
  964. if ((channel == &card->data) && (intparm != 0) &&
  965. (intparm != QETH_RCD_PARM))
  966. goto out;
  967. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  968. QETH_CARD_TEXT(card, 6, "clrchpar");
  969. /* we don't have to handle this further */
  970. intparm = 0;
  971. }
  972. if (intparm == QETH_HALT_CHANNEL_PARM) {
  973. QETH_CARD_TEXT(card, 6, "hltchpar");
  974. /* we don't have to handle this further */
  975. intparm = 0;
  976. }
  977. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  978. (dstat & DEV_STAT_UNIT_CHECK) ||
  979. (cstat)) {
  980. if (irb->esw.esw0.erw.cons) {
  981. dev_warn(&channel->ccwdev->dev,
  982. "The qeth device driver failed to recover "
  983. "an error on the device\n");
  984. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  985. "0x%X dstat 0x%X\n",
  986. dev_name(&channel->ccwdev->dev), cstat, dstat);
  987. print_hex_dump(KERN_WARNING, "qeth: irb ",
  988. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  989. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  990. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  991. }
  992. if (intparm == QETH_RCD_PARM) {
  993. channel->state = CH_STATE_DOWN;
  994. goto out;
  995. }
  996. rc = qeth_get_problem(cdev, irb);
  997. if (rc) {
  998. qeth_clear_ipacmd_list(card);
  999. qeth_schedule_recovery(card);
  1000. goto out;
  1001. }
  1002. }
  1003. if (intparm == QETH_RCD_PARM) {
  1004. channel->state = CH_STATE_RCD_DONE;
  1005. goto out;
  1006. }
  1007. if (intparm) {
  1008. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  1009. buffer->state = BUF_STATE_PROCESSED;
  1010. }
  1011. if (channel == &card->data)
  1012. return;
  1013. if (channel == &card->read &&
  1014. channel->state == CH_STATE_UP)
  1015. qeth_issue_next_read(card);
  1016. iob = channel->iob;
  1017. index = channel->buf_no;
  1018. while (iob[index].state == BUF_STATE_PROCESSED) {
  1019. if (iob[index].callback != NULL)
  1020. iob[index].callback(channel, iob + index);
  1021. index = (index + 1) % QETH_CMD_BUFFER_NO;
  1022. }
  1023. channel->buf_no = index;
  1024. out:
  1025. wake_up(&card->wait_q);
  1026. return;
  1027. }
  1028. static void qeth_notify_skbs(struct qeth_qdio_out_q *q,
  1029. struct qeth_qdio_out_buffer *buf,
  1030. enum iucv_tx_notify notification)
  1031. {
  1032. struct sk_buff *skb;
  1033. if (skb_queue_empty(&buf->skb_list))
  1034. goto out;
  1035. skb = skb_peek(&buf->skb_list);
  1036. while (skb) {
  1037. QETH_CARD_TEXT_(q->card, 5, "skbn%d", notification);
  1038. QETH_CARD_TEXT_(q->card, 5, "%lx", (long) skb);
  1039. if (skb->protocol == ETH_P_AF_IUCV) {
  1040. if (skb->sk) {
  1041. struct iucv_sock *iucv = iucv_sk(skb->sk);
  1042. iucv->sk_txnotify(skb, notification);
  1043. }
  1044. }
  1045. if (skb_queue_is_last(&buf->skb_list, skb))
  1046. skb = NULL;
  1047. else
  1048. skb = skb_queue_next(&buf->skb_list, skb);
  1049. }
  1050. out:
  1051. return;
  1052. }
  1053. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf)
  1054. {
  1055. struct sk_buff *skb;
  1056. struct iucv_sock *iucv;
  1057. int notify_general_error = 0;
  1058. if (atomic_read(&buf->state) == QETH_QDIO_BUF_PENDING)
  1059. notify_general_error = 1;
  1060. /* release may never happen from within CQ tasklet scope */
  1061. WARN_ON_ONCE(atomic_read(&buf->state) == QETH_QDIO_BUF_IN_CQ);
  1062. skb = skb_dequeue(&buf->skb_list);
  1063. while (skb) {
  1064. QETH_CARD_TEXT(buf->q->card, 5, "skbr");
  1065. QETH_CARD_TEXT_(buf->q->card, 5, "%lx", (long) skb);
  1066. if (notify_general_error && skb->protocol == ETH_P_AF_IUCV) {
  1067. if (skb->sk) {
  1068. iucv = iucv_sk(skb->sk);
  1069. iucv->sk_txnotify(skb, TX_NOTIFY_GENERALERROR);
  1070. }
  1071. }
  1072. atomic_dec(&skb->users);
  1073. dev_kfree_skb_any(skb);
  1074. skb = skb_dequeue(&buf->skb_list);
  1075. }
  1076. }
  1077. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  1078. struct qeth_qdio_out_buffer *buf,
  1079. enum qeth_qdio_buffer_states newbufstate)
  1080. {
  1081. int i;
  1082. /* is PCI flag set on buffer? */
  1083. if (buf->buffer->element[0].sflags & SBAL_SFLAGS0_PCI_REQ)
  1084. atomic_dec(&queue->set_pci_flags_count);
  1085. if (newbufstate == QETH_QDIO_BUF_EMPTY) {
  1086. qeth_release_skbs(buf);
  1087. }
  1088. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  1089. if (buf->buffer->element[i].addr && buf->is_header[i])
  1090. kmem_cache_free(qeth_core_header_cache,
  1091. buf->buffer->element[i].addr);
  1092. buf->is_header[i] = 0;
  1093. buf->buffer->element[i].length = 0;
  1094. buf->buffer->element[i].addr = NULL;
  1095. buf->buffer->element[i].eflags = 0;
  1096. buf->buffer->element[i].sflags = 0;
  1097. }
  1098. buf->buffer->element[15].eflags = 0;
  1099. buf->buffer->element[15].sflags = 0;
  1100. buf->next_element_to_fill = 0;
  1101. atomic_set(&buf->state, newbufstate);
  1102. }
  1103. static void qeth_clear_outq_buffers(struct qeth_qdio_out_q *q, int free)
  1104. {
  1105. int j;
  1106. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1107. if (!q->bufs[j])
  1108. continue;
  1109. qeth_cleanup_handled_pending(q, j, 1);
  1110. qeth_clear_output_buffer(q, q->bufs[j], QETH_QDIO_BUF_EMPTY);
  1111. if (free) {
  1112. kmem_cache_free(qeth_qdio_outbuf_cache, q->bufs[j]);
  1113. q->bufs[j] = NULL;
  1114. }
  1115. }
  1116. }
  1117. void qeth_clear_qdio_buffers(struct qeth_card *card)
  1118. {
  1119. int i;
  1120. QETH_CARD_TEXT(card, 2, "clearqdbf");
  1121. /* clear outbound buffers to free skbs */
  1122. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1123. if (card->qdio.out_qs[i]) {
  1124. qeth_clear_outq_buffers(card->qdio.out_qs[i], 0);
  1125. }
  1126. }
  1127. }
  1128. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  1129. static void qeth_free_buffer_pool(struct qeth_card *card)
  1130. {
  1131. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  1132. int i = 0;
  1133. list_for_each_entry_safe(pool_entry, tmp,
  1134. &card->qdio.init_pool.entry_list, init_list){
  1135. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  1136. free_page((unsigned long)pool_entry->elements[i]);
  1137. list_del(&pool_entry->init_list);
  1138. kfree(pool_entry);
  1139. }
  1140. }
  1141. static void qeth_free_qdio_buffers(struct qeth_card *card)
  1142. {
  1143. int i, j;
  1144. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  1145. QETH_QDIO_UNINITIALIZED)
  1146. return;
  1147. qeth_free_cq(card);
  1148. cancel_delayed_work_sync(&card->buffer_reclaim_work);
  1149. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1150. if (card->qdio.in_q->bufs[j].rx_skb)
  1151. dev_kfree_skb_any(card->qdio.in_q->bufs[j].rx_skb);
  1152. }
  1153. kfree(card->qdio.in_q);
  1154. card->qdio.in_q = NULL;
  1155. /* inbound buffer pool */
  1156. qeth_free_buffer_pool(card);
  1157. /* free outbound qdio_qs */
  1158. if (card->qdio.out_qs) {
  1159. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1160. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  1161. kfree(card->qdio.out_qs[i]);
  1162. }
  1163. kfree(card->qdio.out_qs);
  1164. card->qdio.out_qs = NULL;
  1165. }
  1166. }
  1167. static void qeth_clean_channel(struct qeth_channel *channel)
  1168. {
  1169. int cnt;
  1170. QETH_DBF_TEXT(SETUP, 2, "freech");
  1171. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  1172. kfree(channel->iob[cnt].data);
  1173. }
  1174. static void qeth_set_single_write_queues(struct qeth_card *card)
  1175. {
  1176. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1177. (card->qdio.no_out_queues == 4))
  1178. qeth_free_qdio_buffers(card);
  1179. card->qdio.no_out_queues = 1;
  1180. if (card->qdio.default_out_queue != 0)
  1181. dev_info(&card->gdev->dev, "Priority Queueing not supported\n");
  1182. card->qdio.default_out_queue = 0;
  1183. }
  1184. static void qeth_set_multiple_write_queues(struct qeth_card *card)
  1185. {
  1186. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1187. (card->qdio.no_out_queues == 1)) {
  1188. qeth_free_qdio_buffers(card);
  1189. card->qdio.default_out_queue = 2;
  1190. }
  1191. card->qdio.no_out_queues = 4;
  1192. }
  1193. static void qeth_update_from_chp_desc(struct qeth_card *card)
  1194. {
  1195. struct ccw_device *ccwdev;
  1196. struct channelPath_dsc {
  1197. u8 flags;
  1198. u8 lsn;
  1199. u8 desc;
  1200. u8 chpid;
  1201. u8 swla;
  1202. u8 zeroes;
  1203. u8 chla;
  1204. u8 chpp;
  1205. } *chp_dsc;
  1206. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  1207. ccwdev = card->data.ccwdev;
  1208. chp_dsc = ccw_device_get_chp_desc(ccwdev, 0);
  1209. if (!chp_dsc)
  1210. goto out;
  1211. card->info.func_level = 0x4100 + chp_dsc->desc;
  1212. if (card->info.type == QETH_CARD_TYPE_IQD)
  1213. goto out;
  1214. /* CHPP field bit 6 == 1 -> single queue */
  1215. if ((chp_dsc->chpp & 0x02) == 0x02)
  1216. qeth_set_single_write_queues(card);
  1217. else
  1218. qeth_set_multiple_write_queues(card);
  1219. out:
  1220. kfree(chp_dsc);
  1221. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  1222. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  1223. }
  1224. static void qeth_init_qdio_info(struct qeth_card *card)
  1225. {
  1226. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  1227. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1228. /* inbound */
  1229. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1230. if (card->info.type == QETH_CARD_TYPE_IQD)
  1231. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  1232. else
  1233. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  1234. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  1235. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  1236. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  1237. }
  1238. static void qeth_set_intial_options(struct qeth_card *card)
  1239. {
  1240. card->options.route4.type = NO_ROUTER;
  1241. card->options.route6.type = NO_ROUTER;
  1242. card->options.fake_broadcast = 0;
  1243. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  1244. card->options.performance_stats = 0;
  1245. card->options.rx_sg_cb = QETH_RX_SG_CB;
  1246. card->options.isolation = ISOLATION_MODE_NONE;
  1247. card->options.cq = QETH_CQ_DISABLED;
  1248. }
  1249. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  1250. {
  1251. unsigned long flags;
  1252. int rc = 0;
  1253. spin_lock_irqsave(&card->thread_mask_lock, flags);
  1254. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  1255. (u8) card->thread_start_mask,
  1256. (u8) card->thread_allowed_mask,
  1257. (u8) card->thread_running_mask);
  1258. rc = (card->thread_start_mask & thread);
  1259. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  1260. return rc;
  1261. }
  1262. static void qeth_start_kernel_thread(struct work_struct *work)
  1263. {
  1264. struct task_struct *ts;
  1265. struct qeth_card *card = container_of(work, struct qeth_card,
  1266. kernel_thread_starter);
  1267. QETH_CARD_TEXT(card , 2, "strthrd");
  1268. if (card->read.state != CH_STATE_UP &&
  1269. card->write.state != CH_STATE_UP)
  1270. return;
  1271. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD)) {
  1272. ts = kthread_run(card->discipline->recover, (void *)card,
  1273. "qeth_recover");
  1274. if (IS_ERR(ts)) {
  1275. qeth_clear_thread_start_bit(card, QETH_RECOVER_THREAD);
  1276. qeth_clear_thread_running_bit(card,
  1277. QETH_RECOVER_THREAD);
  1278. }
  1279. }
  1280. }
  1281. static int qeth_setup_card(struct qeth_card *card)
  1282. {
  1283. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1284. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1285. card->read.state = CH_STATE_DOWN;
  1286. card->write.state = CH_STATE_DOWN;
  1287. card->data.state = CH_STATE_DOWN;
  1288. card->state = CARD_STATE_DOWN;
  1289. card->lan_online = 0;
  1290. card->read_or_write_problem = 0;
  1291. card->dev = NULL;
  1292. spin_lock_init(&card->vlanlock);
  1293. spin_lock_init(&card->mclock);
  1294. spin_lock_init(&card->lock);
  1295. spin_lock_init(&card->ip_lock);
  1296. spin_lock_init(&card->thread_mask_lock);
  1297. mutex_init(&card->conf_mutex);
  1298. mutex_init(&card->discipline_mutex);
  1299. card->thread_start_mask = 0;
  1300. card->thread_allowed_mask = 0;
  1301. card->thread_running_mask = 0;
  1302. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1303. INIT_LIST_HEAD(&card->ip_list);
  1304. INIT_LIST_HEAD(card->ip_tbd_list);
  1305. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1306. init_waitqueue_head(&card->wait_q);
  1307. /* initial options */
  1308. qeth_set_intial_options(card);
  1309. /* IP address takeover */
  1310. INIT_LIST_HEAD(&card->ipato.entries);
  1311. card->ipato.enabled = 0;
  1312. card->ipato.invert4 = 0;
  1313. card->ipato.invert6 = 0;
  1314. /* init QDIO stuff */
  1315. qeth_init_qdio_info(card);
  1316. INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work);
  1317. INIT_WORK(&card->close_dev_work, qeth_close_dev_handler);
  1318. return 0;
  1319. }
  1320. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1321. {
  1322. struct qeth_card *card = container_of(slr, struct qeth_card,
  1323. qeth_service_level);
  1324. if (card->info.mcl_level[0])
  1325. seq_printf(m, "qeth: %s firmware level %s\n",
  1326. CARD_BUS_ID(card), card->info.mcl_level);
  1327. }
  1328. static struct qeth_card *qeth_alloc_card(void)
  1329. {
  1330. struct qeth_card *card;
  1331. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1332. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1333. if (!card)
  1334. goto out;
  1335. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1336. card->ip_tbd_list = kzalloc(sizeof(struct list_head), GFP_KERNEL);
  1337. if (!card->ip_tbd_list) {
  1338. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1339. goto out_card;
  1340. }
  1341. if (qeth_setup_channel(&card->read))
  1342. goto out_ip;
  1343. if (qeth_setup_channel(&card->write))
  1344. goto out_channel;
  1345. card->options.layer2 = -1;
  1346. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1347. register_service_level(&card->qeth_service_level);
  1348. return card;
  1349. out_channel:
  1350. qeth_clean_channel(&card->read);
  1351. out_ip:
  1352. kfree(card->ip_tbd_list);
  1353. out_card:
  1354. kfree(card);
  1355. out:
  1356. return NULL;
  1357. }
  1358. static int qeth_determine_card_type(struct qeth_card *card)
  1359. {
  1360. int i = 0;
  1361. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1362. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1363. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1364. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1365. if ((CARD_RDEV(card)->id.dev_type ==
  1366. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1367. (CARD_RDEV(card)->id.dev_model ==
  1368. known_devices[i][QETH_DEV_MODEL_IND])) {
  1369. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1370. card->qdio.no_out_queues =
  1371. known_devices[i][QETH_QUEUE_NO_IND];
  1372. card->qdio.no_in_queues = 1;
  1373. card->info.is_multicast_different =
  1374. known_devices[i][QETH_MULTICAST_IND];
  1375. qeth_update_from_chp_desc(card);
  1376. return 0;
  1377. }
  1378. i++;
  1379. }
  1380. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1381. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1382. "unknown type\n");
  1383. return -ENOENT;
  1384. }
  1385. static int qeth_clear_channel(struct qeth_channel *channel)
  1386. {
  1387. unsigned long flags;
  1388. struct qeth_card *card;
  1389. int rc;
  1390. card = CARD_FROM_CDEV(channel->ccwdev);
  1391. QETH_CARD_TEXT(card, 3, "clearch");
  1392. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1393. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1394. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1395. if (rc)
  1396. return rc;
  1397. rc = wait_event_interruptible_timeout(card->wait_q,
  1398. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1399. if (rc == -ERESTARTSYS)
  1400. return rc;
  1401. if (channel->state != CH_STATE_STOPPED)
  1402. return -ETIME;
  1403. channel->state = CH_STATE_DOWN;
  1404. return 0;
  1405. }
  1406. static int qeth_halt_channel(struct qeth_channel *channel)
  1407. {
  1408. unsigned long flags;
  1409. struct qeth_card *card;
  1410. int rc;
  1411. card = CARD_FROM_CDEV(channel->ccwdev);
  1412. QETH_CARD_TEXT(card, 3, "haltch");
  1413. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1414. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1415. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1416. if (rc)
  1417. return rc;
  1418. rc = wait_event_interruptible_timeout(card->wait_q,
  1419. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1420. if (rc == -ERESTARTSYS)
  1421. return rc;
  1422. if (channel->state != CH_STATE_HALTED)
  1423. return -ETIME;
  1424. return 0;
  1425. }
  1426. static int qeth_halt_channels(struct qeth_card *card)
  1427. {
  1428. int rc1 = 0, rc2 = 0, rc3 = 0;
  1429. QETH_CARD_TEXT(card, 3, "haltchs");
  1430. rc1 = qeth_halt_channel(&card->read);
  1431. rc2 = qeth_halt_channel(&card->write);
  1432. rc3 = qeth_halt_channel(&card->data);
  1433. if (rc1)
  1434. return rc1;
  1435. if (rc2)
  1436. return rc2;
  1437. return rc3;
  1438. }
  1439. static int qeth_clear_channels(struct qeth_card *card)
  1440. {
  1441. int rc1 = 0, rc2 = 0, rc3 = 0;
  1442. QETH_CARD_TEXT(card, 3, "clearchs");
  1443. rc1 = qeth_clear_channel(&card->read);
  1444. rc2 = qeth_clear_channel(&card->write);
  1445. rc3 = qeth_clear_channel(&card->data);
  1446. if (rc1)
  1447. return rc1;
  1448. if (rc2)
  1449. return rc2;
  1450. return rc3;
  1451. }
  1452. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1453. {
  1454. int rc = 0;
  1455. QETH_CARD_TEXT(card, 3, "clhacrd");
  1456. if (halt)
  1457. rc = qeth_halt_channels(card);
  1458. if (rc)
  1459. return rc;
  1460. return qeth_clear_channels(card);
  1461. }
  1462. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1463. {
  1464. int rc = 0;
  1465. QETH_CARD_TEXT(card, 3, "qdioclr");
  1466. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1467. QETH_QDIO_CLEANING)) {
  1468. case QETH_QDIO_ESTABLISHED:
  1469. if (card->info.type == QETH_CARD_TYPE_IQD)
  1470. rc = qdio_shutdown(CARD_DDEV(card),
  1471. QDIO_FLAG_CLEANUP_USING_HALT);
  1472. else
  1473. rc = qdio_shutdown(CARD_DDEV(card),
  1474. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1475. if (rc)
  1476. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1477. qdio_free(CARD_DDEV(card));
  1478. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1479. break;
  1480. case QETH_QDIO_CLEANING:
  1481. return rc;
  1482. default:
  1483. break;
  1484. }
  1485. rc = qeth_clear_halt_card(card, use_halt);
  1486. if (rc)
  1487. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1488. card->state = CARD_STATE_DOWN;
  1489. return rc;
  1490. }
  1491. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1492. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1493. int *length)
  1494. {
  1495. struct ciw *ciw;
  1496. char *rcd_buf;
  1497. int ret;
  1498. struct qeth_channel *channel = &card->data;
  1499. unsigned long flags;
  1500. /*
  1501. * scan for RCD command in extended SenseID data
  1502. */
  1503. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1504. if (!ciw || ciw->cmd == 0)
  1505. return -EOPNOTSUPP;
  1506. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1507. if (!rcd_buf)
  1508. return -ENOMEM;
  1509. channel->ccw.cmd_code = ciw->cmd;
  1510. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1511. channel->ccw.count = ciw->count;
  1512. channel->ccw.flags = CCW_FLAG_SLI;
  1513. channel->state = CH_STATE_RCD;
  1514. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1515. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1516. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1517. QETH_RCD_TIMEOUT);
  1518. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1519. if (!ret)
  1520. wait_event(card->wait_q,
  1521. (channel->state == CH_STATE_RCD_DONE ||
  1522. channel->state == CH_STATE_DOWN));
  1523. if (channel->state == CH_STATE_DOWN)
  1524. ret = -EIO;
  1525. else
  1526. channel->state = CH_STATE_DOWN;
  1527. if (ret) {
  1528. kfree(rcd_buf);
  1529. *buffer = NULL;
  1530. *length = 0;
  1531. } else {
  1532. *length = ciw->count;
  1533. *buffer = rcd_buf;
  1534. }
  1535. return ret;
  1536. }
  1537. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1538. {
  1539. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1540. card->info.chpid = prcd[30];
  1541. card->info.unit_addr2 = prcd[31];
  1542. card->info.cula = prcd[63];
  1543. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1544. (prcd[0x11] == _ascebc['M']));
  1545. }
  1546. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1547. {
  1548. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1549. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 &&
  1550. prcd[76] >= 0xF1 && prcd[76] <= 0xF4) {
  1551. card->info.blkt.time_total = 0;
  1552. card->info.blkt.inter_packet = 0;
  1553. card->info.blkt.inter_packet_jumbo = 0;
  1554. } else {
  1555. card->info.blkt.time_total = 250;
  1556. card->info.blkt.inter_packet = 5;
  1557. card->info.blkt.inter_packet_jumbo = 15;
  1558. }
  1559. }
  1560. static void qeth_init_tokens(struct qeth_card *card)
  1561. {
  1562. card->token.issuer_rm_w = 0x00010103UL;
  1563. card->token.cm_filter_w = 0x00010108UL;
  1564. card->token.cm_connection_w = 0x0001010aUL;
  1565. card->token.ulp_filter_w = 0x0001010bUL;
  1566. card->token.ulp_connection_w = 0x0001010dUL;
  1567. }
  1568. static void qeth_init_func_level(struct qeth_card *card)
  1569. {
  1570. switch (card->info.type) {
  1571. case QETH_CARD_TYPE_IQD:
  1572. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1573. break;
  1574. case QETH_CARD_TYPE_OSD:
  1575. case QETH_CARD_TYPE_OSN:
  1576. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1577. break;
  1578. default:
  1579. break;
  1580. }
  1581. }
  1582. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1583. void (*idx_reply_cb)(struct qeth_channel *,
  1584. struct qeth_cmd_buffer *))
  1585. {
  1586. struct qeth_cmd_buffer *iob;
  1587. unsigned long flags;
  1588. int rc;
  1589. struct qeth_card *card;
  1590. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1591. card = CARD_FROM_CDEV(channel->ccwdev);
  1592. iob = qeth_get_buffer(channel);
  1593. iob->callback = idx_reply_cb;
  1594. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1595. channel->ccw.count = QETH_BUFSIZE;
  1596. channel->ccw.cda = (__u32) __pa(iob->data);
  1597. wait_event(card->wait_q,
  1598. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1599. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1600. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1601. rc = ccw_device_start(channel->ccwdev,
  1602. &channel->ccw, (addr_t) iob, 0, 0);
  1603. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1604. if (rc) {
  1605. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1606. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1607. atomic_set(&channel->irq_pending, 0);
  1608. wake_up(&card->wait_q);
  1609. return rc;
  1610. }
  1611. rc = wait_event_interruptible_timeout(card->wait_q,
  1612. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1613. if (rc == -ERESTARTSYS)
  1614. return rc;
  1615. if (channel->state != CH_STATE_UP) {
  1616. rc = -ETIME;
  1617. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1618. qeth_clear_cmd_buffers(channel);
  1619. } else
  1620. rc = 0;
  1621. return rc;
  1622. }
  1623. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1624. void (*idx_reply_cb)(struct qeth_channel *,
  1625. struct qeth_cmd_buffer *))
  1626. {
  1627. struct qeth_card *card;
  1628. struct qeth_cmd_buffer *iob;
  1629. unsigned long flags;
  1630. __u16 temp;
  1631. __u8 tmp;
  1632. int rc;
  1633. struct ccw_dev_id temp_devid;
  1634. card = CARD_FROM_CDEV(channel->ccwdev);
  1635. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1636. iob = qeth_get_buffer(channel);
  1637. iob->callback = idx_reply_cb;
  1638. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1639. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1640. channel->ccw.cda = (__u32) __pa(iob->data);
  1641. if (channel == &card->write) {
  1642. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1643. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1644. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1645. card->seqno.trans_hdr++;
  1646. } else {
  1647. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1648. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1649. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1650. }
  1651. tmp = ((__u8)card->info.portno) | 0x80;
  1652. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1653. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1654. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1655. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1656. &card->info.func_level, sizeof(__u16));
  1657. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1658. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1659. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1660. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1661. wait_event(card->wait_q,
  1662. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1663. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1664. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1665. rc = ccw_device_start(channel->ccwdev,
  1666. &channel->ccw, (addr_t) iob, 0, 0);
  1667. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1668. if (rc) {
  1669. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1670. rc);
  1671. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1672. atomic_set(&channel->irq_pending, 0);
  1673. wake_up(&card->wait_q);
  1674. return rc;
  1675. }
  1676. rc = wait_event_interruptible_timeout(card->wait_q,
  1677. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1678. if (rc == -ERESTARTSYS)
  1679. return rc;
  1680. if (channel->state != CH_STATE_ACTIVATING) {
  1681. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1682. " failed to recover an error on the device\n");
  1683. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1684. dev_name(&channel->ccwdev->dev));
  1685. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1686. qeth_clear_cmd_buffers(channel);
  1687. return -ETIME;
  1688. }
  1689. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1690. }
  1691. static int qeth_peer_func_level(int level)
  1692. {
  1693. if ((level & 0xff) == 8)
  1694. return (level & 0xff) + 0x400;
  1695. if (((level >> 8) & 3) == 1)
  1696. return (level & 0xff) + 0x200;
  1697. return level;
  1698. }
  1699. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1700. struct qeth_cmd_buffer *iob)
  1701. {
  1702. struct qeth_card *card;
  1703. __u16 temp;
  1704. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1705. if (channel->state == CH_STATE_DOWN) {
  1706. channel->state = CH_STATE_ACTIVATING;
  1707. goto out;
  1708. }
  1709. card = CARD_FROM_CDEV(channel->ccwdev);
  1710. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1711. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1712. dev_err(&card->write.ccwdev->dev,
  1713. "The adapter is used exclusively by another "
  1714. "host\n");
  1715. else
  1716. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1717. " negative reply\n",
  1718. dev_name(&card->write.ccwdev->dev));
  1719. goto out;
  1720. }
  1721. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1722. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1723. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1724. "function level mismatch (sent: 0x%x, received: "
  1725. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1726. card->info.func_level, temp);
  1727. goto out;
  1728. }
  1729. channel->state = CH_STATE_UP;
  1730. out:
  1731. qeth_release_buffer(channel, iob);
  1732. }
  1733. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1734. struct qeth_cmd_buffer *iob)
  1735. {
  1736. struct qeth_card *card;
  1737. __u16 temp;
  1738. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1739. if (channel->state == CH_STATE_DOWN) {
  1740. channel->state = CH_STATE_ACTIVATING;
  1741. goto out;
  1742. }
  1743. card = CARD_FROM_CDEV(channel->ccwdev);
  1744. if (qeth_check_idx_response(card, iob->data))
  1745. goto out;
  1746. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1747. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1748. case QETH_IDX_ACT_ERR_EXCL:
  1749. dev_err(&card->write.ccwdev->dev,
  1750. "The adapter is used exclusively by another "
  1751. "host\n");
  1752. break;
  1753. case QETH_IDX_ACT_ERR_AUTH:
  1754. case QETH_IDX_ACT_ERR_AUTH_USER:
  1755. dev_err(&card->read.ccwdev->dev,
  1756. "Setting the device online failed because of "
  1757. "insufficient authorization\n");
  1758. break;
  1759. default:
  1760. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1761. " negative reply\n",
  1762. dev_name(&card->read.ccwdev->dev));
  1763. }
  1764. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1765. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1766. goto out;
  1767. }
  1768. /**
  1769. * * temporary fix for microcode bug
  1770. * * to revert it,replace OR by AND
  1771. * */
  1772. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1773. (card->info.type == QETH_CARD_TYPE_OSD))
  1774. card->info.portname_required = 1;
  1775. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1776. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1777. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1778. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1779. dev_name(&card->read.ccwdev->dev),
  1780. card->info.func_level, temp);
  1781. goto out;
  1782. }
  1783. memcpy(&card->token.issuer_rm_r,
  1784. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1785. QETH_MPC_TOKEN_LENGTH);
  1786. memcpy(&card->info.mcl_level[0],
  1787. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1788. channel->state = CH_STATE_UP;
  1789. out:
  1790. qeth_release_buffer(channel, iob);
  1791. }
  1792. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1793. struct qeth_cmd_buffer *iob)
  1794. {
  1795. qeth_setup_ccw(&card->write, iob->data, len);
  1796. iob->callback = qeth_release_buffer;
  1797. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1798. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1799. card->seqno.trans_hdr++;
  1800. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1801. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1802. card->seqno.pdu_hdr++;
  1803. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1804. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1805. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1806. }
  1807. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1808. int qeth_send_control_data(struct qeth_card *card, int len,
  1809. struct qeth_cmd_buffer *iob,
  1810. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1811. unsigned long),
  1812. void *reply_param)
  1813. {
  1814. int rc;
  1815. unsigned long flags;
  1816. struct qeth_reply *reply = NULL;
  1817. unsigned long timeout, event_timeout;
  1818. struct qeth_ipa_cmd *cmd;
  1819. QETH_CARD_TEXT(card, 2, "sendctl");
  1820. if (card->read_or_write_problem) {
  1821. qeth_release_buffer(iob->channel, iob);
  1822. return -EIO;
  1823. }
  1824. reply = qeth_alloc_reply(card);
  1825. if (!reply) {
  1826. return -ENOMEM;
  1827. }
  1828. reply->callback = reply_cb;
  1829. reply->param = reply_param;
  1830. if (card->state == CARD_STATE_DOWN)
  1831. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1832. else
  1833. reply->seqno = card->seqno.ipa++;
  1834. init_waitqueue_head(&reply->wait_q);
  1835. spin_lock_irqsave(&card->lock, flags);
  1836. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1837. spin_unlock_irqrestore(&card->lock, flags);
  1838. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1839. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1840. qeth_prepare_control_data(card, len, iob);
  1841. if (IS_IPA(iob->data))
  1842. event_timeout = QETH_IPA_TIMEOUT;
  1843. else
  1844. event_timeout = QETH_TIMEOUT;
  1845. timeout = jiffies + event_timeout;
  1846. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1847. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1848. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1849. (addr_t) iob, 0, 0);
  1850. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1851. if (rc) {
  1852. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1853. "ccw_device_start rc = %i\n",
  1854. dev_name(&card->write.ccwdev->dev), rc);
  1855. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1856. spin_lock_irqsave(&card->lock, flags);
  1857. list_del_init(&reply->list);
  1858. qeth_put_reply(reply);
  1859. spin_unlock_irqrestore(&card->lock, flags);
  1860. qeth_release_buffer(iob->channel, iob);
  1861. atomic_set(&card->write.irq_pending, 0);
  1862. wake_up(&card->wait_q);
  1863. return rc;
  1864. }
  1865. /* we have only one long running ipassist, since we can ensure
  1866. process context of this command we can sleep */
  1867. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1868. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1869. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1870. if (!wait_event_timeout(reply->wait_q,
  1871. atomic_read(&reply->received), event_timeout))
  1872. goto time_err;
  1873. } else {
  1874. while (!atomic_read(&reply->received)) {
  1875. if (time_after(jiffies, timeout))
  1876. goto time_err;
  1877. cpu_relax();
  1878. }
  1879. }
  1880. if (reply->rc == -EIO)
  1881. goto error;
  1882. rc = reply->rc;
  1883. qeth_put_reply(reply);
  1884. return rc;
  1885. time_err:
  1886. reply->rc = -ETIME;
  1887. spin_lock_irqsave(&reply->card->lock, flags);
  1888. list_del_init(&reply->list);
  1889. spin_unlock_irqrestore(&reply->card->lock, flags);
  1890. atomic_inc(&reply->received);
  1891. error:
  1892. atomic_set(&card->write.irq_pending, 0);
  1893. qeth_release_buffer(iob->channel, iob);
  1894. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1895. rc = reply->rc;
  1896. qeth_put_reply(reply);
  1897. return rc;
  1898. }
  1899. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1900. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1901. unsigned long data)
  1902. {
  1903. struct qeth_cmd_buffer *iob;
  1904. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1905. iob = (struct qeth_cmd_buffer *) data;
  1906. memcpy(&card->token.cm_filter_r,
  1907. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1908. QETH_MPC_TOKEN_LENGTH);
  1909. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1910. return 0;
  1911. }
  1912. static int qeth_cm_enable(struct qeth_card *card)
  1913. {
  1914. int rc;
  1915. struct qeth_cmd_buffer *iob;
  1916. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1917. iob = qeth_wait_for_buffer(&card->write);
  1918. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1919. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1920. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1921. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1922. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1923. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1924. qeth_cm_enable_cb, NULL);
  1925. return rc;
  1926. }
  1927. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1928. unsigned long data)
  1929. {
  1930. struct qeth_cmd_buffer *iob;
  1931. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1932. iob = (struct qeth_cmd_buffer *) data;
  1933. memcpy(&card->token.cm_connection_r,
  1934. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1935. QETH_MPC_TOKEN_LENGTH);
  1936. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1937. return 0;
  1938. }
  1939. static int qeth_cm_setup(struct qeth_card *card)
  1940. {
  1941. int rc;
  1942. struct qeth_cmd_buffer *iob;
  1943. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1944. iob = qeth_wait_for_buffer(&card->write);
  1945. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1946. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1947. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1948. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1949. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1950. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1951. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1952. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1953. qeth_cm_setup_cb, NULL);
  1954. return rc;
  1955. }
  1956. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1957. {
  1958. switch (card->info.type) {
  1959. case QETH_CARD_TYPE_UNKNOWN:
  1960. return 1500;
  1961. case QETH_CARD_TYPE_IQD:
  1962. return card->info.max_mtu;
  1963. case QETH_CARD_TYPE_OSD:
  1964. switch (card->info.link_type) {
  1965. case QETH_LINK_TYPE_HSTR:
  1966. case QETH_LINK_TYPE_LANE_TR:
  1967. return 2000;
  1968. default:
  1969. return card->options.layer2 ? 1500 : 1492;
  1970. }
  1971. case QETH_CARD_TYPE_OSM:
  1972. case QETH_CARD_TYPE_OSX:
  1973. return card->options.layer2 ? 1500 : 1492;
  1974. default:
  1975. return 1500;
  1976. }
  1977. }
  1978. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1979. {
  1980. switch (framesize) {
  1981. case 0x4000:
  1982. return 8192;
  1983. case 0x6000:
  1984. return 16384;
  1985. case 0xa000:
  1986. return 32768;
  1987. case 0xffff:
  1988. return 57344;
  1989. default:
  1990. return 0;
  1991. }
  1992. }
  1993. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1994. {
  1995. switch (card->info.type) {
  1996. case QETH_CARD_TYPE_OSD:
  1997. case QETH_CARD_TYPE_OSM:
  1998. case QETH_CARD_TYPE_OSX:
  1999. case QETH_CARD_TYPE_IQD:
  2000. return ((mtu >= 576) &&
  2001. (mtu <= card->info.max_mtu));
  2002. case QETH_CARD_TYPE_OSN:
  2003. case QETH_CARD_TYPE_UNKNOWN:
  2004. default:
  2005. return 1;
  2006. }
  2007. }
  2008. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  2009. unsigned long data)
  2010. {
  2011. __u16 mtu, framesize;
  2012. __u16 len;
  2013. __u8 link_type;
  2014. struct qeth_cmd_buffer *iob;
  2015. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  2016. iob = (struct qeth_cmd_buffer *) data;
  2017. memcpy(&card->token.ulp_filter_r,
  2018. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  2019. QETH_MPC_TOKEN_LENGTH);
  2020. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2021. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  2022. mtu = qeth_get_mtu_outof_framesize(framesize);
  2023. if (!mtu) {
  2024. iob->rc = -EINVAL;
  2025. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2026. return 0;
  2027. }
  2028. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  2029. /* frame size has changed */
  2030. if (card->dev &&
  2031. ((card->dev->mtu == card->info.initial_mtu) ||
  2032. (card->dev->mtu > mtu)))
  2033. card->dev->mtu = mtu;
  2034. qeth_free_qdio_buffers(card);
  2035. }
  2036. card->info.initial_mtu = mtu;
  2037. card->info.max_mtu = mtu;
  2038. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  2039. } else {
  2040. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  2041. iob->data);
  2042. card->info.initial_mtu = min(card->info.max_mtu,
  2043. qeth_get_initial_mtu_for_card(card));
  2044. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  2045. }
  2046. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  2047. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  2048. memcpy(&link_type,
  2049. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  2050. card->info.link_type = link_type;
  2051. } else
  2052. card->info.link_type = 0;
  2053. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  2054. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2055. return 0;
  2056. }
  2057. static int qeth_ulp_enable(struct qeth_card *card)
  2058. {
  2059. int rc;
  2060. char prot_type;
  2061. struct qeth_cmd_buffer *iob;
  2062. /*FIXME: trace view callbacks*/
  2063. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  2064. iob = qeth_wait_for_buffer(&card->write);
  2065. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  2066. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  2067. (__u8) card->info.portno;
  2068. if (card->options.layer2)
  2069. if (card->info.type == QETH_CARD_TYPE_OSN)
  2070. prot_type = QETH_PROT_OSN2;
  2071. else
  2072. prot_type = QETH_PROT_LAYER2;
  2073. else
  2074. prot_type = QETH_PROT_TCPIP;
  2075. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  2076. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  2077. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2078. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  2079. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  2080. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  2081. card->info.portname, 9);
  2082. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  2083. qeth_ulp_enable_cb, NULL);
  2084. return rc;
  2085. }
  2086. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  2087. unsigned long data)
  2088. {
  2089. struct qeth_cmd_buffer *iob;
  2090. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  2091. iob = (struct qeth_cmd_buffer *) data;
  2092. memcpy(&card->token.ulp_connection_r,
  2093. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2094. QETH_MPC_TOKEN_LENGTH);
  2095. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2096. 3)) {
  2097. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  2098. dev_err(&card->gdev->dev, "A connection could not be "
  2099. "established because of an OLM limit\n");
  2100. iob->rc = -EMLINK;
  2101. }
  2102. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2103. return 0;
  2104. }
  2105. static int qeth_ulp_setup(struct qeth_card *card)
  2106. {
  2107. int rc;
  2108. __u16 temp;
  2109. struct qeth_cmd_buffer *iob;
  2110. struct ccw_dev_id dev_id;
  2111. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  2112. iob = qeth_wait_for_buffer(&card->write);
  2113. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  2114. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  2115. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2116. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  2117. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  2118. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  2119. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  2120. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  2121. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  2122. temp = (card->info.cula << 8) + card->info.unit_addr2;
  2123. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  2124. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  2125. qeth_ulp_setup_cb, NULL);
  2126. return rc;
  2127. }
  2128. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *q, int bidx)
  2129. {
  2130. int rc;
  2131. struct qeth_qdio_out_buffer *newbuf;
  2132. rc = 0;
  2133. newbuf = kmem_cache_zalloc(qeth_qdio_outbuf_cache, GFP_ATOMIC);
  2134. if (!newbuf) {
  2135. rc = -ENOMEM;
  2136. goto out;
  2137. }
  2138. newbuf->buffer = &q->qdio_bufs[bidx];
  2139. skb_queue_head_init(&newbuf->skb_list);
  2140. lockdep_set_class(&newbuf->skb_list.lock, &qdio_out_skb_queue_key);
  2141. newbuf->q = q;
  2142. newbuf->aob = NULL;
  2143. newbuf->next_pending = q->bufs[bidx];
  2144. atomic_set(&newbuf->state, QETH_QDIO_BUF_EMPTY);
  2145. q->bufs[bidx] = newbuf;
  2146. if (q->bufstates) {
  2147. q->bufstates[bidx].user = newbuf;
  2148. QETH_CARD_TEXT_(q->card, 2, "nbs%d", bidx);
  2149. QETH_CARD_TEXT_(q->card, 2, "%lx", (long) newbuf);
  2150. QETH_CARD_TEXT_(q->card, 2, "%lx",
  2151. (long) newbuf->next_pending);
  2152. }
  2153. out:
  2154. return rc;
  2155. }
  2156. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  2157. {
  2158. int i, j;
  2159. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  2160. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  2161. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  2162. return 0;
  2163. card->qdio.in_q = kzalloc(sizeof(struct qeth_qdio_q),
  2164. GFP_KERNEL);
  2165. if (!card->qdio.in_q)
  2166. goto out_nomem;
  2167. QETH_DBF_TEXT(SETUP, 2, "inq");
  2168. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  2169. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  2170. /* give inbound qeth_qdio_buffers their qdio_buffers */
  2171. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  2172. card->qdio.in_q->bufs[i].buffer =
  2173. &card->qdio.in_q->qdio_bufs[i];
  2174. card->qdio.in_q->bufs[i].rx_skb = NULL;
  2175. }
  2176. /* inbound buffer pool */
  2177. if (qeth_alloc_buffer_pool(card))
  2178. goto out_freeinq;
  2179. /* outbound */
  2180. card->qdio.out_qs =
  2181. kzalloc(card->qdio.no_out_queues *
  2182. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  2183. if (!card->qdio.out_qs)
  2184. goto out_freepool;
  2185. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2186. card->qdio.out_qs[i] = kzalloc(sizeof(struct qeth_qdio_out_q),
  2187. GFP_KERNEL);
  2188. if (!card->qdio.out_qs[i])
  2189. goto out_freeoutq;
  2190. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  2191. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  2192. card->qdio.out_qs[i]->queue_no = i;
  2193. /* give outbound qeth_qdio_buffers their qdio_buffers */
  2194. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2195. WARN_ON(card->qdio.out_qs[i]->bufs[j] != NULL);
  2196. if (qeth_init_qdio_out_buf(card->qdio.out_qs[i], j))
  2197. goto out_freeoutqbufs;
  2198. }
  2199. }
  2200. /* completion */
  2201. if (qeth_alloc_cq(card))
  2202. goto out_freeoutq;
  2203. return 0;
  2204. out_freeoutqbufs:
  2205. while (j > 0) {
  2206. --j;
  2207. kmem_cache_free(qeth_qdio_outbuf_cache,
  2208. card->qdio.out_qs[i]->bufs[j]);
  2209. card->qdio.out_qs[i]->bufs[j] = NULL;
  2210. }
  2211. out_freeoutq:
  2212. while (i > 0) {
  2213. kfree(card->qdio.out_qs[--i]);
  2214. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  2215. }
  2216. kfree(card->qdio.out_qs);
  2217. card->qdio.out_qs = NULL;
  2218. out_freepool:
  2219. qeth_free_buffer_pool(card);
  2220. out_freeinq:
  2221. kfree(card->qdio.in_q);
  2222. card->qdio.in_q = NULL;
  2223. out_nomem:
  2224. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  2225. return -ENOMEM;
  2226. }
  2227. static void qeth_create_qib_param_field(struct qeth_card *card,
  2228. char *param_field)
  2229. {
  2230. param_field[0] = _ascebc['P'];
  2231. param_field[1] = _ascebc['C'];
  2232. param_field[2] = _ascebc['I'];
  2233. param_field[3] = _ascebc['T'];
  2234. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  2235. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  2236. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  2237. }
  2238. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  2239. char *param_field)
  2240. {
  2241. param_field[16] = _ascebc['B'];
  2242. param_field[17] = _ascebc['L'];
  2243. param_field[18] = _ascebc['K'];
  2244. param_field[19] = _ascebc['T'];
  2245. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  2246. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  2247. *((unsigned int *) (&param_field[28])) =
  2248. card->info.blkt.inter_packet_jumbo;
  2249. }
  2250. static int qeth_qdio_activate(struct qeth_card *card)
  2251. {
  2252. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  2253. return qdio_activate(CARD_DDEV(card));
  2254. }
  2255. static int qeth_dm_act(struct qeth_card *card)
  2256. {
  2257. int rc;
  2258. struct qeth_cmd_buffer *iob;
  2259. QETH_DBF_TEXT(SETUP, 2, "dmact");
  2260. iob = qeth_wait_for_buffer(&card->write);
  2261. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  2262. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  2263. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2264. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  2265. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2266. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  2267. return rc;
  2268. }
  2269. static int qeth_mpc_initialize(struct qeth_card *card)
  2270. {
  2271. int rc;
  2272. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  2273. rc = qeth_issue_next_read(card);
  2274. if (rc) {
  2275. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2276. return rc;
  2277. }
  2278. rc = qeth_cm_enable(card);
  2279. if (rc) {
  2280. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2281. goto out_qdio;
  2282. }
  2283. rc = qeth_cm_setup(card);
  2284. if (rc) {
  2285. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  2286. goto out_qdio;
  2287. }
  2288. rc = qeth_ulp_enable(card);
  2289. if (rc) {
  2290. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  2291. goto out_qdio;
  2292. }
  2293. rc = qeth_ulp_setup(card);
  2294. if (rc) {
  2295. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2296. goto out_qdio;
  2297. }
  2298. rc = qeth_alloc_qdio_buffers(card);
  2299. if (rc) {
  2300. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2301. goto out_qdio;
  2302. }
  2303. rc = qeth_qdio_establish(card);
  2304. if (rc) {
  2305. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  2306. qeth_free_qdio_buffers(card);
  2307. goto out_qdio;
  2308. }
  2309. rc = qeth_qdio_activate(card);
  2310. if (rc) {
  2311. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  2312. goto out_qdio;
  2313. }
  2314. rc = qeth_dm_act(card);
  2315. if (rc) {
  2316. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  2317. goto out_qdio;
  2318. }
  2319. return 0;
  2320. out_qdio:
  2321. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  2322. return rc;
  2323. }
  2324. static void qeth_print_status_with_portname(struct qeth_card *card)
  2325. {
  2326. char dbf_text[15];
  2327. int i;
  2328. sprintf(dbf_text, "%s", card->info.portname + 1);
  2329. for (i = 0; i < 8; i++)
  2330. dbf_text[i] =
  2331. (char) _ebcasc[(__u8) dbf_text[i]];
  2332. dbf_text[8] = 0;
  2333. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  2334. "with link type %s (portname: %s)\n",
  2335. qeth_get_cardname(card),
  2336. (card->info.mcl_level[0]) ? " (level: " : "",
  2337. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2338. (card->info.mcl_level[0]) ? ")" : "",
  2339. qeth_get_cardname_short(card),
  2340. dbf_text);
  2341. }
  2342. static void qeth_print_status_no_portname(struct qeth_card *card)
  2343. {
  2344. if (card->info.portname[0])
  2345. dev_info(&card->gdev->dev, "Device is a%s "
  2346. "card%s%s%s\nwith link type %s "
  2347. "(no portname needed by interface).\n",
  2348. qeth_get_cardname(card),
  2349. (card->info.mcl_level[0]) ? " (level: " : "",
  2350. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2351. (card->info.mcl_level[0]) ? ")" : "",
  2352. qeth_get_cardname_short(card));
  2353. else
  2354. dev_info(&card->gdev->dev, "Device is a%s "
  2355. "card%s%s%s\nwith link type %s.\n",
  2356. qeth_get_cardname(card),
  2357. (card->info.mcl_level[0]) ? " (level: " : "",
  2358. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2359. (card->info.mcl_level[0]) ? ")" : "",
  2360. qeth_get_cardname_short(card));
  2361. }
  2362. void qeth_print_status_message(struct qeth_card *card)
  2363. {
  2364. switch (card->info.type) {
  2365. case QETH_CARD_TYPE_OSD:
  2366. case QETH_CARD_TYPE_OSM:
  2367. case QETH_CARD_TYPE_OSX:
  2368. /* VM will use a non-zero first character
  2369. * to indicate a HiperSockets like reporting
  2370. * of the level OSA sets the first character to zero
  2371. * */
  2372. if (!card->info.mcl_level[0]) {
  2373. sprintf(card->info.mcl_level, "%02x%02x",
  2374. card->info.mcl_level[2],
  2375. card->info.mcl_level[3]);
  2376. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2377. break;
  2378. }
  2379. /* fallthrough */
  2380. case QETH_CARD_TYPE_IQD:
  2381. if ((card->info.guestlan) ||
  2382. (card->info.mcl_level[0] & 0x80)) {
  2383. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2384. card->info.mcl_level[0]];
  2385. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2386. card->info.mcl_level[1]];
  2387. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2388. card->info.mcl_level[2]];
  2389. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2390. card->info.mcl_level[3]];
  2391. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2392. }
  2393. break;
  2394. default:
  2395. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2396. }
  2397. if (card->info.portname_required)
  2398. qeth_print_status_with_portname(card);
  2399. else
  2400. qeth_print_status_no_portname(card);
  2401. }
  2402. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2403. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2404. {
  2405. struct qeth_buffer_pool_entry *entry;
  2406. QETH_CARD_TEXT(card, 5, "inwrklst");
  2407. list_for_each_entry(entry,
  2408. &card->qdio.init_pool.entry_list, init_list) {
  2409. qeth_put_buffer_pool_entry(card, entry);
  2410. }
  2411. }
  2412. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2413. struct qeth_card *card)
  2414. {
  2415. struct list_head *plh;
  2416. struct qeth_buffer_pool_entry *entry;
  2417. int i, free;
  2418. struct page *page;
  2419. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2420. return NULL;
  2421. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2422. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2423. free = 1;
  2424. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2425. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2426. free = 0;
  2427. break;
  2428. }
  2429. }
  2430. if (free) {
  2431. list_del_init(&entry->list);
  2432. return entry;
  2433. }
  2434. }
  2435. /* no free buffer in pool so take first one and swap pages */
  2436. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2437. struct qeth_buffer_pool_entry, list);
  2438. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2439. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2440. page = alloc_page(GFP_ATOMIC);
  2441. if (!page) {
  2442. return NULL;
  2443. } else {
  2444. free_page((unsigned long)entry->elements[i]);
  2445. entry->elements[i] = page_address(page);
  2446. if (card->options.performance_stats)
  2447. card->perf_stats.sg_alloc_page_rx++;
  2448. }
  2449. }
  2450. }
  2451. list_del_init(&entry->list);
  2452. return entry;
  2453. }
  2454. static int qeth_init_input_buffer(struct qeth_card *card,
  2455. struct qeth_qdio_buffer *buf)
  2456. {
  2457. struct qeth_buffer_pool_entry *pool_entry;
  2458. int i;
  2459. if ((card->options.cq == QETH_CQ_ENABLED) && (!buf->rx_skb)) {
  2460. buf->rx_skb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  2461. if (!buf->rx_skb)
  2462. return 1;
  2463. }
  2464. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2465. if (!pool_entry)
  2466. return 1;
  2467. /*
  2468. * since the buffer is accessed only from the input_tasklet
  2469. * there shouldn't be a need to synchronize; also, since we use
  2470. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2471. * buffers
  2472. */
  2473. buf->pool_entry = pool_entry;
  2474. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2475. buf->buffer->element[i].length = PAGE_SIZE;
  2476. buf->buffer->element[i].addr = pool_entry->elements[i];
  2477. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2478. buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;
  2479. else
  2480. buf->buffer->element[i].eflags = 0;
  2481. buf->buffer->element[i].sflags = 0;
  2482. }
  2483. return 0;
  2484. }
  2485. int qeth_init_qdio_queues(struct qeth_card *card)
  2486. {
  2487. int i, j;
  2488. int rc;
  2489. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2490. /* inbound queue */
  2491. memset(card->qdio.in_q->qdio_bufs, 0,
  2492. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2493. qeth_initialize_working_pool_list(card);
  2494. /*give only as many buffers to hardware as we have buffer pool entries*/
  2495. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2496. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2497. card->qdio.in_q->next_buf_to_init =
  2498. card->qdio.in_buf_pool.buf_count - 1;
  2499. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2500. card->qdio.in_buf_pool.buf_count - 1);
  2501. if (rc) {
  2502. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2503. return rc;
  2504. }
  2505. /* completion */
  2506. rc = qeth_cq_init(card);
  2507. if (rc) {
  2508. return rc;
  2509. }
  2510. /* outbound queue */
  2511. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2512. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2513. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2514. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2515. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2516. card->qdio.out_qs[i]->bufs[j],
  2517. QETH_QDIO_BUF_EMPTY);
  2518. }
  2519. card->qdio.out_qs[i]->card = card;
  2520. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2521. card->qdio.out_qs[i]->do_pack = 0;
  2522. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2523. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2524. atomic_set(&card->qdio.out_qs[i]->state,
  2525. QETH_OUT_Q_UNLOCKED);
  2526. }
  2527. return 0;
  2528. }
  2529. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2530. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2531. {
  2532. switch (link_type) {
  2533. case QETH_LINK_TYPE_HSTR:
  2534. return 2;
  2535. default:
  2536. return 1;
  2537. }
  2538. }
  2539. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2540. struct qeth_ipa_cmd *cmd, __u8 command,
  2541. enum qeth_prot_versions prot)
  2542. {
  2543. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2544. cmd->hdr.command = command;
  2545. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2546. cmd->hdr.seqno = card->seqno.ipa;
  2547. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2548. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2549. if (card->options.layer2)
  2550. cmd->hdr.prim_version_no = 2;
  2551. else
  2552. cmd->hdr.prim_version_no = 1;
  2553. cmd->hdr.param_count = 1;
  2554. cmd->hdr.prot_version = prot;
  2555. cmd->hdr.ipa_supported = 0;
  2556. cmd->hdr.ipa_enabled = 0;
  2557. }
  2558. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2559. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2560. {
  2561. struct qeth_cmd_buffer *iob;
  2562. struct qeth_ipa_cmd *cmd;
  2563. iob = qeth_wait_for_buffer(&card->write);
  2564. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2565. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2566. return iob;
  2567. }
  2568. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2569. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2570. char prot_type)
  2571. {
  2572. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2573. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2574. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2575. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2576. }
  2577. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2578. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2579. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2580. unsigned long),
  2581. void *reply_param)
  2582. {
  2583. int rc;
  2584. char prot_type;
  2585. QETH_CARD_TEXT(card, 4, "sendipa");
  2586. if (card->options.layer2)
  2587. if (card->info.type == QETH_CARD_TYPE_OSN)
  2588. prot_type = QETH_PROT_OSN2;
  2589. else
  2590. prot_type = QETH_PROT_LAYER2;
  2591. else
  2592. prot_type = QETH_PROT_TCPIP;
  2593. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2594. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2595. iob, reply_cb, reply_param);
  2596. if (rc == -ETIME) {
  2597. qeth_clear_ipacmd_list(card);
  2598. qeth_schedule_recovery(card);
  2599. }
  2600. return rc;
  2601. }
  2602. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2603. int qeth_send_startlan(struct qeth_card *card)
  2604. {
  2605. int rc;
  2606. struct qeth_cmd_buffer *iob;
  2607. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2608. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2609. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2610. return rc;
  2611. }
  2612. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2613. static int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2614. struct qeth_reply *reply, unsigned long data)
  2615. {
  2616. struct qeth_ipa_cmd *cmd;
  2617. QETH_CARD_TEXT(card, 4, "defadpcb");
  2618. cmd = (struct qeth_ipa_cmd *) data;
  2619. if (cmd->hdr.return_code == 0)
  2620. cmd->hdr.return_code =
  2621. cmd->data.setadapterparms.hdr.return_code;
  2622. return 0;
  2623. }
  2624. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2625. struct qeth_reply *reply, unsigned long data)
  2626. {
  2627. struct qeth_ipa_cmd *cmd;
  2628. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2629. cmd = (struct qeth_ipa_cmd *) data;
  2630. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2631. card->info.link_type =
  2632. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2633. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2634. }
  2635. card->options.adp.supported_funcs =
  2636. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2637. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2638. }
  2639. static struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2640. __u32 command, __u32 cmdlen)
  2641. {
  2642. struct qeth_cmd_buffer *iob;
  2643. struct qeth_ipa_cmd *cmd;
  2644. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2645. QETH_PROT_IPV4);
  2646. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2647. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2648. cmd->data.setadapterparms.hdr.command_code = command;
  2649. cmd->data.setadapterparms.hdr.used_total = 1;
  2650. cmd->data.setadapterparms.hdr.seq_no = 1;
  2651. return iob;
  2652. }
  2653. int qeth_query_setadapterparms(struct qeth_card *card)
  2654. {
  2655. int rc;
  2656. struct qeth_cmd_buffer *iob;
  2657. QETH_CARD_TEXT(card, 3, "queryadp");
  2658. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2659. sizeof(struct qeth_ipacmd_setadpparms));
  2660. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2661. return rc;
  2662. }
  2663. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2664. static int qeth_query_ipassists_cb(struct qeth_card *card,
  2665. struct qeth_reply *reply, unsigned long data)
  2666. {
  2667. struct qeth_ipa_cmd *cmd;
  2668. QETH_DBF_TEXT(SETUP, 2, "qipasscb");
  2669. cmd = (struct qeth_ipa_cmd *) data;
  2670. switch (cmd->hdr.return_code) {
  2671. case IPA_RC_NOTSUPP:
  2672. case IPA_RC_L2_UNSUPPORTED_CMD:
  2673. QETH_DBF_TEXT(SETUP, 2, "ipaunsup");
  2674. card->options.ipa4.supported_funcs |= IPA_SETADAPTERPARMS;
  2675. card->options.ipa6.supported_funcs |= IPA_SETADAPTERPARMS;
  2676. return -0;
  2677. default:
  2678. if (cmd->hdr.return_code) {
  2679. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Unhandled "
  2680. "rc=%d\n",
  2681. dev_name(&card->gdev->dev),
  2682. cmd->hdr.return_code);
  2683. return 0;
  2684. }
  2685. }
  2686. if (cmd->hdr.prot_version == QETH_PROT_IPV4) {
  2687. card->options.ipa4.supported_funcs = cmd->hdr.ipa_supported;
  2688. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  2689. } else if (cmd->hdr.prot_version == QETH_PROT_IPV6) {
  2690. card->options.ipa6.supported_funcs = cmd->hdr.ipa_supported;
  2691. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  2692. } else
  2693. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Flawed LIC detected"
  2694. "\n", dev_name(&card->gdev->dev));
  2695. return 0;
  2696. }
  2697. int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot)
  2698. {
  2699. int rc;
  2700. struct qeth_cmd_buffer *iob;
  2701. QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
  2702. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
  2703. rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
  2704. return rc;
  2705. }
  2706. EXPORT_SYMBOL_GPL(qeth_query_ipassists);
  2707. static int qeth_query_setdiagass_cb(struct qeth_card *card,
  2708. struct qeth_reply *reply, unsigned long data)
  2709. {
  2710. struct qeth_ipa_cmd *cmd;
  2711. __u16 rc;
  2712. cmd = (struct qeth_ipa_cmd *)data;
  2713. rc = cmd->hdr.return_code;
  2714. if (rc)
  2715. QETH_CARD_TEXT_(card, 2, "diagq:%x", rc);
  2716. else
  2717. card->info.diagass_support = cmd->data.diagass.ext;
  2718. return 0;
  2719. }
  2720. static int qeth_query_setdiagass(struct qeth_card *card)
  2721. {
  2722. struct qeth_cmd_buffer *iob;
  2723. struct qeth_ipa_cmd *cmd;
  2724. QETH_DBF_TEXT(SETUP, 2, "qdiagass");
  2725. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2726. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2727. cmd->data.diagass.subcmd_len = 16;
  2728. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
  2729. return qeth_send_ipa_cmd(card, iob, qeth_query_setdiagass_cb, NULL);
  2730. }
  2731. static void qeth_get_trap_id(struct qeth_card *card, struct qeth_trap_id *tid)
  2732. {
  2733. unsigned long info = get_zeroed_page(GFP_KERNEL);
  2734. struct sysinfo_2_2_2 *info222 = (struct sysinfo_2_2_2 *)info;
  2735. struct sysinfo_3_2_2 *info322 = (struct sysinfo_3_2_2 *)info;
  2736. struct ccw_dev_id ccwid;
  2737. int level;
  2738. tid->chpid = card->info.chpid;
  2739. ccw_device_get_id(CARD_RDEV(card), &ccwid);
  2740. tid->ssid = ccwid.ssid;
  2741. tid->devno = ccwid.devno;
  2742. if (!info)
  2743. return;
  2744. level = stsi(NULL, 0, 0, 0);
  2745. if ((level >= 2) && (stsi(info222, 2, 2, 2) == 0))
  2746. tid->lparnr = info222->lpar_number;
  2747. if ((level >= 3) && (stsi(info322, 3, 2, 2) == 0)) {
  2748. EBCASC(info322->vm[0].name, sizeof(info322->vm[0].name));
  2749. memcpy(tid->vmname, info322->vm[0].name, sizeof(tid->vmname));
  2750. }
  2751. free_page(info);
  2752. return;
  2753. }
  2754. static int qeth_hw_trap_cb(struct qeth_card *card,
  2755. struct qeth_reply *reply, unsigned long data)
  2756. {
  2757. struct qeth_ipa_cmd *cmd;
  2758. __u16 rc;
  2759. cmd = (struct qeth_ipa_cmd *)data;
  2760. rc = cmd->hdr.return_code;
  2761. if (rc)
  2762. QETH_CARD_TEXT_(card, 2, "trapc:%x", rc);
  2763. return 0;
  2764. }
  2765. int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action)
  2766. {
  2767. struct qeth_cmd_buffer *iob;
  2768. struct qeth_ipa_cmd *cmd;
  2769. QETH_DBF_TEXT(SETUP, 2, "diagtrap");
  2770. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2771. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2772. cmd->data.diagass.subcmd_len = 80;
  2773. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
  2774. cmd->data.diagass.type = 1;
  2775. cmd->data.diagass.action = action;
  2776. switch (action) {
  2777. case QETH_DIAGS_TRAP_ARM:
  2778. cmd->data.diagass.options = 0x0003;
  2779. cmd->data.diagass.ext = 0x00010000 +
  2780. sizeof(struct qeth_trap_id);
  2781. qeth_get_trap_id(card,
  2782. (struct qeth_trap_id *)cmd->data.diagass.cdata);
  2783. break;
  2784. case QETH_DIAGS_TRAP_DISARM:
  2785. cmd->data.diagass.options = 0x0001;
  2786. break;
  2787. case QETH_DIAGS_TRAP_CAPTURE:
  2788. break;
  2789. }
  2790. return qeth_send_ipa_cmd(card, iob, qeth_hw_trap_cb, NULL);
  2791. }
  2792. EXPORT_SYMBOL_GPL(qeth_hw_trap);
  2793. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2794. unsigned int qdio_error, const char *dbftext)
  2795. {
  2796. if (qdio_error) {
  2797. QETH_CARD_TEXT(card, 2, dbftext);
  2798. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2799. buf->element[15].sflags);
  2800. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2801. buf->element[14].sflags);
  2802. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2803. if ((buf->element[15].sflags) == 0x12) {
  2804. card->stats.rx_dropped++;
  2805. return 0;
  2806. } else
  2807. return 1;
  2808. }
  2809. return 0;
  2810. }
  2811. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2812. void qeth_buffer_reclaim_work(struct work_struct *work)
  2813. {
  2814. struct qeth_card *card = container_of(work, struct qeth_card,
  2815. buffer_reclaim_work.work);
  2816. QETH_CARD_TEXT_(card, 2, "brw:%x", card->reclaim_index);
  2817. qeth_queue_input_buffer(card, card->reclaim_index);
  2818. }
  2819. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2820. {
  2821. struct qeth_qdio_q *queue = card->qdio.in_q;
  2822. struct list_head *lh;
  2823. int count;
  2824. int i;
  2825. int rc;
  2826. int newcount = 0;
  2827. count = (index < queue->next_buf_to_init)?
  2828. card->qdio.in_buf_pool.buf_count -
  2829. (queue->next_buf_to_init - index) :
  2830. card->qdio.in_buf_pool.buf_count -
  2831. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2832. /* only requeue at a certain threshold to avoid SIGAs */
  2833. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2834. for (i = queue->next_buf_to_init;
  2835. i < queue->next_buf_to_init + count; ++i) {
  2836. if (qeth_init_input_buffer(card,
  2837. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2838. break;
  2839. } else {
  2840. newcount++;
  2841. }
  2842. }
  2843. if (newcount < count) {
  2844. /* we are in memory shortage so we switch back to
  2845. traditional skb allocation and drop packages */
  2846. atomic_set(&card->force_alloc_skb, 3);
  2847. count = newcount;
  2848. } else {
  2849. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2850. }
  2851. if (!count) {
  2852. i = 0;
  2853. list_for_each(lh, &card->qdio.in_buf_pool.entry_list)
  2854. i++;
  2855. if (i == card->qdio.in_buf_pool.buf_count) {
  2856. QETH_CARD_TEXT(card, 2, "qsarbw");
  2857. card->reclaim_index = index;
  2858. schedule_delayed_work(
  2859. &card->buffer_reclaim_work,
  2860. QETH_RECLAIM_WORK_TIME);
  2861. }
  2862. return;
  2863. }
  2864. /*
  2865. * according to old code it should be avoided to requeue all
  2866. * 128 buffers in order to benefit from PCI avoidance.
  2867. * this function keeps at least one buffer (the buffer at
  2868. * 'index') un-requeued -> this buffer is the first buffer that
  2869. * will be requeued the next time
  2870. */
  2871. if (card->options.performance_stats) {
  2872. card->perf_stats.inbound_do_qdio_cnt++;
  2873. card->perf_stats.inbound_do_qdio_start_time =
  2874. qeth_get_micros();
  2875. }
  2876. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2877. queue->next_buf_to_init, count);
  2878. if (card->options.performance_stats)
  2879. card->perf_stats.inbound_do_qdio_time +=
  2880. qeth_get_micros() -
  2881. card->perf_stats.inbound_do_qdio_start_time;
  2882. if (rc) {
  2883. QETH_CARD_TEXT(card, 2, "qinberr");
  2884. }
  2885. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2886. QDIO_MAX_BUFFERS_PER_Q;
  2887. }
  2888. }
  2889. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2890. static int qeth_handle_send_error(struct qeth_card *card,
  2891. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2892. {
  2893. int sbalf15 = buffer->buffer->element[15].sflags;
  2894. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2895. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2896. if (sbalf15 == 0) {
  2897. qdio_err = 0;
  2898. } else {
  2899. qdio_err = 1;
  2900. }
  2901. }
  2902. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2903. if (!qdio_err)
  2904. return QETH_SEND_ERROR_NONE;
  2905. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2906. return QETH_SEND_ERROR_RETRY;
  2907. QETH_CARD_TEXT(card, 1, "lnkfail");
  2908. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2909. (u16)qdio_err, (u8)sbalf15);
  2910. return QETH_SEND_ERROR_LINK_FAILURE;
  2911. }
  2912. /*
  2913. * Switched to packing state if the number of used buffers on a queue
  2914. * reaches a certain limit.
  2915. */
  2916. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2917. {
  2918. if (!queue->do_pack) {
  2919. if (atomic_read(&queue->used_buffers)
  2920. >= QETH_HIGH_WATERMARK_PACK){
  2921. /* switch non-PACKING -> PACKING */
  2922. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2923. if (queue->card->options.performance_stats)
  2924. queue->card->perf_stats.sc_dp_p++;
  2925. queue->do_pack = 1;
  2926. }
  2927. }
  2928. }
  2929. /*
  2930. * Switches from packing to non-packing mode. If there is a packing
  2931. * buffer on the queue this buffer will be prepared to be flushed.
  2932. * In that case 1 is returned to inform the caller. If no buffer
  2933. * has to be flushed, zero is returned.
  2934. */
  2935. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2936. {
  2937. struct qeth_qdio_out_buffer *buffer;
  2938. int flush_count = 0;
  2939. if (queue->do_pack) {
  2940. if (atomic_read(&queue->used_buffers)
  2941. <= QETH_LOW_WATERMARK_PACK) {
  2942. /* switch PACKING -> non-PACKING */
  2943. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2944. if (queue->card->options.performance_stats)
  2945. queue->card->perf_stats.sc_p_dp++;
  2946. queue->do_pack = 0;
  2947. /* flush packing buffers */
  2948. buffer = queue->bufs[queue->next_buf_to_fill];
  2949. if ((atomic_read(&buffer->state) ==
  2950. QETH_QDIO_BUF_EMPTY) &&
  2951. (buffer->next_element_to_fill > 0)) {
  2952. atomic_set(&buffer->state,
  2953. QETH_QDIO_BUF_PRIMED);
  2954. flush_count++;
  2955. queue->next_buf_to_fill =
  2956. (queue->next_buf_to_fill + 1) %
  2957. QDIO_MAX_BUFFERS_PER_Q;
  2958. }
  2959. }
  2960. }
  2961. return flush_count;
  2962. }
  2963. /*
  2964. * Called to flush a packing buffer if no more pci flags are on the queue.
  2965. * Checks if there is a packing buffer and prepares it to be flushed.
  2966. * In that case returns 1, otherwise zero.
  2967. */
  2968. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2969. {
  2970. struct qeth_qdio_out_buffer *buffer;
  2971. buffer = queue->bufs[queue->next_buf_to_fill];
  2972. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2973. (buffer->next_element_to_fill > 0)) {
  2974. /* it's a packing buffer */
  2975. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2976. queue->next_buf_to_fill =
  2977. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2978. return 1;
  2979. }
  2980. return 0;
  2981. }
  2982. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2983. int count)
  2984. {
  2985. struct qeth_qdio_out_buffer *buf;
  2986. int rc;
  2987. int i;
  2988. unsigned int qdio_flags;
  2989. for (i = index; i < index + count; ++i) {
  2990. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  2991. buf = queue->bufs[bidx];
  2992. buf->buffer->element[buf->next_element_to_fill - 1].eflags |=
  2993. SBAL_EFLAGS_LAST_ENTRY;
  2994. if (queue->bufstates)
  2995. queue->bufstates[bidx].user = buf;
  2996. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2997. continue;
  2998. if (!queue->do_pack) {
  2999. if ((atomic_read(&queue->used_buffers) >=
  3000. (QETH_HIGH_WATERMARK_PACK -
  3001. QETH_WATERMARK_PACK_FUZZ)) &&
  3002. !atomic_read(&queue->set_pci_flags_count)) {
  3003. /* it's likely that we'll go to packing
  3004. * mode soon */
  3005. atomic_inc(&queue->set_pci_flags_count);
  3006. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  3007. }
  3008. } else {
  3009. if (!atomic_read(&queue->set_pci_flags_count)) {
  3010. /*
  3011. * there's no outstanding PCI any more, so we
  3012. * have to request a PCI to be sure the the PCI
  3013. * will wake at some time in the future then we
  3014. * can flush packed buffers that might still be
  3015. * hanging around, which can happen if no
  3016. * further send was requested by the stack
  3017. */
  3018. atomic_inc(&queue->set_pci_flags_count);
  3019. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  3020. }
  3021. }
  3022. }
  3023. queue->card->dev->trans_start = jiffies;
  3024. if (queue->card->options.performance_stats) {
  3025. queue->card->perf_stats.outbound_do_qdio_cnt++;
  3026. queue->card->perf_stats.outbound_do_qdio_start_time =
  3027. qeth_get_micros();
  3028. }
  3029. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  3030. if (atomic_read(&queue->set_pci_flags_count))
  3031. qdio_flags |= QDIO_FLAG_PCI_OUT;
  3032. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  3033. queue->queue_no, index, count);
  3034. if (queue->card->options.performance_stats)
  3035. queue->card->perf_stats.outbound_do_qdio_time +=
  3036. qeth_get_micros() -
  3037. queue->card->perf_stats.outbound_do_qdio_start_time;
  3038. atomic_add(count, &queue->used_buffers);
  3039. if (rc) {
  3040. queue->card->stats.tx_errors += count;
  3041. /* ignore temporary SIGA errors without busy condition */
  3042. if (rc == -ENOBUFS)
  3043. return;
  3044. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  3045. QETH_CARD_TEXT_(queue->card, 2, " q%d", queue->queue_no);
  3046. QETH_CARD_TEXT_(queue->card, 2, " idx%d", index);
  3047. QETH_CARD_TEXT_(queue->card, 2, " c%d", count);
  3048. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  3049. /* this must not happen under normal circumstances. if it
  3050. * happens something is really wrong -> recover */
  3051. qeth_schedule_recovery(queue->card);
  3052. return;
  3053. }
  3054. if (queue->card->options.performance_stats)
  3055. queue->card->perf_stats.bufs_sent += count;
  3056. }
  3057. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  3058. {
  3059. int index;
  3060. int flush_cnt = 0;
  3061. int q_was_packing = 0;
  3062. /*
  3063. * check if weed have to switch to non-packing mode or if
  3064. * we have to get a pci flag out on the queue
  3065. */
  3066. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  3067. !atomic_read(&queue->set_pci_flags_count)) {
  3068. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  3069. QETH_OUT_Q_UNLOCKED) {
  3070. /*
  3071. * If we get in here, there was no action in
  3072. * do_send_packet. So, we check if there is a
  3073. * packing buffer to be flushed here.
  3074. */
  3075. netif_stop_queue(queue->card->dev);
  3076. index = queue->next_buf_to_fill;
  3077. q_was_packing = queue->do_pack;
  3078. /* queue->do_pack may change */
  3079. barrier();
  3080. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  3081. if (!flush_cnt &&
  3082. !atomic_read(&queue->set_pci_flags_count))
  3083. flush_cnt +=
  3084. qeth_flush_buffers_on_no_pci(queue);
  3085. if (queue->card->options.performance_stats &&
  3086. q_was_packing)
  3087. queue->card->perf_stats.bufs_sent_pack +=
  3088. flush_cnt;
  3089. if (flush_cnt)
  3090. qeth_flush_buffers(queue, index, flush_cnt);
  3091. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3092. }
  3093. }
  3094. }
  3095. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  3096. unsigned long card_ptr)
  3097. {
  3098. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3099. if (card->dev && (card->dev->flags & IFF_UP))
  3100. napi_schedule(&card->napi);
  3101. }
  3102. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  3103. int qeth_configure_cq(struct qeth_card *card, enum qeth_cq cq)
  3104. {
  3105. int rc;
  3106. if (card->options.cq == QETH_CQ_NOTAVAILABLE) {
  3107. rc = -1;
  3108. goto out;
  3109. } else {
  3110. if (card->options.cq == cq) {
  3111. rc = 0;
  3112. goto out;
  3113. }
  3114. if (card->state != CARD_STATE_DOWN &&
  3115. card->state != CARD_STATE_RECOVER) {
  3116. rc = -1;
  3117. goto out;
  3118. }
  3119. qeth_free_qdio_buffers(card);
  3120. card->options.cq = cq;
  3121. rc = 0;
  3122. }
  3123. out:
  3124. return rc;
  3125. }
  3126. EXPORT_SYMBOL_GPL(qeth_configure_cq);
  3127. static void qeth_qdio_cq_handler(struct qeth_card *card,
  3128. unsigned int qdio_err,
  3129. unsigned int queue, int first_element, int count) {
  3130. struct qeth_qdio_q *cq = card->qdio.c_q;
  3131. int i;
  3132. int rc;
  3133. if (!qeth_is_cq(card, queue))
  3134. goto out;
  3135. QETH_CARD_TEXT_(card, 5, "qcqhe%d", first_element);
  3136. QETH_CARD_TEXT_(card, 5, "qcqhc%d", count);
  3137. QETH_CARD_TEXT_(card, 5, "qcqherr%d", qdio_err);
  3138. if (qdio_err) {
  3139. netif_stop_queue(card->dev);
  3140. qeth_schedule_recovery(card);
  3141. goto out;
  3142. }
  3143. if (card->options.performance_stats) {
  3144. card->perf_stats.cq_cnt++;
  3145. card->perf_stats.cq_start_time = qeth_get_micros();
  3146. }
  3147. for (i = first_element; i < first_element + count; ++i) {
  3148. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3149. struct qdio_buffer *buffer = &cq->qdio_bufs[bidx];
  3150. int e;
  3151. e = 0;
  3152. while (buffer->element[e].addr) {
  3153. unsigned long phys_aob_addr;
  3154. phys_aob_addr = (unsigned long) buffer->element[e].addr;
  3155. qeth_qdio_handle_aob(card, phys_aob_addr);
  3156. buffer->element[e].addr = NULL;
  3157. buffer->element[e].eflags = 0;
  3158. buffer->element[e].sflags = 0;
  3159. buffer->element[e].length = 0;
  3160. ++e;
  3161. }
  3162. buffer->element[15].eflags = 0;
  3163. buffer->element[15].sflags = 0;
  3164. }
  3165. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, queue,
  3166. card->qdio.c_q->next_buf_to_init,
  3167. count);
  3168. if (rc) {
  3169. dev_warn(&card->gdev->dev,
  3170. "QDIO reported an error, rc=%i\n", rc);
  3171. QETH_CARD_TEXT(card, 2, "qcqherr");
  3172. }
  3173. card->qdio.c_q->next_buf_to_init = (card->qdio.c_q->next_buf_to_init
  3174. + count) % QDIO_MAX_BUFFERS_PER_Q;
  3175. netif_wake_queue(card->dev);
  3176. if (card->options.performance_stats) {
  3177. int delta_t = qeth_get_micros();
  3178. delta_t -= card->perf_stats.cq_start_time;
  3179. card->perf_stats.cq_time += delta_t;
  3180. }
  3181. out:
  3182. return;
  3183. }
  3184. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  3185. unsigned int queue, int first_elem, int count,
  3186. unsigned long card_ptr)
  3187. {
  3188. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3189. QETH_CARD_TEXT_(card, 2, "qihq%d", queue);
  3190. QETH_CARD_TEXT_(card, 2, "qiec%d", qdio_err);
  3191. if (qeth_is_cq(card, queue))
  3192. qeth_qdio_cq_handler(card, qdio_err, queue, first_elem, count);
  3193. else if (qdio_err)
  3194. qeth_schedule_recovery(card);
  3195. }
  3196. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  3197. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  3198. unsigned int qdio_error, int __queue, int first_element,
  3199. int count, unsigned long card_ptr)
  3200. {
  3201. struct qeth_card *card = (struct qeth_card *) card_ptr;
  3202. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  3203. struct qeth_qdio_out_buffer *buffer;
  3204. int i;
  3205. QETH_CARD_TEXT(card, 6, "qdouhdl");
  3206. if (qdio_error & QDIO_ERROR_FATAL) {
  3207. QETH_CARD_TEXT(card, 2, "achkcond");
  3208. netif_stop_queue(card->dev);
  3209. qeth_schedule_recovery(card);
  3210. return;
  3211. }
  3212. if (card->options.performance_stats) {
  3213. card->perf_stats.outbound_handler_cnt++;
  3214. card->perf_stats.outbound_handler_start_time =
  3215. qeth_get_micros();
  3216. }
  3217. for (i = first_element; i < (first_element + count); ++i) {
  3218. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3219. buffer = queue->bufs[bidx];
  3220. qeth_handle_send_error(card, buffer, qdio_error);
  3221. if (queue->bufstates &&
  3222. (queue->bufstates[bidx].flags &
  3223. QDIO_OUTBUF_STATE_FLAG_PENDING) != 0) {
  3224. WARN_ON_ONCE(card->options.cq != QETH_CQ_ENABLED);
  3225. if (atomic_cmpxchg(&buffer->state,
  3226. QETH_QDIO_BUF_PRIMED,
  3227. QETH_QDIO_BUF_PENDING) ==
  3228. QETH_QDIO_BUF_PRIMED) {
  3229. qeth_notify_skbs(queue, buffer,
  3230. TX_NOTIFY_PENDING);
  3231. }
  3232. buffer->aob = queue->bufstates[bidx].aob;
  3233. QETH_CARD_TEXT_(queue->card, 5, "pel%d", bidx);
  3234. QETH_CARD_TEXT(queue->card, 5, "aob");
  3235. QETH_CARD_TEXT_(queue->card, 5, "%lx",
  3236. virt_to_phys(buffer->aob));
  3237. if (qeth_init_qdio_out_buf(queue, bidx)) {
  3238. QETH_CARD_TEXT(card, 2, "outofbuf");
  3239. qeth_schedule_recovery(card);
  3240. }
  3241. } else {
  3242. if (card->options.cq == QETH_CQ_ENABLED) {
  3243. enum iucv_tx_notify n;
  3244. n = qeth_compute_cq_notification(
  3245. buffer->buffer->element[15].sflags, 0);
  3246. qeth_notify_skbs(queue, buffer, n);
  3247. }
  3248. qeth_clear_output_buffer(queue, buffer,
  3249. QETH_QDIO_BUF_EMPTY);
  3250. }
  3251. qeth_cleanup_handled_pending(queue, bidx, 0);
  3252. }
  3253. atomic_sub(count, &queue->used_buffers);
  3254. /* check if we need to do something on this outbound queue */
  3255. if (card->info.type != QETH_CARD_TYPE_IQD)
  3256. qeth_check_outbound_queue(queue);
  3257. netif_wake_queue(queue->card->dev);
  3258. if (card->options.performance_stats)
  3259. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  3260. card->perf_stats.outbound_handler_start_time;
  3261. }
  3262. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  3263. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  3264. int ipv, int cast_type)
  3265. {
  3266. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  3267. card->info.type == QETH_CARD_TYPE_OSX))
  3268. return card->qdio.default_out_queue;
  3269. switch (card->qdio.no_out_queues) {
  3270. case 4:
  3271. if (cast_type && card->info.is_multicast_different)
  3272. return card->info.is_multicast_different &
  3273. (card->qdio.no_out_queues - 1);
  3274. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  3275. const u8 tos = ip_hdr(skb)->tos;
  3276. if (card->qdio.do_prio_queueing ==
  3277. QETH_PRIO_Q_ING_TOS) {
  3278. if (tos & IP_TOS_NOTIMPORTANT)
  3279. return 3;
  3280. if (tos & IP_TOS_HIGHRELIABILITY)
  3281. return 2;
  3282. if (tos & IP_TOS_HIGHTHROUGHPUT)
  3283. return 1;
  3284. if (tos & IP_TOS_LOWDELAY)
  3285. return 0;
  3286. }
  3287. if (card->qdio.do_prio_queueing ==
  3288. QETH_PRIO_Q_ING_PREC)
  3289. return 3 - (tos >> 6);
  3290. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  3291. /* TODO: IPv6!!! */
  3292. }
  3293. return card->qdio.default_out_queue;
  3294. case 1: /* fallthrough for single-out-queue 1920-device */
  3295. default:
  3296. return card->qdio.default_out_queue;
  3297. }
  3298. }
  3299. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  3300. int qeth_get_elements_for_frags(struct sk_buff *skb)
  3301. {
  3302. int cnt, length, e, elements = 0;
  3303. struct skb_frag_struct *frag;
  3304. char *data;
  3305. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3306. frag = &skb_shinfo(skb)->frags[cnt];
  3307. data = (char *)page_to_phys(skb_frag_page(frag)) +
  3308. frag->page_offset;
  3309. length = frag->size;
  3310. e = PFN_UP((unsigned long)data + length - 1) -
  3311. PFN_DOWN((unsigned long)data);
  3312. elements += e;
  3313. }
  3314. return elements;
  3315. }
  3316. EXPORT_SYMBOL_GPL(qeth_get_elements_for_frags);
  3317. int qeth_get_elements_no(struct qeth_card *card,
  3318. struct sk_buff *skb, int elems)
  3319. {
  3320. int dlen = skb->len - skb->data_len;
  3321. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  3322. PFN_DOWN((unsigned long)skb->data);
  3323. elements_needed += qeth_get_elements_for_frags(skb);
  3324. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  3325. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  3326. "(Number=%d / Length=%d). Discarded.\n",
  3327. (elements_needed+elems), skb->len);
  3328. return 0;
  3329. }
  3330. return elements_needed;
  3331. }
  3332. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  3333. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, struct qeth_hdr **hdr, int len)
  3334. {
  3335. int hroom, inpage, rest;
  3336. if (((unsigned long)skb->data & PAGE_MASK) !=
  3337. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  3338. hroom = skb_headroom(skb);
  3339. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  3340. rest = len - inpage;
  3341. if (rest > hroom)
  3342. return 1;
  3343. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  3344. skb->data -= rest;
  3345. skb->tail -= rest;
  3346. *hdr = (struct qeth_hdr *)skb->data;
  3347. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  3348. }
  3349. return 0;
  3350. }
  3351. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  3352. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  3353. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  3354. int offset)
  3355. {
  3356. int length = skb->len - skb->data_len;
  3357. int length_here;
  3358. int element;
  3359. char *data;
  3360. int first_lap, cnt;
  3361. struct skb_frag_struct *frag;
  3362. element = *next_element_to_fill;
  3363. data = skb->data;
  3364. first_lap = (is_tso == 0 ? 1 : 0);
  3365. if (offset >= 0) {
  3366. data = skb->data + offset;
  3367. length -= offset;
  3368. first_lap = 0;
  3369. }
  3370. while (length > 0) {
  3371. /* length_here is the remaining amount of data in this page */
  3372. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  3373. if (length < length_here)
  3374. length_here = length;
  3375. buffer->element[element].addr = data;
  3376. buffer->element[element].length = length_here;
  3377. length -= length_here;
  3378. if (!length) {
  3379. if (first_lap)
  3380. if (skb_shinfo(skb)->nr_frags)
  3381. buffer->element[element].eflags =
  3382. SBAL_EFLAGS_FIRST_FRAG;
  3383. else
  3384. buffer->element[element].eflags = 0;
  3385. else
  3386. buffer->element[element].eflags =
  3387. SBAL_EFLAGS_MIDDLE_FRAG;
  3388. } else {
  3389. if (first_lap)
  3390. buffer->element[element].eflags =
  3391. SBAL_EFLAGS_FIRST_FRAG;
  3392. else
  3393. buffer->element[element].eflags =
  3394. SBAL_EFLAGS_MIDDLE_FRAG;
  3395. }
  3396. data += length_here;
  3397. element++;
  3398. first_lap = 0;
  3399. }
  3400. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3401. frag = &skb_shinfo(skb)->frags[cnt];
  3402. data = (char *)page_to_phys(skb_frag_page(frag)) +
  3403. frag->page_offset;
  3404. length = frag->size;
  3405. while (length > 0) {
  3406. length_here = PAGE_SIZE -
  3407. ((unsigned long) data % PAGE_SIZE);
  3408. if (length < length_here)
  3409. length_here = length;
  3410. buffer->element[element].addr = data;
  3411. buffer->element[element].length = length_here;
  3412. buffer->element[element].eflags =
  3413. SBAL_EFLAGS_MIDDLE_FRAG;
  3414. length -= length_here;
  3415. data += length_here;
  3416. element++;
  3417. }
  3418. }
  3419. if (buffer->element[element - 1].eflags)
  3420. buffer->element[element - 1].eflags = SBAL_EFLAGS_LAST_FRAG;
  3421. *next_element_to_fill = element;
  3422. }
  3423. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  3424. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  3425. struct qeth_hdr *hdr, int offset, int hd_len)
  3426. {
  3427. struct qdio_buffer *buffer;
  3428. int flush_cnt = 0, hdr_len, large_send = 0;
  3429. buffer = buf->buffer;
  3430. atomic_inc(&skb->users);
  3431. skb_queue_tail(&buf->skb_list, skb);
  3432. /*check first on TSO ....*/
  3433. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  3434. int element = buf->next_element_to_fill;
  3435. hdr_len = sizeof(struct qeth_hdr_tso) +
  3436. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  3437. /*fill first buffer entry only with header information */
  3438. buffer->element[element].addr = skb->data;
  3439. buffer->element[element].length = hdr_len;
  3440. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3441. buf->next_element_to_fill++;
  3442. skb->data += hdr_len;
  3443. skb->len -= hdr_len;
  3444. large_send = 1;
  3445. }
  3446. if (offset >= 0) {
  3447. int element = buf->next_element_to_fill;
  3448. buffer->element[element].addr = hdr;
  3449. buffer->element[element].length = sizeof(struct qeth_hdr) +
  3450. hd_len;
  3451. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3452. buf->is_header[element] = 1;
  3453. buf->next_element_to_fill++;
  3454. }
  3455. __qeth_fill_buffer(skb, buffer, large_send,
  3456. (int *)&buf->next_element_to_fill, offset);
  3457. if (!queue->do_pack) {
  3458. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  3459. /* set state to PRIMED -> will be flushed */
  3460. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3461. flush_cnt = 1;
  3462. } else {
  3463. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  3464. if (queue->card->options.performance_stats)
  3465. queue->card->perf_stats.skbs_sent_pack++;
  3466. if (buf->next_element_to_fill >=
  3467. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  3468. /*
  3469. * packed buffer if full -> set state PRIMED
  3470. * -> will be flushed
  3471. */
  3472. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3473. flush_cnt = 1;
  3474. }
  3475. }
  3476. return flush_cnt;
  3477. }
  3478. int qeth_do_send_packet_fast(struct qeth_card *card,
  3479. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  3480. struct qeth_hdr *hdr, int elements_needed,
  3481. int offset, int hd_len)
  3482. {
  3483. struct qeth_qdio_out_buffer *buffer;
  3484. int index;
  3485. /* spin until we get the queue ... */
  3486. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3487. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3488. /* ... now we've got the queue */
  3489. index = queue->next_buf_to_fill;
  3490. buffer = queue->bufs[queue->next_buf_to_fill];
  3491. /*
  3492. * check if buffer is empty to make sure that we do not 'overtake'
  3493. * ourselves and try to fill a buffer that is already primed
  3494. */
  3495. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  3496. goto out;
  3497. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  3498. QDIO_MAX_BUFFERS_PER_Q;
  3499. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3500. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  3501. qeth_flush_buffers(queue, index, 1);
  3502. return 0;
  3503. out:
  3504. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3505. return -EBUSY;
  3506. }
  3507. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  3508. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  3509. struct sk_buff *skb, struct qeth_hdr *hdr,
  3510. int elements_needed)
  3511. {
  3512. struct qeth_qdio_out_buffer *buffer;
  3513. int start_index;
  3514. int flush_count = 0;
  3515. int do_pack = 0;
  3516. int tmp;
  3517. int rc = 0;
  3518. /* spin until we get the queue ... */
  3519. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3520. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3521. start_index = queue->next_buf_to_fill;
  3522. buffer = queue->bufs[queue->next_buf_to_fill];
  3523. /*
  3524. * check if buffer is empty to make sure that we do not 'overtake'
  3525. * ourselves and try to fill a buffer that is already primed
  3526. */
  3527. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  3528. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3529. return -EBUSY;
  3530. }
  3531. /* check if we need to switch packing state of this queue */
  3532. qeth_switch_to_packing_if_needed(queue);
  3533. if (queue->do_pack) {
  3534. do_pack = 1;
  3535. /* does packet fit in current buffer? */
  3536. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  3537. buffer->next_element_to_fill) < elements_needed) {
  3538. /* ... no -> set state PRIMED */
  3539. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3540. flush_count++;
  3541. queue->next_buf_to_fill =
  3542. (queue->next_buf_to_fill + 1) %
  3543. QDIO_MAX_BUFFERS_PER_Q;
  3544. buffer = queue->bufs[queue->next_buf_to_fill];
  3545. /* we did a step forward, so check buffer state
  3546. * again */
  3547. if (atomic_read(&buffer->state) !=
  3548. QETH_QDIO_BUF_EMPTY) {
  3549. qeth_flush_buffers(queue, start_index,
  3550. flush_count);
  3551. atomic_set(&queue->state,
  3552. QETH_OUT_Q_UNLOCKED);
  3553. return -EBUSY;
  3554. }
  3555. }
  3556. }
  3557. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  3558. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3559. QDIO_MAX_BUFFERS_PER_Q;
  3560. flush_count += tmp;
  3561. if (flush_count)
  3562. qeth_flush_buffers(queue, start_index, flush_count);
  3563. else if (!atomic_read(&queue->set_pci_flags_count))
  3564. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3565. /*
  3566. * queue->state will go from LOCKED -> UNLOCKED or from
  3567. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3568. * (switch packing state or flush buffer to get another pci flag out).
  3569. * In that case we will enter this loop
  3570. */
  3571. while (atomic_dec_return(&queue->state)) {
  3572. flush_count = 0;
  3573. start_index = queue->next_buf_to_fill;
  3574. /* check if we can go back to non-packing state */
  3575. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3576. /*
  3577. * check if we need to flush a packing buffer to get a pci
  3578. * flag out on the queue
  3579. */
  3580. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3581. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3582. if (flush_count)
  3583. qeth_flush_buffers(queue, start_index, flush_count);
  3584. }
  3585. /* at this point the queue is UNLOCKED again */
  3586. if (queue->card->options.performance_stats && do_pack)
  3587. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3588. return rc;
  3589. }
  3590. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3591. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3592. struct qeth_reply *reply, unsigned long data)
  3593. {
  3594. struct qeth_ipa_cmd *cmd;
  3595. struct qeth_ipacmd_setadpparms *setparms;
  3596. QETH_CARD_TEXT(card, 4, "prmadpcb");
  3597. cmd = (struct qeth_ipa_cmd *) data;
  3598. setparms = &(cmd->data.setadapterparms);
  3599. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3600. if (cmd->hdr.return_code) {
  3601. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3602. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3603. }
  3604. card->info.promisc_mode = setparms->data.mode;
  3605. return 0;
  3606. }
  3607. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3608. {
  3609. enum qeth_ipa_promisc_modes mode;
  3610. struct net_device *dev = card->dev;
  3611. struct qeth_cmd_buffer *iob;
  3612. struct qeth_ipa_cmd *cmd;
  3613. QETH_CARD_TEXT(card, 4, "setprom");
  3614. if (((dev->flags & IFF_PROMISC) &&
  3615. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3616. (!(dev->flags & IFF_PROMISC) &&
  3617. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3618. return;
  3619. mode = SET_PROMISC_MODE_OFF;
  3620. if (dev->flags & IFF_PROMISC)
  3621. mode = SET_PROMISC_MODE_ON;
  3622. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3623. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3624. sizeof(struct qeth_ipacmd_setadpparms));
  3625. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3626. cmd->data.setadapterparms.data.mode = mode;
  3627. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3628. }
  3629. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3630. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3631. {
  3632. struct qeth_card *card;
  3633. char dbf_text[15];
  3634. card = dev->ml_priv;
  3635. QETH_CARD_TEXT(card, 4, "chgmtu");
  3636. sprintf(dbf_text, "%8x", new_mtu);
  3637. QETH_CARD_TEXT(card, 4, dbf_text);
  3638. if (new_mtu < 64)
  3639. return -EINVAL;
  3640. if (new_mtu > 65535)
  3641. return -EINVAL;
  3642. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3643. (!qeth_mtu_is_valid(card, new_mtu)))
  3644. return -EINVAL;
  3645. dev->mtu = new_mtu;
  3646. return 0;
  3647. }
  3648. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3649. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3650. {
  3651. struct qeth_card *card;
  3652. card = dev->ml_priv;
  3653. QETH_CARD_TEXT(card, 5, "getstat");
  3654. return &card->stats;
  3655. }
  3656. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3657. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3658. struct qeth_reply *reply, unsigned long data)
  3659. {
  3660. struct qeth_ipa_cmd *cmd;
  3661. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3662. cmd = (struct qeth_ipa_cmd *) data;
  3663. if (!card->options.layer2 ||
  3664. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3665. memcpy(card->dev->dev_addr,
  3666. &cmd->data.setadapterparms.data.change_addr.addr,
  3667. OSA_ADDR_LEN);
  3668. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3669. }
  3670. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3671. return 0;
  3672. }
  3673. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3674. {
  3675. int rc;
  3676. struct qeth_cmd_buffer *iob;
  3677. struct qeth_ipa_cmd *cmd;
  3678. QETH_CARD_TEXT(card, 4, "chgmac");
  3679. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3680. sizeof(struct qeth_ipacmd_setadpparms));
  3681. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3682. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3683. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3684. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3685. card->dev->dev_addr, OSA_ADDR_LEN);
  3686. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3687. NULL);
  3688. return rc;
  3689. }
  3690. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3691. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3692. struct qeth_reply *reply, unsigned long data)
  3693. {
  3694. struct qeth_ipa_cmd *cmd;
  3695. struct qeth_set_access_ctrl *access_ctrl_req;
  3696. int fallback = *(int *)reply->param;
  3697. QETH_CARD_TEXT(card, 4, "setaccb");
  3698. cmd = (struct qeth_ipa_cmd *) data;
  3699. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3700. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3701. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3702. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3703. cmd->data.setadapterparms.hdr.return_code);
  3704. if (cmd->data.setadapterparms.hdr.return_code !=
  3705. SET_ACCESS_CTRL_RC_SUCCESS)
  3706. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3707. card->gdev->dev.kobj.name,
  3708. access_ctrl_req->subcmd_code,
  3709. cmd->data.setadapterparms.hdr.return_code);
  3710. switch (cmd->data.setadapterparms.hdr.return_code) {
  3711. case SET_ACCESS_CTRL_RC_SUCCESS:
  3712. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3713. dev_info(&card->gdev->dev,
  3714. "QDIO data connection isolation is deactivated\n");
  3715. } else {
  3716. dev_info(&card->gdev->dev,
  3717. "QDIO data connection isolation is activated\n");
  3718. }
  3719. break;
  3720. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3721. QETH_DBF_MESSAGE(2, "%s QDIO data connection isolation already "
  3722. "deactivated\n", dev_name(&card->gdev->dev));
  3723. if (fallback)
  3724. card->options.isolation = card->options.prev_isolation;
  3725. break;
  3726. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3727. QETH_DBF_MESSAGE(2, "%s QDIO data connection isolation already"
  3728. " activated\n", dev_name(&card->gdev->dev));
  3729. if (fallback)
  3730. card->options.isolation = card->options.prev_isolation;
  3731. break;
  3732. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3733. dev_err(&card->gdev->dev, "Adapter does not "
  3734. "support QDIO data connection isolation\n");
  3735. break;
  3736. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3737. dev_err(&card->gdev->dev,
  3738. "Adapter is dedicated. "
  3739. "QDIO data connection isolation not supported\n");
  3740. if (fallback)
  3741. card->options.isolation = card->options.prev_isolation;
  3742. break;
  3743. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3744. dev_err(&card->gdev->dev,
  3745. "TSO does not permit QDIO data connection isolation\n");
  3746. if (fallback)
  3747. card->options.isolation = card->options.prev_isolation;
  3748. break;
  3749. case SET_ACCESS_CTRL_RC_REFLREL_UNSUPPORTED:
  3750. dev_err(&card->gdev->dev, "The adjacent switch port does not "
  3751. "support reflective relay mode\n");
  3752. if (fallback)
  3753. card->options.isolation = card->options.prev_isolation;
  3754. break;
  3755. case SET_ACCESS_CTRL_RC_REFLREL_FAILED:
  3756. dev_err(&card->gdev->dev, "The reflective relay mode cannot be "
  3757. "enabled at the adjacent switch port");
  3758. if (fallback)
  3759. card->options.isolation = card->options.prev_isolation;
  3760. break;
  3761. case SET_ACCESS_CTRL_RC_REFLREL_DEACT_FAILED:
  3762. dev_warn(&card->gdev->dev, "Turning off reflective relay mode "
  3763. "at the adjacent switch failed\n");
  3764. break;
  3765. default:
  3766. /* this should never happen */
  3767. if (fallback)
  3768. card->options.isolation = card->options.prev_isolation;
  3769. break;
  3770. }
  3771. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3772. return 0;
  3773. }
  3774. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3775. enum qeth_ipa_isolation_modes isolation, int fallback)
  3776. {
  3777. int rc;
  3778. struct qeth_cmd_buffer *iob;
  3779. struct qeth_ipa_cmd *cmd;
  3780. struct qeth_set_access_ctrl *access_ctrl_req;
  3781. QETH_CARD_TEXT(card, 4, "setacctl");
  3782. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3783. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3784. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3785. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3786. sizeof(struct qeth_set_access_ctrl));
  3787. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3788. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3789. access_ctrl_req->subcmd_code = isolation;
  3790. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3791. &fallback);
  3792. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3793. return rc;
  3794. }
  3795. int qeth_set_access_ctrl_online(struct qeth_card *card, int fallback)
  3796. {
  3797. int rc = 0;
  3798. QETH_CARD_TEXT(card, 4, "setactlo");
  3799. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3800. card->info.type == QETH_CARD_TYPE_OSX) &&
  3801. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3802. rc = qeth_setadpparms_set_access_ctrl(card,
  3803. card->options.isolation, fallback);
  3804. if (rc) {
  3805. QETH_DBF_MESSAGE(3,
  3806. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3807. card->gdev->dev.kobj.name,
  3808. rc);
  3809. rc = -EOPNOTSUPP;
  3810. }
  3811. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3812. card->options.isolation = ISOLATION_MODE_NONE;
  3813. dev_err(&card->gdev->dev, "Adapter does not "
  3814. "support QDIO data connection isolation\n");
  3815. rc = -EOPNOTSUPP;
  3816. }
  3817. return rc;
  3818. }
  3819. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3820. void qeth_tx_timeout(struct net_device *dev)
  3821. {
  3822. struct qeth_card *card;
  3823. card = dev->ml_priv;
  3824. QETH_CARD_TEXT(card, 4, "txtimeo");
  3825. card->stats.tx_errors++;
  3826. qeth_schedule_recovery(card);
  3827. }
  3828. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3829. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3830. {
  3831. struct qeth_card *card = dev->ml_priv;
  3832. int rc = 0;
  3833. switch (regnum) {
  3834. case MII_BMCR: /* Basic mode control register */
  3835. rc = BMCR_FULLDPLX;
  3836. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3837. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3838. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3839. rc |= BMCR_SPEED100;
  3840. break;
  3841. case MII_BMSR: /* Basic mode status register */
  3842. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3843. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3844. BMSR_100BASE4;
  3845. break;
  3846. case MII_PHYSID1: /* PHYS ID 1 */
  3847. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3848. dev->dev_addr[2];
  3849. rc = (rc >> 5) & 0xFFFF;
  3850. break;
  3851. case MII_PHYSID2: /* PHYS ID 2 */
  3852. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3853. break;
  3854. case MII_ADVERTISE: /* Advertisement control reg */
  3855. rc = ADVERTISE_ALL;
  3856. break;
  3857. case MII_LPA: /* Link partner ability reg */
  3858. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3859. LPA_100BASE4 | LPA_LPACK;
  3860. break;
  3861. case MII_EXPANSION: /* Expansion register */
  3862. break;
  3863. case MII_DCOUNTER: /* disconnect counter */
  3864. break;
  3865. case MII_FCSCOUNTER: /* false carrier counter */
  3866. break;
  3867. case MII_NWAYTEST: /* N-way auto-neg test register */
  3868. break;
  3869. case MII_RERRCOUNTER: /* rx error counter */
  3870. rc = card->stats.rx_errors;
  3871. break;
  3872. case MII_SREVISION: /* silicon revision */
  3873. break;
  3874. case MII_RESV1: /* reserved 1 */
  3875. break;
  3876. case MII_LBRERROR: /* loopback, rx, bypass error */
  3877. break;
  3878. case MII_PHYADDR: /* physical address */
  3879. break;
  3880. case MII_RESV2: /* reserved 2 */
  3881. break;
  3882. case MII_TPISTATUS: /* TPI status for 10mbps */
  3883. break;
  3884. case MII_NCONFIG: /* network interface config */
  3885. break;
  3886. default:
  3887. break;
  3888. }
  3889. return rc;
  3890. }
  3891. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3892. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3893. struct qeth_cmd_buffer *iob, int len,
  3894. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3895. unsigned long),
  3896. void *reply_param)
  3897. {
  3898. u16 s1, s2;
  3899. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3900. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3901. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3902. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3903. /* adjust PDU length fields in IPA_PDU_HEADER */
  3904. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3905. s2 = (u32) len;
  3906. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3907. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3908. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3909. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3910. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3911. reply_cb, reply_param);
  3912. }
  3913. static int qeth_snmp_command_cb(struct qeth_card *card,
  3914. struct qeth_reply *reply, unsigned long sdata)
  3915. {
  3916. struct qeth_ipa_cmd *cmd;
  3917. struct qeth_arp_query_info *qinfo;
  3918. struct qeth_snmp_cmd *snmp;
  3919. unsigned char *data;
  3920. __u16 data_len;
  3921. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3922. cmd = (struct qeth_ipa_cmd *) sdata;
  3923. data = (unsigned char *)((char *)cmd - reply->offset);
  3924. qinfo = (struct qeth_arp_query_info *) reply->param;
  3925. snmp = &cmd->data.setadapterparms.data.snmp;
  3926. if (cmd->hdr.return_code) {
  3927. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3928. return 0;
  3929. }
  3930. if (cmd->data.setadapterparms.hdr.return_code) {
  3931. cmd->hdr.return_code =
  3932. cmd->data.setadapterparms.hdr.return_code;
  3933. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3934. return 0;
  3935. }
  3936. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3937. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3938. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3939. else
  3940. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3941. /* check if there is enough room in userspace */
  3942. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3943. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3944. cmd->hdr.return_code = IPA_RC_ENOMEM;
  3945. return 0;
  3946. }
  3947. QETH_CARD_TEXT_(card, 4, "snore%i",
  3948. cmd->data.setadapterparms.hdr.used_total);
  3949. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3950. cmd->data.setadapterparms.hdr.seq_no);
  3951. /*copy entries to user buffer*/
  3952. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3953. memcpy(qinfo->udata + qinfo->udata_offset,
  3954. (char *)snmp,
  3955. data_len + offsetof(struct qeth_snmp_cmd, data));
  3956. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3957. } else {
  3958. memcpy(qinfo->udata + qinfo->udata_offset,
  3959. (char *)&snmp->request, data_len);
  3960. }
  3961. qinfo->udata_offset += data_len;
  3962. /* check if all replies received ... */
  3963. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3964. cmd->data.setadapterparms.hdr.used_total);
  3965. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3966. cmd->data.setadapterparms.hdr.seq_no);
  3967. if (cmd->data.setadapterparms.hdr.seq_no <
  3968. cmd->data.setadapterparms.hdr.used_total)
  3969. return 1;
  3970. return 0;
  3971. }
  3972. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3973. {
  3974. struct qeth_cmd_buffer *iob;
  3975. struct qeth_ipa_cmd *cmd;
  3976. struct qeth_snmp_ureq *ureq;
  3977. int req_len;
  3978. struct qeth_arp_query_info qinfo = {0, };
  3979. int rc = 0;
  3980. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3981. if (card->info.guestlan)
  3982. return -EOPNOTSUPP;
  3983. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3984. (!card->options.layer2)) {
  3985. return -EOPNOTSUPP;
  3986. }
  3987. /* skip 4 bytes (data_len struct member) to get req_len */
  3988. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3989. return -EFAULT;
  3990. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3991. if (IS_ERR(ureq)) {
  3992. QETH_CARD_TEXT(card, 2, "snmpnome");
  3993. return PTR_ERR(ureq);
  3994. }
  3995. qinfo.udata_len = ureq->hdr.data_len;
  3996. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3997. if (!qinfo.udata) {
  3998. kfree(ureq);
  3999. return -ENOMEM;
  4000. }
  4001. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  4002. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  4003. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  4004. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  4005. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  4006. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  4007. qeth_snmp_command_cb, (void *)&qinfo);
  4008. if (rc)
  4009. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  4010. QETH_CARD_IFNAME(card), rc);
  4011. else {
  4012. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  4013. rc = -EFAULT;
  4014. }
  4015. kfree(ureq);
  4016. kfree(qinfo.udata);
  4017. return rc;
  4018. }
  4019. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  4020. static int qeth_setadpparms_query_oat_cb(struct qeth_card *card,
  4021. struct qeth_reply *reply, unsigned long data)
  4022. {
  4023. struct qeth_ipa_cmd *cmd;
  4024. struct qeth_qoat_priv *priv;
  4025. char *resdata;
  4026. int resdatalen;
  4027. QETH_CARD_TEXT(card, 3, "qoatcb");
  4028. cmd = (struct qeth_ipa_cmd *)data;
  4029. priv = (struct qeth_qoat_priv *)reply->param;
  4030. resdatalen = cmd->data.setadapterparms.hdr.cmdlength;
  4031. resdata = (char *)data + 28;
  4032. if (resdatalen > (priv->buffer_len - priv->response_len)) {
  4033. cmd->hdr.return_code = IPA_RC_FFFF;
  4034. return 0;
  4035. }
  4036. memcpy((priv->buffer + priv->response_len), resdata,
  4037. resdatalen);
  4038. priv->response_len += resdatalen;
  4039. if (cmd->data.setadapterparms.hdr.seq_no <
  4040. cmd->data.setadapterparms.hdr.used_total)
  4041. return 1;
  4042. return 0;
  4043. }
  4044. int qeth_query_oat_command(struct qeth_card *card, char __user *udata)
  4045. {
  4046. int rc = 0;
  4047. struct qeth_cmd_buffer *iob;
  4048. struct qeth_ipa_cmd *cmd;
  4049. struct qeth_query_oat *oat_req;
  4050. struct qeth_query_oat_data oat_data;
  4051. struct qeth_qoat_priv priv;
  4052. void __user *tmp;
  4053. QETH_CARD_TEXT(card, 3, "qoatcmd");
  4054. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_OAT)) {
  4055. rc = -EOPNOTSUPP;
  4056. goto out;
  4057. }
  4058. if (copy_from_user(&oat_data, udata,
  4059. sizeof(struct qeth_query_oat_data))) {
  4060. rc = -EFAULT;
  4061. goto out;
  4062. }
  4063. priv.buffer_len = oat_data.buffer_len;
  4064. priv.response_len = 0;
  4065. priv.buffer = kzalloc(oat_data.buffer_len, GFP_KERNEL);
  4066. if (!priv.buffer) {
  4067. rc = -ENOMEM;
  4068. goto out;
  4069. }
  4070. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_OAT,
  4071. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  4072. sizeof(struct qeth_query_oat));
  4073. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  4074. oat_req = &cmd->data.setadapterparms.data.query_oat;
  4075. oat_req->subcmd_code = oat_data.command;
  4076. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_query_oat_cb,
  4077. &priv);
  4078. if (!rc) {
  4079. if (is_compat_task())
  4080. tmp = compat_ptr(oat_data.ptr);
  4081. else
  4082. tmp = (void __user *)(unsigned long)oat_data.ptr;
  4083. if (copy_to_user(tmp, priv.buffer,
  4084. priv.response_len)) {
  4085. rc = -EFAULT;
  4086. goto out_free;
  4087. }
  4088. oat_data.response_len = priv.response_len;
  4089. if (copy_to_user(udata, &oat_data,
  4090. sizeof(struct qeth_query_oat_data)))
  4091. rc = -EFAULT;
  4092. } else
  4093. if (rc == IPA_RC_FFFF)
  4094. rc = -EFAULT;
  4095. out_free:
  4096. kfree(priv.buffer);
  4097. out:
  4098. return rc;
  4099. }
  4100. EXPORT_SYMBOL_GPL(qeth_query_oat_command);
  4101. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  4102. {
  4103. switch (card->info.type) {
  4104. case QETH_CARD_TYPE_IQD:
  4105. return 2;
  4106. default:
  4107. return 0;
  4108. }
  4109. }
  4110. static void qeth_determine_capabilities(struct qeth_card *card)
  4111. {
  4112. int rc;
  4113. int length;
  4114. char *prcd;
  4115. struct ccw_device *ddev;
  4116. int ddev_offline = 0;
  4117. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  4118. ddev = CARD_DDEV(card);
  4119. if (!ddev->online) {
  4120. ddev_offline = 1;
  4121. rc = ccw_device_set_online(ddev);
  4122. if (rc) {
  4123. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4124. goto out;
  4125. }
  4126. }
  4127. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  4128. if (rc) {
  4129. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  4130. dev_name(&card->gdev->dev), rc);
  4131. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4132. goto out_offline;
  4133. }
  4134. qeth_configure_unitaddr(card, prcd);
  4135. if (ddev_offline)
  4136. qeth_configure_blkt_default(card, prcd);
  4137. kfree(prcd);
  4138. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  4139. if (rc)
  4140. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  4141. QETH_DBF_TEXT_(SETUP, 2, "qfmt%d", card->ssqd.qfmt);
  4142. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac1);
  4143. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac3);
  4144. QETH_DBF_TEXT_(SETUP, 2, "icnt%d", card->ssqd.icnt);
  4145. if (!((card->ssqd.qfmt != QDIO_IQDIO_QFMT) ||
  4146. ((card->ssqd.qdioac1 & CHSC_AC1_INITIATE_INPUTQ) == 0) ||
  4147. ((card->ssqd.qdioac3 & CHSC_AC3_FORMAT2_CQ_AVAILABLE) == 0))) {
  4148. dev_info(&card->gdev->dev,
  4149. "Completion Queueing supported\n");
  4150. } else {
  4151. card->options.cq = QETH_CQ_NOTAVAILABLE;
  4152. }
  4153. out_offline:
  4154. if (ddev_offline == 1)
  4155. ccw_device_set_offline(ddev);
  4156. out:
  4157. return;
  4158. }
  4159. static inline void qeth_qdio_establish_cq(struct qeth_card *card,
  4160. struct qdio_buffer **in_sbal_ptrs,
  4161. void (**queue_start_poll) (struct ccw_device *, int, unsigned long)) {
  4162. int i;
  4163. if (card->options.cq == QETH_CQ_ENABLED) {
  4164. int offset = QDIO_MAX_BUFFERS_PER_Q *
  4165. (card->qdio.no_in_queues - 1);
  4166. i = QDIO_MAX_BUFFERS_PER_Q * (card->qdio.no_in_queues - 1);
  4167. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4168. in_sbal_ptrs[offset + i] = (struct qdio_buffer *)
  4169. virt_to_phys(card->qdio.c_q->bufs[i].buffer);
  4170. }
  4171. queue_start_poll[card->qdio.no_in_queues - 1] = NULL;
  4172. }
  4173. }
  4174. static int qeth_qdio_establish(struct qeth_card *card)
  4175. {
  4176. struct qdio_initialize init_data;
  4177. char *qib_param_field;
  4178. struct qdio_buffer **in_sbal_ptrs;
  4179. void (**queue_start_poll) (struct ccw_device *, int, unsigned long);
  4180. struct qdio_buffer **out_sbal_ptrs;
  4181. int i, j, k;
  4182. int rc = 0;
  4183. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  4184. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  4185. GFP_KERNEL);
  4186. if (!qib_param_field) {
  4187. rc = -ENOMEM;
  4188. goto out_free_nothing;
  4189. }
  4190. qeth_create_qib_param_field(card, qib_param_field);
  4191. qeth_create_qib_param_field_blkt(card, qib_param_field);
  4192. in_sbal_ptrs = kzalloc(card->qdio.no_in_queues *
  4193. QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  4194. GFP_KERNEL);
  4195. if (!in_sbal_ptrs) {
  4196. rc = -ENOMEM;
  4197. goto out_free_qib_param;
  4198. }
  4199. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4200. in_sbal_ptrs[i] = (struct qdio_buffer *)
  4201. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  4202. }
  4203. queue_start_poll = kzalloc(sizeof(void *) * card->qdio.no_in_queues,
  4204. GFP_KERNEL);
  4205. if (!queue_start_poll) {
  4206. rc = -ENOMEM;
  4207. goto out_free_in_sbals;
  4208. }
  4209. for (i = 0; i < card->qdio.no_in_queues; ++i)
  4210. queue_start_poll[i] = card->discipline->start_poll;
  4211. qeth_qdio_establish_cq(card, in_sbal_ptrs, queue_start_poll);
  4212. out_sbal_ptrs =
  4213. kzalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  4214. sizeof(void *), GFP_KERNEL);
  4215. if (!out_sbal_ptrs) {
  4216. rc = -ENOMEM;
  4217. goto out_free_queue_start_poll;
  4218. }
  4219. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  4220. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  4221. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  4222. card->qdio.out_qs[i]->bufs[j]->buffer);
  4223. }
  4224. memset(&init_data, 0, sizeof(struct qdio_initialize));
  4225. init_data.cdev = CARD_DDEV(card);
  4226. init_data.q_format = qeth_get_qdio_q_format(card);
  4227. init_data.qib_param_field_format = 0;
  4228. init_data.qib_param_field = qib_param_field;
  4229. init_data.no_input_qs = card->qdio.no_in_queues;
  4230. init_data.no_output_qs = card->qdio.no_out_queues;
  4231. init_data.input_handler = card->discipline->input_handler;
  4232. init_data.output_handler = card->discipline->output_handler;
  4233. init_data.queue_start_poll_array = queue_start_poll;
  4234. init_data.int_parm = (unsigned long) card;
  4235. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  4236. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  4237. init_data.output_sbal_state_array = card->qdio.out_bufstates;
  4238. init_data.scan_threshold =
  4239. (card->info.type == QETH_CARD_TYPE_IQD) ? 1 : 32;
  4240. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  4241. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  4242. rc = qdio_allocate(&init_data);
  4243. if (rc) {
  4244. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4245. goto out;
  4246. }
  4247. rc = qdio_establish(&init_data);
  4248. if (rc) {
  4249. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4250. qdio_free(CARD_DDEV(card));
  4251. }
  4252. }
  4253. switch (card->options.cq) {
  4254. case QETH_CQ_ENABLED:
  4255. dev_info(&card->gdev->dev, "Completion Queue support enabled");
  4256. break;
  4257. case QETH_CQ_DISABLED:
  4258. dev_info(&card->gdev->dev, "Completion Queue support disabled");
  4259. break;
  4260. default:
  4261. break;
  4262. }
  4263. out:
  4264. kfree(out_sbal_ptrs);
  4265. out_free_queue_start_poll:
  4266. kfree(queue_start_poll);
  4267. out_free_in_sbals:
  4268. kfree(in_sbal_ptrs);
  4269. out_free_qib_param:
  4270. kfree(qib_param_field);
  4271. out_free_nothing:
  4272. return rc;
  4273. }
  4274. static void qeth_core_free_card(struct qeth_card *card)
  4275. {
  4276. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  4277. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  4278. qeth_clean_channel(&card->read);
  4279. qeth_clean_channel(&card->write);
  4280. if (card->dev)
  4281. free_netdev(card->dev);
  4282. kfree(card->ip_tbd_list);
  4283. qeth_free_qdio_buffers(card);
  4284. unregister_service_level(&card->qeth_service_level);
  4285. kfree(card);
  4286. }
  4287. void qeth_trace_features(struct qeth_card *card)
  4288. {
  4289. QETH_CARD_TEXT(card, 2, "features");
  4290. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa4.supported_funcs);
  4291. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa4.enabled_funcs);
  4292. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa6.supported_funcs);
  4293. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa6.enabled_funcs);
  4294. QETH_CARD_TEXT_(card, 2, "%x", card->options.adp.supported_funcs);
  4295. QETH_CARD_TEXT_(card, 2, "%x", card->options.adp.enabled_funcs);
  4296. QETH_CARD_TEXT_(card, 2, "%x", card->info.diagass_support);
  4297. }
  4298. EXPORT_SYMBOL_GPL(qeth_trace_features);
  4299. static struct ccw_device_id qeth_ids[] = {
  4300. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  4301. .driver_info = QETH_CARD_TYPE_OSD},
  4302. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  4303. .driver_info = QETH_CARD_TYPE_IQD},
  4304. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  4305. .driver_info = QETH_CARD_TYPE_OSN},
  4306. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  4307. .driver_info = QETH_CARD_TYPE_OSM},
  4308. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  4309. .driver_info = QETH_CARD_TYPE_OSX},
  4310. {},
  4311. };
  4312. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  4313. static struct ccw_driver qeth_ccw_driver = {
  4314. .driver = {
  4315. .owner = THIS_MODULE,
  4316. .name = "qeth",
  4317. },
  4318. .ids = qeth_ids,
  4319. .probe = ccwgroup_probe_ccwdev,
  4320. .remove = ccwgroup_remove_ccwdev,
  4321. };
  4322. int qeth_core_hardsetup_card(struct qeth_card *card)
  4323. {
  4324. int retries = 3;
  4325. int rc;
  4326. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  4327. atomic_set(&card->force_alloc_skb, 0);
  4328. qeth_update_from_chp_desc(card);
  4329. retry:
  4330. if (retries < 3)
  4331. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  4332. dev_name(&card->gdev->dev));
  4333. ccw_device_set_offline(CARD_DDEV(card));
  4334. ccw_device_set_offline(CARD_WDEV(card));
  4335. ccw_device_set_offline(CARD_RDEV(card));
  4336. rc = ccw_device_set_online(CARD_RDEV(card));
  4337. if (rc)
  4338. goto retriable;
  4339. rc = ccw_device_set_online(CARD_WDEV(card));
  4340. if (rc)
  4341. goto retriable;
  4342. rc = ccw_device_set_online(CARD_DDEV(card));
  4343. if (rc)
  4344. goto retriable;
  4345. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  4346. retriable:
  4347. if (rc == -ERESTARTSYS) {
  4348. QETH_DBF_TEXT(SETUP, 2, "break1");
  4349. return rc;
  4350. } else if (rc) {
  4351. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  4352. if (--retries < 0)
  4353. goto out;
  4354. else
  4355. goto retry;
  4356. }
  4357. qeth_determine_capabilities(card);
  4358. qeth_init_tokens(card);
  4359. qeth_init_func_level(card);
  4360. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  4361. if (rc == -ERESTARTSYS) {
  4362. QETH_DBF_TEXT(SETUP, 2, "break2");
  4363. return rc;
  4364. } else if (rc) {
  4365. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4366. if (--retries < 0)
  4367. goto out;
  4368. else
  4369. goto retry;
  4370. }
  4371. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  4372. if (rc == -ERESTARTSYS) {
  4373. QETH_DBF_TEXT(SETUP, 2, "break3");
  4374. return rc;
  4375. } else if (rc) {
  4376. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  4377. if (--retries < 0)
  4378. goto out;
  4379. else
  4380. goto retry;
  4381. }
  4382. card->read_or_write_problem = 0;
  4383. rc = qeth_mpc_initialize(card);
  4384. if (rc) {
  4385. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4386. goto out;
  4387. }
  4388. card->options.ipa4.supported_funcs = 0;
  4389. card->options.adp.supported_funcs = 0;
  4390. card->info.diagass_support = 0;
  4391. qeth_query_ipassists(card, QETH_PROT_IPV4);
  4392. if (qeth_is_supported(card, IPA_SETADAPTERPARMS))
  4393. qeth_query_setadapterparms(card);
  4394. if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST))
  4395. qeth_query_setdiagass(card);
  4396. return 0;
  4397. out:
  4398. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  4399. "an error on the device\n");
  4400. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  4401. dev_name(&card->gdev->dev), rc);
  4402. return rc;
  4403. }
  4404. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  4405. static inline int qeth_create_skb_frag(struct qeth_qdio_buffer *qethbuffer,
  4406. struct qdio_buffer_element *element,
  4407. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  4408. {
  4409. struct page *page = virt_to_page(element->addr);
  4410. if (*pskb == NULL) {
  4411. if (qethbuffer->rx_skb) {
  4412. /* only if qeth_card.options.cq == QETH_CQ_ENABLED */
  4413. *pskb = qethbuffer->rx_skb;
  4414. qethbuffer->rx_skb = NULL;
  4415. } else {
  4416. *pskb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  4417. if (!(*pskb))
  4418. return -ENOMEM;
  4419. }
  4420. skb_reserve(*pskb, ETH_HLEN);
  4421. if (data_len <= QETH_RX_PULL_LEN) {
  4422. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  4423. data_len);
  4424. } else {
  4425. get_page(page);
  4426. memcpy(skb_put(*pskb, QETH_RX_PULL_LEN),
  4427. element->addr + offset, QETH_RX_PULL_LEN);
  4428. skb_fill_page_desc(*pskb, *pfrag, page,
  4429. offset + QETH_RX_PULL_LEN,
  4430. data_len - QETH_RX_PULL_LEN);
  4431. (*pskb)->data_len += data_len - QETH_RX_PULL_LEN;
  4432. (*pskb)->len += data_len - QETH_RX_PULL_LEN;
  4433. (*pskb)->truesize += data_len - QETH_RX_PULL_LEN;
  4434. (*pfrag)++;
  4435. }
  4436. } else {
  4437. get_page(page);
  4438. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  4439. (*pskb)->data_len += data_len;
  4440. (*pskb)->len += data_len;
  4441. (*pskb)->truesize += data_len;
  4442. (*pfrag)++;
  4443. }
  4444. return 0;
  4445. }
  4446. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  4447. struct qeth_qdio_buffer *qethbuffer,
  4448. struct qdio_buffer_element **__element, int *__offset,
  4449. struct qeth_hdr **hdr)
  4450. {
  4451. struct qdio_buffer_element *element = *__element;
  4452. struct qdio_buffer *buffer = qethbuffer->buffer;
  4453. int offset = *__offset;
  4454. struct sk_buff *skb = NULL;
  4455. int skb_len = 0;
  4456. void *data_ptr;
  4457. int data_len;
  4458. int headroom = 0;
  4459. int use_rx_sg = 0;
  4460. int frag = 0;
  4461. /* qeth_hdr must not cross element boundaries */
  4462. if (element->length < offset + sizeof(struct qeth_hdr)) {
  4463. if (qeth_is_last_sbale(element))
  4464. return NULL;
  4465. element++;
  4466. offset = 0;
  4467. if (element->length < sizeof(struct qeth_hdr))
  4468. return NULL;
  4469. }
  4470. *hdr = element->addr + offset;
  4471. offset += sizeof(struct qeth_hdr);
  4472. switch ((*hdr)->hdr.l2.id) {
  4473. case QETH_HEADER_TYPE_LAYER2:
  4474. skb_len = (*hdr)->hdr.l2.pkt_length;
  4475. break;
  4476. case QETH_HEADER_TYPE_LAYER3:
  4477. skb_len = (*hdr)->hdr.l3.length;
  4478. headroom = ETH_HLEN;
  4479. break;
  4480. case QETH_HEADER_TYPE_OSN:
  4481. skb_len = (*hdr)->hdr.osn.pdu_length;
  4482. headroom = sizeof(struct qeth_hdr);
  4483. break;
  4484. default:
  4485. break;
  4486. }
  4487. if (!skb_len)
  4488. return NULL;
  4489. if (((skb_len >= card->options.rx_sg_cb) &&
  4490. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  4491. (!atomic_read(&card->force_alloc_skb))) ||
  4492. (card->options.cq == QETH_CQ_ENABLED)) {
  4493. use_rx_sg = 1;
  4494. } else {
  4495. skb = dev_alloc_skb(skb_len + headroom);
  4496. if (!skb)
  4497. goto no_mem;
  4498. if (headroom)
  4499. skb_reserve(skb, headroom);
  4500. }
  4501. data_ptr = element->addr + offset;
  4502. while (skb_len) {
  4503. data_len = min(skb_len, (int)(element->length - offset));
  4504. if (data_len) {
  4505. if (use_rx_sg) {
  4506. if (qeth_create_skb_frag(qethbuffer, element,
  4507. &skb, offset, &frag, data_len))
  4508. goto no_mem;
  4509. } else {
  4510. memcpy(skb_put(skb, data_len), data_ptr,
  4511. data_len);
  4512. }
  4513. }
  4514. skb_len -= data_len;
  4515. if (skb_len) {
  4516. if (qeth_is_last_sbale(element)) {
  4517. QETH_CARD_TEXT(card, 4, "unexeob");
  4518. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  4519. dev_kfree_skb_any(skb);
  4520. card->stats.rx_errors++;
  4521. return NULL;
  4522. }
  4523. element++;
  4524. offset = 0;
  4525. data_ptr = element->addr;
  4526. } else {
  4527. offset += data_len;
  4528. }
  4529. }
  4530. *__element = element;
  4531. *__offset = offset;
  4532. if (use_rx_sg && card->options.performance_stats) {
  4533. card->perf_stats.sg_skbs_rx++;
  4534. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  4535. }
  4536. return skb;
  4537. no_mem:
  4538. if (net_ratelimit()) {
  4539. QETH_CARD_TEXT(card, 2, "noskbmem");
  4540. }
  4541. card->stats.rx_dropped++;
  4542. return NULL;
  4543. }
  4544. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  4545. static void qeth_unregister_dbf_views(void)
  4546. {
  4547. int x;
  4548. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4549. debug_unregister(qeth_dbf[x].id);
  4550. qeth_dbf[x].id = NULL;
  4551. }
  4552. }
  4553. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  4554. {
  4555. char dbf_txt_buf[32];
  4556. va_list args;
  4557. if (level > id->level)
  4558. return;
  4559. va_start(args, fmt);
  4560. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  4561. va_end(args);
  4562. debug_text_event(id, level, dbf_txt_buf);
  4563. }
  4564. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  4565. static int qeth_register_dbf_views(void)
  4566. {
  4567. int ret;
  4568. int x;
  4569. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4570. /* register the areas */
  4571. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  4572. qeth_dbf[x].pages,
  4573. qeth_dbf[x].areas,
  4574. qeth_dbf[x].len);
  4575. if (qeth_dbf[x].id == NULL) {
  4576. qeth_unregister_dbf_views();
  4577. return -ENOMEM;
  4578. }
  4579. /* register a view */
  4580. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  4581. if (ret) {
  4582. qeth_unregister_dbf_views();
  4583. return ret;
  4584. }
  4585. /* set a passing level */
  4586. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  4587. }
  4588. return 0;
  4589. }
  4590. int qeth_core_load_discipline(struct qeth_card *card,
  4591. enum qeth_discipline_id discipline)
  4592. {
  4593. int rc = 0;
  4594. mutex_lock(&qeth_mod_mutex);
  4595. switch (discipline) {
  4596. case QETH_DISCIPLINE_LAYER3:
  4597. card->discipline = try_then_request_module(
  4598. symbol_get(qeth_l3_discipline), "qeth_l3");
  4599. break;
  4600. case QETH_DISCIPLINE_LAYER2:
  4601. card->discipline = try_then_request_module(
  4602. symbol_get(qeth_l2_discipline), "qeth_l2");
  4603. break;
  4604. }
  4605. if (!card->discipline) {
  4606. dev_err(&card->gdev->dev, "There is no kernel module to "
  4607. "support discipline %d\n", discipline);
  4608. rc = -EINVAL;
  4609. }
  4610. mutex_unlock(&qeth_mod_mutex);
  4611. return rc;
  4612. }
  4613. void qeth_core_free_discipline(struct qeth_card *card)
  4614. {
  4615. if (card->options.layer2)
  4616. symbol_put(qeth_l2_discipline);
  4617. else
  4618. symbol_put(qeth_l3_discipline);
  4619. card->discipline = NULL;
  4620. }
  4621. static const struct device_type qeth_generic_devtype = {
  4622. .name = "qeth_generic",
  4623. .groups = qeth_generic_attr_groups,
  4624. };
  4625. static const struct device_type qeth_osn_devtype = {
  4626. .name = "qeth_osn",
  4627. .groups = qeth_osn_attr_groups,
  4628. };
  4629. #define DBF_NAME_LEN 20
  4630. struct qeth_dbf_entry {
  4631. char dbf_name[DBF_NAME_LEN];
  4632. debug_info_t *dbf_info;
  4633. struct list_head dbf_list;
  4634. };
  4635. static LIST_HEAD(qeth_dbf_list);
  4636. static DEFINE_MUTEX(qeth_dbf_list_mutex);
  4637. static debug_info_t *qeth_get_dbf_entry(char *name)
  4638. {
  4639. struct qeth_dbf_entry *entry;
  4640. debug_info_t *rc = NULL;
  4641. mutex_lock(&qeth_dbf_list_mutex);
  4642. list_for_each_entry(entry, &qeth_dbf_list, dbf_list) {
  4643. if (strcmp(entry->dbf_name, name) == 0) {
  4644. rc = entry->dbf_info;
  4645. break;
  4646. }
  4647. }
  4648. mutex_unlock(&qeth_dbf_list_mutex);
  4649. return rc;
  4650. }
  4651. static int qeth_add_dbf_entry(struct qeth_card *card, char *name)
  4652. {
  4653. struct qeth_dbf_entry *new_entry;
  4654. card->debug = debug_register(name, 2, 1, 8);
  4655. if (!card->debug) {
  4656. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  4657. goto err;
  4658. }
  4659. if (debug_register_view(card->debug, &debug_hex_ascii_view))
  4660. goto err_dbg;
  4661. new_entry = kzalloc(sizeof(struct qeth_dbf_entry), GFP_KERNEL);
  4662. if (!new_entry)
  4663. goto err_dbg;
  4664. strncpy(new_entry->dbf_name, name, DBF_NAME_LEN);
  4665. new_entry->dbf_info = card->debug;
  4666. mutex_lock(&qeth_dbf_list_mutex);
  4667. list_add(&new_entry->dbf_list, &qeth_dbf_list);
  4668. mutex_unlock(&qeth_dbf_list_mutex);
  4669. return 0;
  4670. err_dbg:
  4671. debug_unregister(card->debug);
  4672. err:
  4673. return -ENOMEM;
  4674. }
  4675. static void qeth_clear_dbf_list(void)
  4676. {
  4677. struct qeth_dbf_entry *entry, *tmp;
  4678. mutex_lock(&qeth_dbf_list_mutex);
  4679. list_for_each_entry_safe(entry, tmp, &qeth_dbf_list, dbf_list) {
  4680. list_del(&entry->dbf_list);
  4681. debug_unregister(entry->dbf_info);
  4682. kfree(entry);
  4683. }
  4684. mutex_unlock(&qeth_dbf_list_mutex);
  4685. }
  4686. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  4687. {
  4688. struct qeth_card *card;
  4689. struct device *dev;
  4690. int rc;
  4691. unsigned long flags;
  4692. char dbf_name[DBF_NAME_LEN];
  4693. QETH_DBF_TEXT(SETUP, 2, "probedev");
  4694. dev = &gdev->dev;
  4695. if (!get_device(dev))
  4696. return -ENODEV;
  4697. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  4698. card = qeth_alloc_card();
  4699. if (!card) {
  4700. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  4701. rc = -ENOMEM;
  4702. goto err_dev;
  4703. }
  4704. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  4705. dev_name(&gdev->dev));
  4706. card->debug = qeth_get_dbf_entry(dbf_name);
  4707. if (!card->debug) {
  4708. rc = qeth_add_dbf_entry(card, dbf_name);
  4709. if (rc)
  4710. goto err_card;
  4711. }
  4712. card->read.ccwdev = gdev->cdev[0];
  4713. card->write.ccwdev = gdev->cdev[1];
  4714. card->data.ccwdev = gdev->cdev[2];
  4715. dev_set_drvdata(&gdev->dev, card);
  4716. card->gdev = gdev;
  4717. gdev->cdev[0]->handler = qeth_irq;
  4718. gdev->cdev[1]->handler = qeth_irq;
  4719. gdev->cdev[2]->handler = qeth_irq;
  4720. rc = qeth_determine_card_type(card);
  4721. if (rc) {
  4722. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4723. goto err_card;
  4724. }
  4725. rc = qeth_setup_card(card);
  4726. if (rc) {
  4727. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  4728. goto err_card;
  4729. }
  4730. if (card->info.type == QETH_CARD_TYPE_OSN)
  4731. gdev->dev.type = &qeth_osn_devtype;
  4732. else
  4733. gdev->dev.type = &qeth_generic_devtype;
  4734. switch (card->info.type) {
  4735. case QETH_CARD_TYPE_OSN:
  4736. case QETH_CARD_TYPE_OSM:
  4737. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  4738. if (rc)
  4739. goto err_card;
  4740. rc = card->discipline->setup(card->gdev);
  4741. if (rc)
  4742. goto err_disc;
  4743. case QETH_CARD_TYPE_OSD:
  4744. case QETH_CARD_TYPE_OSX:
  4745. default:
  4746. break;
  4747. }
  4748. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4749. list_add_tail(&card->list, &qeth_core_card_list.list);
  4750. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4751. qeth_determine_capabilities(card);
  4752. return 0;
  4753. err_disc:
  4754. qeth_core_free_discipline(card);
  4755. err_card:
  4756. qeth_core_free_card(card);
  4757. err_dev:
  4758. put_device(dev);
  4759. return rc;
  4760. }
  4761. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  4762. {
  4763. unsigned long flags;
  4764. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4765. QETH_DBF_TEXT(SETUP, 2, "removedv");
  4766. if (card->discipline) {
  4767. card->discipline->remove(gdev);
  4768. qeth_core_free_discipline(card);
  4769. }
  4770. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4771. list_del(&card->list);
  4772. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4773. qeth_core_free_card(card);
  4774. dev_set_drvdata(&gdev->dev, NULL);
  4775. put_device(&gdev->dev);
  4776. return;
  4777. }
  4778. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  4779. {
  4780. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4781. int rc = 0;
  4782. int def_discipline;
  4783. if (!card->discipline) {
  4784. if (card->info.type == QETH_CARD_TYPE_IQD)
  4785. def_discipline = QETH_DISCIPLINE_LAYER3;
  4786. else
  4787. def_discipline = QETH_DISCIPLINE_LAYER2;
  4788. rc = qeth_core_load_discipline(card, def_discipline);
  4789. if (rc)
  4790. goto err;
  4791. rc = card->discipline->setup(card->gdev);
  4792. if (rc)
  4793. goto err;
  4794. }
  4795. rc = card->discipline->set_online(gdev);
  4796. err:
  4797. return rc;
  4798. }
  4799. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  4800. {
  4801. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4802. return card->discipline->set_offline(gdev);
  4803. }
  4804. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  4805. {
  4806. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4807. if (card->discipline && card->discipline->shutdown)
  4808. card->discipline->shutdown(gdev);
  4809. }
  4810. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  4811. {
  4812. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4813. if (card->discipline && card->discipline->prepare)
  4814. return card->discipline->prepare(gdev);
  4815. return 0;
  4816. }
  4817. static void qeth_core_complete(struct ccwgroup_device *gdev)
  4818. {
  4819. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4820. if (card->discipline && card->discipline->complete)
  4821. card->discipline->complete(gdev);
  4822. }
  4823. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  4824. {
  4825. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4826. if (card->discipline && card->discipline->freeze)
  4827. return card->discipline->freeze(gdev);
  4828. return 0;
  4829. }
  4830. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4831. {
  4832. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4833. if (card->discipline && card->discipline->thaw)
  4834. return card->discipline->thaw(gdev);
  4835. return 0;
  4836. }
  4837. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4838. {
  4839. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4840. if (card->discipline && card->discipline->restore)
  4841. return card->discipline->restore(gdev);
  4842. return 0;
  4843. }
  4844. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4845. .driver = {
  4846. .owner = THIS_MODULE,
  4847. .name = "qeth",
  4848. },
  4849. .setup = qeth_core_probe_device,
  4850. .remove = qeth_core_remove_device,
  4851. .set_online = qeth_core_set_online,
  4852. .set_offline = qeth_core_set_offline,
  4853. .shutdown = qeth_core_shutdown,
  4854. .prepare = qeth_core_prepare,
  4855. .complete = qeth_core_complete,
  4856. .freeze = qeth_core_freeze,
  4857. .thaw = qeth_core_thaw,
  4858. .restore = qeth_core_restore,
  4859. };
  4860. static ssize_t qeth_core_driver_group_store(struct device_driver *ddrv,
  4861. const char *buf, size_t count)
  4862. {
  4863. int err;
  4864. err = ccwgroup_create_dev(qeth_core_root_dev,
  4865. &qeth_core_ccwgroup_driver, 3, buf);
  4866. return err ? err : count;
  4867. }
  4868. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4869. static struct attribute *qeth_drv_attrs[] = {
  4870. &driver_attr_group.attr,
  4871. NULL,
  4872. };
  4873. static struct attribute_group qeth_drv_attr_group = {
  4874. .attrs = qeth_drv_attrs,
  4875. };
  4876. static const struct attribute_group *qeth_drv_attr_groups[] = {
  4877. &qeth_drv_attr_group,
  4878. NULL,
  4879. };
  4880. static struct {
  4881. const char str[ETH_GSTRING_LEN];
  4882. } qeth_ethtool_stats_keys[] = {
  4883. /* 0 */{"rx skbs"},
  4884. {"rx buffers"},
  4885. {"tx skbs"},
  4886. {"tx buffers"},
  4887. {"tx skbs no packing"},
  4888. {"tx buffers no packing"},
  4889. {"tx skbs packing"},
  4890. {"tx buffers packing"},
  4891. {"tx sg skbs"},
  4892. {"tx sg frags"},
  4893. /* 10 */{"rx sg skbs"},
  4894. {"rx sg frags"},
  4895. {"rx sg page allocs"},
  4896. {"tx large kbytes"},
  4897. {"tx large count"},
  4898. {"tx pk state ch n->p"},
  4899. {"tx pk state ch p->n"},
  4900. {"tx pk watermark low"},
  4901. {"tx pk watermark high"},
  4902. {"queue 0 buffer usage"},
  4903. /* 20 */{"queue 1 buffer usage"},
  4904. {"queue 2 buffer usage"},
  4905. {"queue 3 buffer usage"},
  4906. {"rx poll time"},
  4907. {"rx poll count"},
  4908. {"rx do_QDIO time"},
  4909. {"rx do_QDIO count"},
  4910. {"tx handler time"},
  4911. {"tx handler count"},
  4912. {"tx time"},
  4913. /* 30 */{"tx count"},
  4914. {"tx do_QDIO time"},
  4915. {"tx do_QDIO count"},
  4916. {"tx csum"},
  4917. {"tx lin"},
  4918. {"cq handler count"},
  4919. {"cq handler time"}
  4920. };
  4921. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4922. {
  4923. switch (stringset) {
  4924. case ETH_SS_STATS:
  4925. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4926. default:
  4927. return -EINVAL;
  4928. }
  4929. }
  4930. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4931. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4932. struct ethtool_stats *stats, u64 *data)
  4933. {
  4934. struct qeth_card *card = dev->ml_priv;
  4935. data[0] = card->stats.rx_packets -
  4936. card->perf_stats.initial_rx_packets;
  4937. data[1] = card->perf_stats.bufs_rec;
  4938. data[2] = card->stats.tx_packets -
  4939. card->perf_stats.initial_tx_packets;
  4940. data[3] = card->perf_stats.bufs_sent;
  4941. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4942. - card->perf_stats.skbs_sent_pack;
  4943. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4944. data[6] = card->perf_stats.skbs_sent_pack;
  4945. data[7] = card->perf_stats.bufs_sent_pack;
  4946. data[8] = card->perf_stats.sg_skbs_sent;
  4947. data[9] = card->perf_stats.sg_frags_sent;
  4948. data[10] = card->perf_stats.sg_skbs_rx;
  4949. data[11] = card->perf_stats.sg_frags_rx;
  4950. data[12] = card->perf_stats.sg_alloc_page_rx;
  4951. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4952. data[14] = card->perf_stats.large_send_cnt;
  4953. data[15] = card->perf_stats.sc_dp_p;
  4954. data[16] = card->perf_stats.sc_p_dp;
  4955. data[17] = QETH_LOW_WATERMARK_PACK;
  4956. data[18] = QETH_HIGH_WATERMARK_PACK;
  4957. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4958. data[20] = (card->qdio.no_out_queues > 1) ?
  4959. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4960. data[21] = (card->qdio.no_out_queues > 2) ?
  4961. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4962. data[22] = (card->qdio.no_out_queues > 3) ?
  4963. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4964. data[23] = card->perf_stats.inbound_time;
  4965. data[24] = card->perf_stats.inbound_cnt;
  4966. data[25] = card->perf_stats.inbound_do_qdio_time;
  4967. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4968. data[27] = card->perf_stats.outbound_handler_time;
  4969. data[28] = card->perf_stats.outbound_handler_cnt;
  4970. data[29] = card->perf_stats.outbound_time;
  4971. data[30] = card->perf_stats.outbound_cnt;
  4972. data[31] = card->perf_stats.outbound_do_qdio_time;
  4973. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4974. data[33] = card->perf_stats.tx_csum;
  4975. data[34] = card->perf_stats.tx_lin;
  4976. data[35] = card->perf_stats.cq_cnt;
  4977. data[36] = card->perf_stats.cq_time;
  4978. }
  4979. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4980. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4981. {
  4982. switch (stringset) {
  4983. case ETH_SS_STATS:
  4984. memcpy(data, &qeth_ethtool_stats_keys,
  4985. sizeof(qeth_ethtool_stats_keys));
  4986. break;
  4987. default:
  4988. WARN_ON(1);
  4989. break;
  4990. }
  4991. }
  4992. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4993. void qeth_core_get_drvinfo(struct net_device *dev,
  4994. struct ethtool_drvinfo *info)
  4995. {
  4996. struct qeth_card *card = dev->ml_priv;
  4997. strlcpy(info->driver, card->options.layer2 ? "qeth_l2" : "qeth_l3",
  4998. sizeof(info->driver));
  4999. strlcpy(info->version, "1.0", sizeof(info->version));
  5000. strlcpy(info->fw_version, card->info.mcl_level,
  5001. sizeof(info->fw_version));
  5002. snprintf(info->bus_info, sizeof(info->bus_info), "%s/%s/%s",
  5003. CARD_RDEV_ID(card), CARD_WDEV_ID(card), CARD_DDEV_ID(card));
  5004. }
  5005. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  5006. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  5007. struct ethtool_cmd *ecmd)
  5008. {
  5009. struct qeth_card *card = netdev->ml_priv;
  5010. enum qeth_link_types link_type;
  5011. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  5012. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  5013. else
  5014. link_type = card->info.link_type;
  5015. ecmd->transceiver = XCVR_INTERNAL;
  5016. ecmd->supported = SUPPORTED_Autoneg;
  5017. ecmd->advertising = ADVERTISED_Autoneg;
  5018. ecmd->duplex = DUPLEX_FULL;
  5019. ecmd->autoneg = AUTONEG_ENABLE;
  5020. switch (link_type) {
  5021. case QETH_LINK_TYPE_FAST_ETH:
  5022. case QETH_LINK_TYPE_LANE_ETH100:
  5023. ecmd->supported |= SUPPORTED_10baseT_Half |
  5024. SUPPORTED_10baseT_Full |
  5025. SUPPORTED_100baseT_Half |
  5026. SUPPORTED_100baseT_Full |
  5027. SUPPORTED_TP;
  5028. ecmd->advertising |= ADVERTISED_10baseT_Half |
  5029. ADVERTISED_10baseT_Full |
  5030. ADVERTISED_100baseT_Half |
  5031. ADVERTISED_100baseT_Full |
  5032. ADVERTISED_TP;
  5033. ecmd->speed = SPEED_100;
  5034. ecmd->port = PORT_TP;
  5035. break;
  5036. case QETH_LINK_TYPE_GBIT_ETH:
  5037. case QETH_LINK_TYPE_LANE_ETH1000:
  5038. ecmd->supported |= SUPPORTED_10baseT_Half |
  5039. SUPPORTED_10baseT_Full |
  5040. SUPPORTED_100baseT_Half |
  5041. SUPPORTED_100baseT_Full |
  5042. SUPPORTED_1000baseT_Half |
  5043. SUPPORTED_1000baseT_Full |
  5044. SUPPORTED_FIBRE;
  5045. ecmd->advertising |= ADVERTISED_10baseT_Half |
  5046. ADVERTISED_10baseT_Full |
  5047. ADVERTISED_100baseT_Half |
  5048. ADVERTISED_100baseT_Full |
  5049. ADVERTISED_1000baseT_Half |
  5050. ADVERTISED_1000baseT_Full |
  5051. ADVERTISED_FIBRE;
  5052. ecmd->speed = SPEED_1000;
  5053. ecmd->port = PORT_FIBRE;
  5054. break;
  5055. case QETH_LINK_TYPE_10GBIT_ETH:
  5056. ecmd->supported |= SUPPORTED_10baseT_Half |
  5057. SUPPORTED_10baseT_Full |
  5058. SUPPORTED_100baseT_Half |
  5059. SUPPORTED_100baseT_Full |
  5060. SUPPORTED_1000baseT_Half |
  5061. SUPPORTED_1000baseT_Full |
  5062. SUPPORTED_10000baseT_Full |
  5063. SUPPORTED_FIBRE;
  5064. ecmd->advertising |= ADVERTISED_10baseT_Half |
  5065. ADVERTISED_10baseT_Full |
  5066. ADVERTISED_100baseT_Half |
  5067. ADVERTISED_100baseT_Full |
  5068. ADVERTISED_1000baseT_Half |
  5069. ADVERTISED_1000baseT_Full |
  5070. ADVERTISED_10000baseT_Full |
  5071. ADVERTISED_FIBRE;
  5072. ecmd->speed = SPEED_10000;
  5073. ecmd->port = PORT_FIBRE;
  5074. break;
  5075. default:
  5076. ecmd->supported |= SUPPORTED_10baseT_Half |
  5077. SUPPORTED_10baseT_Full |
  5078. SUPPORTED_TP;
  5079. ecmd->advertising |= ADVERTISED_10baseT_Half |
  5080. ADVERTISED_10baseT_Full |
  5081. ADVERTISED_TP;
  5082. ecmd->speed = SPEED_10;
  5083. ecmd->port = PORT_TP;
  5084. }
  5085. return 0;
  5086. }
  5087. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  5088. static int __init qeth_core_init(void)
  5089. {
  5090. int rc;
  5091. pr_info("loading core functions\n");
  5092. INIT_LIST_HEAD(&qeth_core_card_list.list);
  5093. INIT_LIST_HEAD(&qeth_dbf_list);
  5094. rwlock_init(&qeth_core_card_list.rwlock);
  5095. mutex_init(&qeth_mod_mutex);
  5096. qeth_wq = create_singlethread_workqueue("qeth_wq");
  5097. rc = qeth_register_dbf_views();
  5098. if (rc)
  5099. goto out_err;
  5100. qeth_core_root_dev = root_device_register("qeth");
  5101. rc = PTR_RET(qeth_core_root_dev);
  5102. if (rc)
  5103. goto register_err;
  5104. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  5105. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  5106. if (!qeth_core_header_cache) {
  5107. rc = -ENOMEM;
  5108. goto slab_err;
  5109. }
  5110. qeth_qdio_outbuf_cache = kmem_cache_create("qeth_buf",
  5111. sizeof(struct qeth_qdio_out_buffer), 0, 0, NULL);
  5112. if (!qeth_qdio_outbuf_cache) {
  5113. rc = -ENOMEM;
  5114. goto cqslab_err;
  5115. }
  5116. rc = ccw_driver_register(&qeth_ccw_driver);
  5117. if (rc)
  5118. goto ccw_err;
  5119. qeth_core_ccwgroup_driver.driver.groups = qeth_drv_attr_groups;
  5120. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  5121. if (rc)
  5122. goto ccwgroup_err;
  5123. return 0;
  5124. ccwgroup_err:
  5125. ccw_driver_unregister(&qeth_ccw_driver);
  5126. ccw_err:
  5127. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  5128. cqslab_err:
  5129. kmem_cache_destroy(qeth_core_header_cache);
  5130. slab_err:
  5131. root_device_unregister(qeth_core_root_dev);
  5132. register_err:
  5133. qeth_unregister_dbf_views();
  5134. out_err:
  5135. pr_err("Initializing the qeth device driver failed\n");
  5136. return rc;
  5137. }
  5138. static void __exit qeth_core_exit(void)
  5139. {
  5140. qeth_clear_dbf_list();
  5141. destroy_workqueue(qeth_wq);
  5142. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  5143. ccw_driver_unregister(&qeth_ccw_driver);
  5144. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  5145. kmem_cache_destroy(qeth_core_header_cache);
  5146. root_device_unregister(qeth_core_root_dev);
  5147. qeth_unregister_dbf_views();
  5148. pr_info("core functions removed\n");
  5149. }
  5150. module_init(qeth_core_init);
  5151. module_exit(qeth_core_exit);
  5152. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  5153. MODULE_DESCRIPTION("qeth core functions");
  5154. MODULE_LICENSE("GPL");