pwm-renesas-tpu.c 12 KB

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  1. /*
  2. * R-Mobile TPU PWM driver
  3. *
  4. * Copyright (C) 2012 Renesas Solutions Corp.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/clk.h>
  16. #include <linux/err.h>
  17. #include <linux/io.h>
  18. #include <linux/init.h>
  19. #include <linux/ioport.h>
  20. #include <linux/module.h>
  21. #include <linux/mutex.h>
  22. #include <linux/of.h>
  23. #include <linux/platform_data/pwm-renesas-tpu.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/pwm.h>
  27. #include <linux/slab.h>
  28. #include <linux/spinlock.h>
  29. #define TPU_TSTR 0x00 /* Timer start register (shared) */
  30. #define TPU_TCRn 0x00 /* Timer control register */
  31. #define TPU_TCR_CCLR_NONE (0 << 5)
  32. #define TPU_TCR_CCLR_TGRA (1 << 5)
  33. #define TPU_TCR_CCLR_TGRB (2 << 5)
  34. #define TPU_TCR_CCLR_TGRC (5 << 5)
  35. #define TPU_TCR_CCLR_TGRD (6 << 5)
  36. #define TPU_TCR_CKEG_RISING (0 << 3)
  37. #define TPU_TCR_CKEG_FALLING (1 << 3)
  38. #define TPU_TCR_CKEG_BOTH (2 << 3)
  39. #define TPU_TMDRn 0x04 /* Timer mode register */
  40. #define TPU_TMDR_BFWT (1 << 6)
  41. #define TPU_TMDR_BFB (1 << 5)
  42. #define TPU_TMDR_BFA (1 << 4)
  43. #define TPU_TMDR_MD_NORMAL (0 << 0)
  44. #define TPU_TMDR_MD_PWM (2 << 0)
  45. #define TPU_TIORn 0x08 /* Timer I/O control register */
  46. #define TPU_TIOR_IOA_0 (0 << 0)
  47. #define TPU_TIOR_IOA_0_CLR (1 << 0)
  48. #define TPU_TIOR_IOA_0_SET (2 << 0)
  49. #define TPU_TIOR_IOA_0_TOGGLE (3 << 0)
  50. #define TPU_TIOR_IOA_1 (4 << 0)
  51. #define TPU_TIOR_IOA_1_CLR (5 << 0)
  52. #define TPU_TIOR_IOA_1_SET (6 << 0)
  53. #define TPU_TIOR_IOA_1_TOGGLE (7 << 0)
  54. #define TPU_TIERn 0x0c /* Timer interrupt enable register */
  55. #define TPU_TSRn 0x10 /* Timer status register */
  56. #define TPU_TCNTn 0x14 /* Timer counter */
  57. #define TPU_TGRAn 0x18 /* Timer general register A */
  58. #define TPU_TGRBn 0x1c /* Timer general register B */
  59. #define TPU_TGRCn 0x20 /* Timer general register C */
  60. #define TPU_TGRDn 0x24 /* Timer general register D */
  61. #define TPU_CHANNEL_OFFSET 0x10
  62. #define TPU_CHANNEL_SIZE 0x40
  63. enum tpu_pin_state {
  64. TPU_PIN_INACTIVE, /* Pin is driven inactive */
  65. TPU_PIN_PWM, /* Pin is driven by PWM */
  66. TPU_PIN_ACTIVE, /* Pin is driven active */
  67. };
  68. struct tpu_device;
  69. struct tpu_pwm_device {
  70. bool timer_on; /* Whether the timer is running */
  71. struct tpu_device *tpu;
  72. unsigned int channel; /* Channel number in the TPU */
  73. enum pwm_polarity polarity;
  74. unsigned int prescaler;
  75. u16 period;
  76. u16 duty;
  77. };
  78. struct tpu_device {
  79. struct platform_device *pdev;
  80. enum pwm_polarity polarities[TPU_CHANNEL_MAX];
  81. struct pwm_chip chip;
  82. spinlock_t lock;
  83. void __iomem *base;
  84. struct clk *clk;
  85. };
  86. #define to_tpu_device(c) container_of(c, struct tpu_device, chip)
  87. static void tpu_pwm_write(struct tpu_pwm_device *pwm, int reg_nr, u16 value)
  88. {
  89. void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET
  90. + pwm->channel * TPU_CHANNEL_SIZE;
  91. iowrite16(value, base + reg_nr);
  92. }
  93. static void tpu_pwm_set_pin(struct tpu_pwm_device *pwm,
  94. enum tpu_pin_state state)
  95. {
  96. static const char * const states[] = { "inactive", "PWM", "active" };
  97. dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n",
  98. pwm->channel, states[state]);
  99. switch (state) {
  100. case TPU_PIN_INACTIVE:
  101. tpu_pwm_write(pwm, TPU_TIORn,
  102. pwm->polarity == PWM_POLARITY_INVERSED ?
  103. TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
  104. break;
  105. case TPU_PIN_PWM:
  106. tpu_pwm_write(pwm, TPU_TIORn,
  107. pwm->polarity == PWM_POLARITY_INVERSED ?
  108. TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
  109. break;
  110. case TPU_PIN_ACTIVE:
  111. tpu_pwm_write(pwm, TPU_TIORn,
  112. pwm->polarity == PWM_POLARITY_INVERSED ?
  113. TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
  114. break;
  115. }
  116. }
  117. static void tpu_pwm_start_stop(struct tpu_pwm_device *pwm, int start)
  118. {
  119. unsigned long flags;
  120. u16 value;
  121. spin_lock_irqsave(&pwm->tpu->lock, flags);
  122. value = ioread16(pwm->tpu->base + TPU_TSTR);
  123. if (start)
  124. value |= 1 << pwm->channel;
  125. else
  126. value &= ~(1 << pwm->channel);
  127. iowrite16(value, pwm->tpu->base + TPU_TSTR);
  128. spin_unlock_irqrestore(&pwm->tpu->lock, flags);
  129. }
  130. static int tpu_pwm_timer_start(struct tpu_pwm_device *pwm)
  131. {
  132. int ret;
  133. if (!pwm->timer_on) {
  134. /* Wake up device and enable clock. */
  135. pm_runtime_get_sync(&pwm->tpu->pdev->dev);
  136. ret = clk_prepare_enable(pwm->tpu->clk);
  137. if (ret) {
  138. dev_err(&pwm->tpu->pdev->dev, "cannot enable clock\n");
  139. return ret;
  140. }
  141. pwm->timer_on = true;
  142. }
  143. /*
  144. * Make sure the channel is stopped, as we need to reconfigure it
  145. * completely. First drive the pin to the inactive state to avoid
  146. * glitches.
  147. */
  148. tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE);
  149. tpu_pwm_start_stop(pwm, false);
  150. /*
  151. * - Clear TCNT on TGRB match
  152. * - Count on rising edge
  153. * - Set prescaler
  154. * - Output 0 until TGRA, output 1 until TGRB (active low polarity)
  155. * - Output 1 until TGRA, output 0 until TGRB (active high polarity
  156. * - PWM mode
  157. */
  158. tpu_pwm_write(pwm, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |
  159. pwm->prescaler);
  160. tpu_pwm_write(pwm, TPU_TMDRn, TPU_TMDR_MD_PWM);
  161. tpu_pwm_set_pin(pwm, TPU_PIN_PWM);
  162. tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty);
  163. tpu_pwm_write(pwm, TPU_TGRBn, pwm->period);
  164. dev_dbg(&pwm->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
  165. pwm->channel, pwm->duty, pwm->period);
  166. /* Start the channel. */
  167. tpu_pwm_start_stop(pwm, true);
  168. return 0;
  169. }
  170. static void tpu_pwm_timer_stop(struct tpu_pwm_device *pwm)
  171. {
  172. if (!pwm->timer_on)
  173. return;
  174. /* Disable channel. */
  175. tpu_pwm_start_stop(pwm, false);
  176. /* Stop clock and mark device as idle. */
  177. clk_disable_unprepare(pwm->tpu->clk);
  178. pm_runtime_put(&pwm->tpu->pdev->dev);
  179. pwm->timer_on = false;
  180. }
  181. /* -----------------------------------------------------------------------------
  182. * PWM API
  183. */
  184. static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *_pwm)
  185. {
  186. struct tpu_device *tpu = to_tpu_device(chip);
  187. struct tpu_pwm_device *pwm;
  188. if (_pwm->hwpwm >= TPU_CHANNEL_MAX)
  189. return -EINVAL;
  190. pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
  191. if (pwm == NULL)
  192. return -ENOMEM;
  193. pwm->tpu = tpu;
  194. pwm->channel = _pwm->hwpwm;
  195. pwm->polarity = tpu->polarities[pwm->channel];
  196. pwm->prescaler = 0;
  197. pwm->period = 0;
  198. pwm->duty = 0;
  199. pwm->timer_on = false;
  200. pwm_set_chip_data(_pwm, pwm);
  201. return 0;
  202. }
  203. static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *_pwm)
  204. {
  205. struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
  206. tpu_pwm_timer_stop(pwm);
  207. kfree(pwm);
  208. }
  209. static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *_pwm,
  210. int duty_ns, int period_ns)
  211. {
  212. static const unsigned int prescalers[] = { 1, 4, 16, 64 };
  213. struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
  214. struct tpu_device *tpu = to_tpu_device(chip);
  215. unsigned int prescaler;
  216. bool duty_only = false;
  217. u32 clk_rate;
  218. u32 period;
  219. u32 duty;
  220. int ret;
  221. /*
  222. * Pick a prescaler to avoid overflowing the counter.
  223. * TODO: Pick the highest acceptable prescaler.
  224. */
  225. clk_rate = clk_get_rate(tpu->clk);
  226. for (prescaler = 0; prescaler < ARRAY_SIZE(prescalers); ++prescaler) {
  227. period = clk_rate / prescalers[prescaler]
  228. / (NSEC_PER_SEC / period_ns);
  229. if (period <= 0xffff)
  230. break;
  231. }
  232. if (prescaler == ARRAY_SIZE(prescalers) || period == 0) {
  233. dev_err(&tpu->pdev->dev, "clock rate mismatch\n");
  234. return -ENOTSUPP;
  235. }
  236. if (duty_ns) {
  237. duty = clk_rate / prescalers[prescaler]
  238. / (NSEC_PER_SEC / duty_ns);
  239. if (duty > period)
  240. return -EINVAL;
  241. } else {
  242. duty = 0;
  243. }
  244. dev_dbg(&tpu->pdev->dev,
  245. "rate %u, prescaler %u, period %u, duty %u\n",
  246. clk_rate, prescalers[prescaler], period, duty);
  247. if (pwm->prescaler == prescaler && pwm->period == period)
  248. duty_only = true;
  249. pwm->prescaler = prescaler;
  250. pwm->period = period;
  251. pwm->duty = duty;
  252. /* If the channel is disabled we're done. */
  253. if (!test_bit(PWMF_ENABLED, &_pwm->flags))
  254. return 0;
  255. if (duty_only && pwm->timer_on) {
  256. /*
  257. * If only the duty cycle changed and the timer is already
  258. * running, there's no need to reconfigure it completely, Just
  259. * modify the duty cycle.
  260. */
  261. tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty);
  262. dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", pwm->channel,
  263. pwm->duty);
  264. } else {
  265. /* Otherwise perform a full reconfiguration. */
  266. ret = tpu_pwm_timer_start(pwm);
  267. if (ret < 0)
  268. return ret;
  269. }
  270. if (duty == 0 || duty == period) {
  271. /*
  272. * To avoid running the timer when not strictly required, handle
  273. * 0% and 100% duty cycles as fixed levels and stop the timer.
  274. */
  275. tpu_pwm_set_pin(pwm, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
  276. tpu_pwm_timer_stop(pwm);
  277. }
  278. return 0;
  279. }
  280. static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *_pwm,
  281. enum pwm_polarity polarity)
  282. {
  283. struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
  284. pwm->polarity = polarity;
  285. return 0;
  286. }
  287. static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *_pwm)
  288. {
  289. struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
  290. int ret;
  291. ret = tpu_pwm_timer_start(pwm);
  292. if (ret < 0)
  293. return ret;
  294. /*
  295. * To avoid running the timer when not strictly required, handle 0% and
  296. * 100% duty cycles as fixed levels and stop the timer.
  297. */
  298. if (pwm->duty == 0 || pwm->duty == pwm->period) {
  299. tpu_pwm_set_pin(pwm, pwm->duty ?
  300. TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
  301. tpu_pwm_timer_stop(pwm);
  302. }
  303. return 0;
  304. }
  305. static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *_pwm)
  306. {
  307. struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
  308. /* The timer must be running to modify the pin output configuration. */
  309. tpu_pwm_timer_start(pwm);
  310. tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE);
  311. tpu_pwm_timer_stop(pwm);
  312. }
  313. static const struct pwm_ops tpu_pwm_ops = {
  314. .request = tpu_pwm_request,
  315. .free = tpu_pwm_free,
  316. .config = tpu_pwm_config,
  317. .set_polarity = tpu_pwm_set_polarity,
  318. .enable = tpu_pwm_enable,
  319. .disable = tpu_pwm_disable,
  320. .owner = THIS_MODULE,
  321. };
  322. /* -----------------------------------------------------------------------------
  323. * Probe and remove
  324. */
  325. static void tpu_parse_pdata(struct tpu_device *tpu)
  326. {
  327. struct tpu_pwm_platform_data *pdata = tpu->pdev->dev.platform_data;
  328. unsigned int i;
  329. for (i = 0; i < ARRAY_SIZE(tpu->polarities); ++i)
  330. tpu->polarities[i] = pdata ? pdata->channels[i].polarity
  331. : PWM_POLARITY_NORMAL;
  332. }
  333. static int tpu_probe(struct platform_device *pdev)
  334. {
  335. struct tpu_device *tpu;
  336. struct resource *res;
  337. int ret;
  338. tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
  339. if (tpu == NULL) {
  340. dev_err(&pdev->dev, "failed to allocate driver data\n");
  341. return -ENOMEM;
  342. }
  343. spin_lock_init(&tpu->lock);
  344. tpu->pdev = pdev;
  345. /* Initialize device configuration from platform data. */
  346. tpu_parse_pdata(tpu);
  347. /* Map memory, get clock and pin control. */
  348. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  349. tpu->base = devm_ioremap_resource(&pdev->dev, res);
  350. if (IS_ERR(tpu->base))
  351. return PTR_ERR(tpu->base);
  352. tpu->clk = devm_clk_get(&pdev->dev, NULL);
  353. if (IS_ERR(tpu->clk)) {
  354. dev_err(&pdev->dev, "cannot get clock\n");
  355. return PTR_ERR(tpu->clk);
  356. }
  357. /* Initialize and register the device. */
  358. platform_set_drvdata(pdev, tpu);
  359. tpu->chip.dev = &pdev->dev;
  360. tpu->chip.ops = &tpu_pwm_ops;
  361. tpu->chip.of_xlate = of_pwm_xlate_with_flags;
  362. tpu->chip.of_pwm_n_cells = 3;
  363. tpu->chip.base = -1;
  364. tpu->chip.npwm = TPU_CHANNEL_MAX;
  365. ret = pwmchip_add(&tpu->chip);
  366. if (ret < 0) {
  367. dev_err(&pdev->dev, "failed to register PWM chip\n");
  368. return ret;
  369. }
  370. dev_info(&pdev->dev, "TPU PWM %d registered\n", tpu->pdev->id);
  371. pm_runtime_enable(&pdev->dev);
  372. return 0;
  373. }
  374. static int tpu_remove(struct platform_device *pdev)
  375. {
  376. struct tpu_device *tpu = platform_get_drvdata(pdev);
  377. int ret;
  378. ret = pwmchip_remove(&tpu->chip);
  379. if (ret)
  380. return ret;
  381. pm_runtime_disable(&pdev->dev);
  382. return 0;
  383. }
  384. #ifdef CONFIG_OF
  385. static const struct of_device_id tpu_of_table[] = {
  386. { .compatible = "renesas,tpu-r8a73a4", },
  387. { .compatible = "renesas,tpu-r8a7740", },
  388. { .compatible = "renesas,tpu-r8a7790", },
  389. { .compatible = "renesas,tpu-sh7372", },
  390. { .compatible = "renesas,tpu", },
  391. { },
  392. };
  393. MODULE_DEVICE_TABLE(of, tpu_of_table);
  394. #endif
  395. static struct platform_driver tpu_driver = {
  396. .probe = tpu_probe,
  397. .remove = tpu_remove,
  398. .driver = {
  399. .name = "renesas-tpu-pwm",
  400. .owner = THIS_MODULE,
  401. .of_match_table = of_match_ptr(tpu_of_table),
  402. }
  403. };
  404. module_platform_driver(tpu_driver);
  405. MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
  406. MODULE_DESCRIPTION("Renesas TPU PWM Driver");
  407. MODULE_LICENSE("GPL v2");
  408. MODULE_ALIAS("platform:renesas-tpu-pwm");