pinctrl-coh901.c 23 KB

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  1. /*
  2. * U300 GPIO module.
  3. *
  4. * Copyright (C) 2007-2012 ST-Ericsson AB
  5. * License terms: GNU General Public License (GPL) version 2
  6. * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
  7. * Author: Linus Walleij <linus.walleij@linaro.org>
  8. * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/irq.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/delay.h>
  14. #include <linux/errno.h>
  15. #include <linux/io.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/clk.h>
  18. #include <linux/err.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/gpio.h>
  21. #include <linux/list.h>
  22. #include <linux/slab.h>
  23. #include <linux/pinctrl/consumer.h>
  24. #include <linux/pinctrl/pinconf-generic.h>
  25. #include "pinctrl-coh901.h"
  26. #define U300_GPIO_PORT_STRIDE (0x30)
  27. /*
  28. * Control Register 32bit (R/W)
  29. * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
  30. * gives the number of GPIO pins.
  31. * bit 8-2 (mask 0x000001FC) contains the core version ID.
  32. */
  33. #define U300_GPIO_CR (0x00)
  34. #define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
  35. #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
  36. #define U300_GPIO_PXPDIR (0x04)
  37. #define U300_GPIO_PXPDOR (0x08)
  38. #define U300_GPIO_PXPCR (0x0C)
  39. #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
  40. #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
  41. #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
  42. #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
  43. #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
  44. #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
  45. #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
  46. #define U300_GPIO_PXPER (0x10)
  47. #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
  48. #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
  49. #define U300_GPIO_PXIEV (0x14)
  50. #define U300_GPIO_PXIEN (0x18)
  51. #define U300_GPIO_PXIFR (0x1C)
  52. #define U300_GPIO_PXICR (0x20)
  53. #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
  54. #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
  55. #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
  56. #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
  57. /* 8 bits per port, no version has more than 7 ports */
  58. #define U300_GPIO_NUM_PORTS 7
  59. #define U300_GPIO_PINS_PER_PORT 8
  60. #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
  61. struct u300_gpio {
  62. struct gpio_chip chip;
  63. struct list_head port_list;
  64. struct clk *clk;
  65. void __iomem *base;
  66. struct device *dev;
  67. u32 stride;
  68. /* Register offsets */
  69. u32 pcr;
  70. u32 dor;
  71. u32 dir;
  72. u32 per;
  73. u32 icr;
  74. u32 ien;
  75. u32 iev;
  76. };
  77. struct u300_gpio_port {
  78. struct list_head node;
  79. struct u300_gpio *gpio;
  80. char name[8];
  81. struct irq_domain *domain;
  82. int irq;
  83. int number;
  84. u8 toggle_edge_mode;
  85. };
  86. /*
  87. * Macro to expand to read a specific register found in the "gpio"
  88. * struct. It requires the struct u300_gpio *gpio variable to exist in
  89. * its context. It calculates the port offset from the given pin
  90. * offset, muliplies by the port stride and adds the register offset
  91. * so it provides a pointer to the desired register.
  92. */
  93. #define U300_PIN_REG(pin, reg) \
  94. (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
  95. /*
  96. * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
  97. * register.
  98. */
  99. #define U300_PIN_BIT(pin) \
  100. (1 << (pin & 0x07))
  101. struct u300_gpio_confdata {
  102. u16 bias_mode;
  103. bool output;
  104. int outval;
  105. };
  106. #define U300_FLOATING_INPUT { \
  107. .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
  108. .output = false, \
  109. }
  110. #define U300_PULL_UP_INPUT { \
  111. .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
  112. .output = false, \
  113. }
  114. #define U300_OUTPUT_LOW { \
  115. .output = true, \
  116. .outval = 0, \
  117. }
  118. #define U300_OUTPUT_HIGH { \
  119. .output = true, \
  120. .outval = 1, \
  121. }
  122. /* Initial configuration */
  123. static const struct __initconst u300_gpio_confdata
  124. bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
  125. /* Port 0, pins 0-7 */
  126. {
  127. U300_FLOATING_INPUT,
  128. U300_OUTPUT_HIGH,
  129. U300_FLOATING_INPUT,
  130. U300_OUTPUT_LOW,
  131. U300_OUTPUT_LOW,
  132. U300_OUTPUT_LOW,
  133. U300_OUTPUT_LOW,
  134. U300_OUTPUT_LOW,
  135. },
  136. /* Port 1, pins 0-7 */
  137. {
  138. U300_OUTPUT_LOW,
  139. U300_OUTPUT_LOW,
  140. U300_OUTPUT_LOW,
  141. U300_PULL_UP_INPUT,
  142. U300_FLOATING_INPUT,
  143. U300_OUTPUT_HIGH,
  144. U300_OUTPUT_LOW,
  145. U300_OUTPUT_LOW,
  146. },
  147. /* Port 2, pins 0-7 */
  148. {
  149. U300_FLOATING_INPUT,
  150. U300_FLOATING_INPUT,
  151. U300_FLOATING_INPUT,
  152. U300_FLOATING_INPUT,
  153. U300_OUTPUT_LOW,
  154. U300_PULL_UP_INPUT,
  155. U300_OUTPUT_LOW,
  156. U300_PULL_UP_INPUT,
  157. },
  158. /* Port 3, pins 0-7 */
  159. {
  160. U300_PULL_UP_INPUT,
  161. U300_OUTPUT_LOW,
  162. U300_FLOATING_INPUT,
  163. U300_FLOATING_INPUT,
  164. U300_FLOATING_INPUT,
  165. U300_FLOATING_INPUT,
  166. U300_FLOATING_INPUT,
  167. U300_FLOATING_INPUT,
  168. },
  169. /* Port 4, pins 0-7 */
  170. {
  171. U300_FLOATING_INPUT,
  172. U300_FLOATING_INPUT,
  173. U300_FLOATING_INPUT,
  174. U300_FLOATING_INPUT,
  175. U300_FLOATING_INPUT,
  176. U300_FLOATING_INPUT,
  177. U300_FLOATING_INPUT,
  178. U300_FLOATING_INPUT,
  179. },
  180. /* Port 5, pins 0-7 */
  181. {
  182. U300_FLOATING_INPUT,
  183. U300_FLOATING_INPUT,
  184. U300_FLOATING_INPUT,
  185. U300_FLOATING_INPUT,
  186. U300_FLOATING_INPUT,
  187. U300_FLOATING_INPUT,
  188. U300_FLOATING_INPUT,
  189. U300_FLOATING_INPUT,
  190. },
  191. /* Port 6, pind 0-7 */
  192. {
  193. U300_FLOATING_INPUT,
  194. U300_FLOATING_INPUT,
  195. U300_FLOATING_INPUT,
  196. U300_FLOATING_INPUT,
  197. U300_FLOATING_INPUT,
  198. U300_FLOATING_INPUT,
  199. U300_FLOATING_INPUT,
  200. U300_FLOATING_INPUT,
  201. }
  202. };
  203. /**
  204. * to_u300_gpio() - get the pointer to u300_gpio
  205. * @chip: the gpio chip member of the structure u300_gpio
  206. */
  207. static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
  208. {
  209. return container_of(chip, struct u300_gpio, chip);
  210. }
  211. static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
  212. {
  213. /*
  214. * Map back to global GPIO space and request muxing, the direction
  215. * parameter does not matter for this controller.
  216. */
  217. int gpio = chip->base + offset;
  218. return pinctrl_request_gpio(gpio);
  219. }
  220. static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
  221. {
  222. int gpio = chip->base + offset;
  223. pinctrl_free_gpio(gpio);
  224. }
  225. static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
  226. {
  227. struct u300_gpio *gpio = to_u300_gpio(chip);
  228. return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
  229. }
  230. static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  231. {
  232. struct u300_gpio *gpio = to_u300_gpio(chip);
  233. unsigned long flags;
  234. u32 val;
  235. local_irq_save(flags);
  236. val = readl(U300_PIN_REG(offset, dor));
  237. if (value)
  238. writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
  239. else
  240. writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
  241. local_irq_restore(flags);
  242. }
  243. static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  244. {
  245. struct u300_gpio *gpio = to_u300_gpio(chip);
  246. unsigned long flags;
  247. u32 val;
  248. local_irq_save(flags);
  249. val = readl(U300_PIN_REG(offset, pcr));
  250. /* Mask out this pin, note 2 bits per setting */
  251. val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
  252. writel(val, U300_PIN_REG(offset, pcr));
  253. local_irq_restore(flags);
  254. return 0;
  255. }
  256. static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
  257. int value)
  258. {
  259. struct u300_gpio *gpio = to_u300_gpio(chip);
  260. unsigned long flags;
  261. u32 oldmode;
  262. u32 val;
  263. local_irq_save(flags);
  264. val = readl(U300_PIN_REG(offset, pcr));
  265. /*
  266. * Drive mode must be set by the special mode set function, set
  267. * push/pull mode by default if no mode has been selected.
  268. */
  269. oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
  270. ((offset & 0x07) << 1));
  271. /* mode = 0 means input, else some mode is already set */
  272. if (oldmode == 0) {
  273. val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
  274. ((offset & 0x07) << 1));
  275. val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
  276. << ((offset & 0x07) << 1));
  277. writel(val, U300_PIN_REG(offset, pcr));
  278. }
  279. u300_gpio_set(chip, offset, value);
  280. local_irq_restore(flags);
  281. return 0;
  282. }
  283. static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  284. {
  285. struct u300_gpio *gpio = to_u300_gpio(chip);
  286. int portno = offset >> 3;
  287. struct u300_gpio_port *port = NULL;
  288. struct list_head *p;
  289. int retirq;
  290. bool found = false;
  291. list_for_each(p, &gpio->port_list) {
  292. port = list_entry(p, struct u300_gpio_port, node);
  293. if (port->number == portno) {
  294. found = true;
  295. break;
  296. }
  297. }
  298. if (!found) {
  299. dev_err(gpio->dev, "could not locate port for GPIO %d IRQ\n",
  300. offset);
  301. return -EINVAL;
  302. }
  303. /*
  304. * The local hwirqs on the port are the lower three bits, there
  305. * are exactly 8 IRQs per port since they are 8-bit
  306. */
  307. retirq = irq_find_mapping(port->domain, (offset & 0x7));
  308. dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d from port %d\n",
  309. offset, retirq, port->number);
  310. return retirq;
  311. }
  312. /* Returning -EINVAL means "supported but not available" */
  313. int u300_gpio_config_get(struct gpio_chip *chip,
  314. unsigned offset,
  315. unsigned long *config)
  316. {
  317. struct u300_gpio *gpio = to_u300_gpio(chip);
  318. enum pin_config_param param = (enum pin_config_param) *config;
  319. bool biasmode;
  320. u32 drmode;
  321. /* One bit per pin, clamp to bool range */
  322. biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
  323. /* Mask out the two bits for this pin and shift to bits 0,1 */
  324. drmode = readl(U300_PIN_REG(offset, pcr));
  325. drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
  326. drmode >>= ((offset & 0x07) << 1);
  327. switch (param) {
  328. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  329. *config = 0;
  330. if (biasmode)
  331. return 0;
  332. else
  333. return -EINVAL;
  334. break;
  335. case PIN_CONFIG_BIAS_PULL_UP:
  336. *config = 0;
  337. if (!biasmode)
  338. return 0;
  339. else
  340. return -EINVAL;
  341. break;
  342. case PIN_CONFIG_DRIVE_PUSH_PULL:
  343. *config = 0;
  344. if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
  345. return 0;
  346. else
  347. return -EINVAL;
  348. break;
  349. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  350. *config = 0;
  351. if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
  352. return 0;
  353. else
  354. return -EINVAL;
  355. break;
  356. case PIN_CONFIG_DRIVE_OPEN_SOURCE:
  357. *config = 0;
  358. if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
  359. return 0;
  360. else
  361. return -EINVAL;
  362. break;
  363. default:
  364. break;
  365. }
  366. return -ENOTSUPP;
  367. }
  368. int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
  369. enum pin_config_param param)
  370. {
  371. struct u300_gpio *gpio = to_u300_gpio(chip);
  372. unsigned long flags;
  373. u32 val;
  374. local_irq_save(flags);
  375. switch (param) {
  376. case PIN_CONFIG_BIAS_DISABLE:
  377. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  378. val = readl(U300_PIN_REG(offset, per));
  379. writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
  380. break;
  381. case PIN_CONFIG_BIAS_PULL_UP:
  382. val = readl(U300_PIN_REG(offset, per));
  383. writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
  384. break;
  385. case PIN_CONFIG_DRIVE_PUSH_PULL:
  386. val = readl(U300_PIN_REG(offset, pcr));
  387. val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
  388. << ((offset & 0x07) << 1));
  389. val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
  390. << ((offset & 0x07) << 1));
  391. writel(val, U300_PIN_REG(offset, pcr));
  392. break;
  393. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  394. val = readl(U300_PIN_REG(offset, pcr));
  395. val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
  396. << ((offset & 0x07) << 1));
  397. val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
  398. << ((offset & 0x07) << 1));
  399. writel(val, U300_PIN_REG(offset, pcr));
  400. break;
  401. case PIN_CONFIG_DRIVE_OPEN_SOURCE:
  402. val = readl(U300_PIN_REG(offset, pcr));
  403. val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
  404. << ((offset & 0x07) << 1));
  405. val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
  406. << ((offset & 0x07) << 1));
  407. writel(val, U300_PIN_REG(offset, pcr));
  408. break;
  409. default:
  410. local_irq_restore(flags);
  411. dev_err(gpio->dev, "illegal configuration requested\n");
  412. return -EINVAL;
  413. }
  414. local_irq_restore(flags);
  415. return 0;
  416. }
  417. static struct gpio_chip u300_gpio_chip = {
  418. .label = "u300-gpio-chip",
  419. .owner = THIS_MODULE,
  420. .request = u300_gpio_request,
  421. .free = u300_gpio_free,
  422. .get = u300_gpio_get,
  423. .set = u300_gpio_set,
  424. .direction_input = u300_gpio_direction_input,
  425. .direction_output = u300_gpio_direction_output,
  426. .to_irq = u300_gpio_to_irq,
  427. };
  428. static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
  429. {
  430. u32 val;
  431. val = readl(U300_PIN_REG(offset, icr));
  432. /* Set mode depending on state */
  433. if (u300_gpio_get(&gpio->chip, offset)) {
  434. /* High now, let's trigger on falling edge next then */
  435. writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
  436. dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
  437. offset);
  438. } else {
  439. /* Low now, let's trigger on rising edge next then */
  440. writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
  441. dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
  442. offset);
  443. }
  444. }
  445. static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
  446. {
  447. struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
  448. struct u300_gpio *gpio = port->gpio;
  449. int offset = (port->number << 3) + d->hwirq;
  450. u32 val;
  451. if ((trigger & IRQF_TRIGGER_RISING) &&
  452. (trigger & IRQF_TRIGGER_FALLING)) {
  453. /*
  454. * The GPIO block can only trigger on falling OR rising edges,
  455. * not both. So we need to toggle the mode whenever the pin
  456. * goes from one state to the other with a special state flag
  457. */
  458. dev_dbg(gpio->dev,
  459. "trigger on both rising and falling edge on pin %d\n",
  460. offset);
  461. port->toggle_edge_mode |= U300_PIN_BIT(offset);
  462. u300_toggle_trigger(gpio, offset);
  463. } else if (trigger & IRQF_TRIGGER_RISING) {
  464. dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
  465. offset);
  466. val = readl(U300_PIN_REG(offset, icr));
  467. writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
  468. port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
  469. } else if (trigger & IRQF_TRIGGER_FALLING) {
  470. dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
  471. offset);
  472. val = readl(U300_PIN_REG(offset, icr));
  473. writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
  474. port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
  475. }
  476. return 0;
  477. }
  478. static void u300_gpio_irq_enable(struct irq_data *d)
  479. {
  480. struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
  481. struct u300_gpio *gpio = port->gpio;
  482. int offset = (port->number << 3) + d->hwirq;
  483. u32 val;
  484. unsigned long flags;
  485. dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
  486. d->hwirq, port->name, offset);
  487. local_irq_save(flags);
  488. val = readl(U300_PIN_REG(offset, ien));
  489. writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
  490. local_irq_restore(flags);
  491. }
  492. static void u300_gpio_irq_disable(struct irq_data *d)
  493. {
  494. struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
  495. struct u300_gpio *gpio = port->gpio;
  496. int offset = (port->number << 3) + d->hwirq;
  497. u32 val;
  498. unsigned long flags;
  499. local_irq_save(flags);
  500. val = readl(U300_PIN_REG(offset, ien));
  501. writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
  502. local_irq_restore(flags);
  503. }
  504. static struct irq_chip u300_gpio_irqchip = {
  505. .name = "u300-gpio-irqchip",
  506. .irq_enable = u300_gpio_irq_enable,
  507. .irq_disable = u300_gpio_irq_disable,
  508. .irq_set_type = u300_gpio_irq_type,
  509. };
  510. static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
  511. {
  512. struct u300_gpio_port *port = irq_get_handler_data(irq);
  513. struct u300_gpio *gpio = port->gpio;
  514. int pinoffset = port->number << 3; /* get the right stride */
  515. unsigned long val;
  516. desc->irq_data.chip->irq_ack(&desc->irq_data);
  517. /* Read event register */
  518. val = readl(U300_PIN_REG(pinoffset, iev));
  519. /* Mask relevant bits */
  520. val &= 0xFFU; /* 8 bits per port */
  521. /* ACK IRQ (clear event) */
  522. writel(val, U300_PIN_REG(pinoffset, iev));
  523. /* Call IRQ handler */
  524. if (val != 0) {
  525. int irqoffset;
  526. for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
  527. int pin_irq = irq_find_mapping(port->domain, irqoffset);
  528. int offset = pinoffset + irqoffset;
  529. dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
  530. pin_irq, offset);
  531. generic_handle_irq(pin_irq);
  532. /*
  533. * Triggering IRQ on both rising and falling edge
  534. * needs mockery
  535. */
  536. if (port->toggle_edge_mode & U300_PIN_BIT(offset))
  537. u300_toggle_trigger(gpio, offset);
  538. }
  539. }
  540. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  541. }
  542. static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
  543. int offset,
  544. const struct u300_gpio_confdata *conf)
  545. {
  546. /* Set mode: input or output */
  547. if (conf->output) {
  548. u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
  549. /* Deactivate bias mode for output */
  550. u300_gpio_config_set(&gpio->chip, offset,
  551. PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
  552. /* Set drive mode for output */
  553. u300_gpio_config_set(&gpio->chip, offset,
  554. PIN_CONFIG_DRIVE_PUSH_PULL);
  555. dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
  556. offset, conf->outval);
  557. } else {
  558. u300_gpio_direction_input(&gpio->chip, offset);
  559. /* Always set output low on input pins */
  560. u300_gpio_set(&gpio->chip, offset, 0);
  561. /* Set bias mode for input */
  562. u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
  563. dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
  564. offset, conf->bias_mode);
  565. }
  566. }
  567. static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
  568. {
  569. int i, j;
  570. /* Write default config and values to all pins */
  571. for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
  572. for (j = 0; j < 8; j++) {
  573. const struct u300_gpio_confdata *conf;
  574. int offset = (i*8) + j;
  575. conf = &bs335_gpio_config[i][j];
  576. u300_gpio_init_pin(gpio, offset, conf);
  577. }
  578. }
  579. }
  580. static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
  581. {
  582. struct u300_gpio_port *port;
  583. struct list_head *p, *n;
  584. list_for_each_safe(p, n, &gpio->port_list) {
  585. port = list_entry(p, struct u300_gpio_port, node);
  586. list_del(&port->node);
  587. if (port->domain)
  588. irq_domain_remove(port->domain);
  589. kfree(port);
  590. }
  591. }
  592. /*
  593. * Here we map a GPIO in the local gpio_chip pin space to a pin in
  594. * the local pinctrl pin space. The pin controller used is
  595. * pinctrl-u300.
  596. */
  597. struct coh901_pinpair {
  598. unsigned int offset;
  599. unsigned int pin_base;
  600. };
  601. #define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
  602. static struct coh901_pinpair coh901_pintable[] = {
  603. COH901_PINRANGE(10, 426),
  604. COH901_PINRANGE(11, 180),
  605. COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
  606. COH901_PINRANGE(13, 179),
  607. COH901_PINRANGE(14, 178),
  608. COH901_PINRANGE(16, 194),
  609. COH901_PINRANGE(17, 193),
  610. COH901_PINRANGE(18, 192),
  611. COH901_PINRANGE(19, 191),
  612. COH901_PINRANGE(20, 186),
  613. COH901_PINRANGE(21, 185),
  614. COH901_PINRANGE(22, 184),
  615. COH901_PINRANGE(23, 183),
  616. COH901_PINRANGE(24, 182),
  617. COH901_PINRANGE(25, 181),
  618. };
  619. static int __init u300_gpio_probe(struct platform_device *pdev)
  620. {
  621. struct u300_gpio *gpio;
  622. struct resource *memres;
  623. int err = 0;
  624. int portno;
  625. u32 val;
  626. u32 ifr;
  627. int i;
  628. gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
  629. if (gpio == NULL)
  630. return -ENOMEM;
  631. gpio->chip = u300_gpio_chip;
  632. gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
  633. gpio->chip.dev = &pdev->dev;
  634. gpio->chip.base = 0;
  635. gpio->dev = &pdev->dev;
  636. memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  637. gpio->base = devm_ioremap_resource(&pdev->dev, memres);
  638. if (IS_ERR(gpio->base))
  639. return PTR_ERR(gpio->base);
  640. gpio->clk = devm_clk_get(gpio->dev, NULL);
  641. if (IS_ERR(gpio->clk)) {
  642. err = PTR_ERR(gpio->clk);
  643. dev_err(gpio->dev, "could not get GPIO clock\n");
  644. return err;
  645. }
  646. err = clk_prepare_enable(gpio->clk);
  647. if (err) {
  648. dev_err(gpio->dev, "could not enable GPIO clock\n");
  649. return err;
  650. }
  651. dev_info(gpio->dev,
  652. "initializing GPIO Controller COH 901 571/3\n");
  653. gpio->stride = U300_GPIO_PORT_STRIDE;
  654. gpio->pcr = U300_GPIO_PXPCR;
  655. gpio->dor = U300_GPIO_PXPDOR;
  656. gpio->dir = U300_GPIO_PXPDIR;
  657. gpio->per = U300_GPIO_PXPER;
  658. gpio->icr = U300_GPIO_PXICR;
  659. gpio->ien = U300_GPIO_PXIEN;
  660. gpio->iev = U300_GPIO_PXIEV;
  661. ifr = U300_GPIO_PXIFR;
  662. val = readl(gpio->base + U300_GPIO_CR);
  663. dev_info(gpio->dev, "COH901571/3 block version: %d, " \
  664. "number of cores: %d totalling %d pins\n",
  665. ((val & 0x000001FC) >> 2),
  666. ((val & 0x0000FE00) >> 9),
  667. ((val & 0x0000FE00) >> 9) * 8);
  668. writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
  669. gpio->base + U300_GPIO_CR);
  670. u300_gpio_init_coh901571(gpio);
  671. /* Add each port with its IRQ separately */
  672. INIT_LIST_HEAD(&gpio->port_list);
  673. for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
  674. struct u300_gpio_port *port =
  675. kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
  676. if (!port) {
  677. dev_err(gpio->dev, "out of memory\n");
  678. err = -ENOMEM;
  679. goto err_no_port;
  680. }
  681. snprintf(port->name, 8, "gpio%d", portno);
  682. port->number = portno;
  683. port->gpio = gpio;
  684. port->irq = platform_get_irq(pdev, portno);
  685. dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq,
  686. port->name);
  687. port->domain = irq_domain_add_linear(pdev->dev.of_node,
  688. U300_GPIO_PINS_PER_PORT,
  689. &irq_domain_simple_ops,
  690. port);
  691. if (!port->domain) {
  692. err = -ENOMEM;
  693. goto err_no_domain;
  694. }
  695. irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
  696. irq_set_handler_data(port->irq, port);
  697. /* For each GPIO pin set the unique IRQ handler */
  698. for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
  699. int irqno = irq_create_mapping(port->domain, i);
  700. dev_dbg(gpio->dev, "GPIO%d on port %s gets IRQ %d\n",
  701. gpio->chip.base + (port->number << 3) + i,
  702. port->name, irqno);
  703. irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
  704. handle_simple_irq);
  705. set_irq_flags(irqno, IRQF_VALID);
  706. irq_set_chip_data(irqno, port);
  707. }
  708. /* Turns off irq force (test register) for this port */
  709. writel(0x0, gpio->base + portno * gpio->stride + ifr);
  710. list_add_tail(&port->node, &gpio->port_list);
  711. }
  712. dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
  713. #ifdef CONFIG_OF_GPIO
  714. gpio->chip.of_node = pdev->dev.of_node;
  715. #endif
  716. err = gpiochip_add(&gpio->chip);
  717. if (err) {
  718. dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
  719. goto err_no_chip;
  720. }
  721. /*
  722. * Add pinctrl pin ranges, the pin controller must be registered
  723. * at this point
  724. */
  725. for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
  726. struct coh901_pinpair *p = &coh901_pintable[i];
  727. err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
  728. p->offset, p->pin_base, 1);
  729. if (err)
  730. goto err_no_range;
  731. }
  732. platform_set_drvdata(pdev, gpio);
  733. return 0;
  734. err_no_range:
  735. if (gpiochip_remove(&gpio->chip))
  736. dev_err(&pdev->dev, "failed to remove gpio chip\n");
  737. err_no_chip:
  738. err_no_domain:
  739. err_no_port:
  740. u300_gpio_free_ports(gpio);
  741. clk_disable_unprepare(gpio->clk);
  742. dev_err(&pdev->dev, "module ERROR:%d\n", err);
  743. return err;
  744. }
  745. static int __exit u300_gpio_remove(struct platform_device *pdev)
  746. {
  747. struct u300_gpio *gpio = platform_get_drvdata(pdev);
  748. int err;
  749. /* Turn off the GPIO block */
  750. writel(0x00000000U, gpio->base + U300_GPIO_CR);
  751. err = gpiochip_remove(&gpio->chip);
  752. if (err < 0) {
  753. dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
  754. return err;
  755. }
  756. u300_gpio_free_ports(gpio);
  757. clk_disable_unprepare(gpio->clk);
  758. return 0;
  759. }
  760. static const struct of_device_id u300_gpio_match[] = {
  761. { .compatible = "stericsson,gpio-coh901" },
  762. {},
  763. };
  764. static struct platform_driver u300_gpio_driver = {
  765. .driver = {
  766. .name = "u300-gpio",
  767. .of_match_table = u300_gpio_match,
  768. },
  769. .remove = __exit_p(u300_gpio_remove),
  770. };
  771. static int __init u300_gpio_init(void)
  772. {
  773. return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
  774. }
  775. static void __exit u300_gpio_exit(void)
  776. {
  777. platform_driver_unregister(&u300_gpio_driver);
  778. }
  779. arch_initcall(u300_gpio_init);
  780. module_exit(u300_gpio_exit);
  781. MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
  782. MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
  783. MODULE_LICENSE("GPL");