mvebu-devbus.c 6.4 KB

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  1. /*
  2. * Marvell EBU SoC Device Bus Controller
  3. * (memory controller for NOR/NAND/SRAM/FPGA devices)
  4. *
  5. * Copyright (C) 2013 Marvell
  6. *
  7. * This program is free software: you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. *
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/slab.h>
  23. #include <linux/err.h>
  24. #include <linux/io.h>
  25. #include <linux/clk.h>
  26. #include <linux/mbus.h>
  27. #include <linux/of_platform.h>
  28. #include <linux/of_address.h>
  29. #include <linux/platform_device.h>
  30. /* Register definitions */
  31. #define DEV_WIDTH_BIT 30
  32. #define BADR_SKEW_BIT 28
  33. #define RD_HOLD_BIT 23
  34. #define ACC_NEXT_BIT 17
  35. #define RD_SETUP_BIT 12
  36. #define ACC_FIRST_BIT 6
  37. #define SYNC_ENABLE_BIT 24
  38. #define WR_HIGH_BIT 16
  39. #define WR_LOW_BIT 8
  40. #define READ_PARAM_OFFSET 0x0
  41. #define WRITE_PARAM_OFFSET 0x4
  42. struct devbus_read_params {
  43. u32 bus_width;
  44. u32 badr_skew;
  45. u32 turn_off;
  46. u32 acc_first;
  47. u32 acc_next;
  48. u32 rd_setup;
  49. u32 rd_hold;
  50. };
  51. struct devbus_write_params {
  52. u32 sync_enable;
  53. u32 wr_high;
  54. u32 wr_low;
  55. u32 ale_wr;
  56. };
  57. struct devbus {
  58. struct device *dev;
  59. void __iomem *base;
  60. unsigned long tick_ps;
  61. };
  62. static int get_timing_param_ps(struct devbus *devbus,
  63. struct device_node *node,
  64. const char *name,
  65. u32 *ticks)
  66. {
  67. u32 time_ps;
  68. int err;
  69. err = of_property_read_u32(node, name, &time_ps);
  70. if (err < 0) {
  71. dev_err(devbus->dev, "%s has no '%s' property\n",
  72. name, node->full_name);
  73. return err;
  74. }
  75. *ticks = (time_ps + devbus->tick_ps - 1) / devbus->tick_ps;
  76. dev_dbg(devbus->dev, "%s: %u ps -> 0x%x\n",
  77. name, time_ps, *ticks);
  78. return 0;
  79. }
  80. static int devbus_set_timing_params(struct devbus *devbus,
  81. struct device_node *node)
  82. {
  83. struct devbus_read_params r;
  84. struct devbus_write_params w;
  85. u32 value;
  86. int err;
  87. dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
  88. devbus->tick_ps);
  89. /* Get read timings */
  90. err = of_property_read_u32(node, "devbus,bus-width", &r.bus_width);
  91. if (err < 0) {
  92. dev_err(devbus->dev,
  93. "%s has no 'devbus,bus-width' property\n",
  94. node->full_name);
  95. return err;
  96. }
  97. /* Convert bit width to byte width */
  98. r.bus_width /= 8;
  99. err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
  100. &r.badr_skew);
  101. if (err < 0)
  102. return err;
  103. err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
  104. &r.turn_off);
  105. if (err < 0)
  106. return err;
  107. err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
  108. &r.acc_first);
  109. if (err < 0)
  110. return err;
  111. err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
  112. &r.acc_next);
  113. if (err < 0)
  114. return err;
  115. err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
  116. &r.rd_setup);
  117. if (err < 0)
  118. return err;
  119. err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
  120. &r.rd_hold);
  121. if (err < 0)
  122. return err;
  123. /* Get write timings */
  124. err = of_property_read_u32(node, "devbus,sync-enable",
  125. &w.sync_enable);
  126. if (err < 0) {
  127. dev_err(devbus->dev,
  128. "%s has no 'devbus,sync-enable' property\n",
  129. node->full_name);
  130. return err;
  131. }
  132. err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
  133. &w.ale_wr);
  134. if (err < 0)
  135. return err;
  136. err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
  137. &w.wr_low);
  138. if (err < 0)
  139. return err;
  140. err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
  141. &w.wr_high);
  142. if (err < 0)
  143. return err;
  144. /* Set read timings */
  145. value = r.bus_width << DEV_WIDTH_BIT |
  146. r.badr_skew << BADR_SKEW_BIT |
  147. r.rd_hold << RD_HOLD_BIT |
  148. r.acc_next << ACC_NEXT_BIT |
  149. r.rd_setup << RD_SETUP_BIT |
  150. r.acc_first << ACC_FIRST_BIT |
  151. r.turn_off;
  152. dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
  153. devbus->base + READ_PARAM_OFFSET,
  154. value);
  155. writel(value, devbus->base + READ_PARAM_OFFSET);
  156. /* Set write timings */
  157. value = w.sync_enable << SYNC_ENABLE_BIT |
  158. w.wr_low << WR_LOW_BIT |
  159. w.wr_high << WR_HIGH_BIT |
  160. w.ale_wr;
  161. dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
  162. devbus->base + WRITE_PARAM_OFFSET,
  163. value);
  164. writel(value, devbus->base + WRITE_PARAM_OFFSET);
  165. return 0;
  166. }
  167. static int mvebu_devbus_probe(struct platform_device *pdev)
  168. {
  169. struct device *dev = &pdev->dev;
  170. struct device_node *node = pdev->dev.of_node;
  171. struct devbus *devbus;
  172. struct resource *res;
  173. struct clk *clk;
  174. unsigned long rate;
  175. int err;
  176. devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
  177. if (!devbus)
  178. return -ENOMEM;
  179. devbus->dev = dev;
  180. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  181. devbus->base = devm_ioremap_resource(&pdev->dev, res);
  182. if (IS_ERR(devbus->base))
  183. return PTR_ERR(devbus->base);
  184. clk = devm_clk_get(&pdev->dev, NULL);
  185. if (IS_ERR(clk))
  186. return PTR_ERR(clk);
  187. clk_prepare_enable(clk);
  188. /*
  189. * Obtain clock period in picoseconds,
  190. * we need this in order to convert timing
  191. * parameters from cycles to picoseconds.
  192. */
  193. rate = clk_get_rate(clk) / 1000;
  194. devbus->tick_ps = 1000000000 / rate;
  195. /* Read the device tree node and set the new timing parameters */
  196. err = devbus_set_timing_params(devbus, node);
  197. if (err < 0)
  198. return err;
  199. /*
  200. * We need to create a child device explicitly from here to
  201. * guarantee that the child will be probed after the timing
  202. * parameters for the bus are written.
  203. */
  204. err = of_platform_populate(node, NULL, NULL, dev);
  205. if (err < 0)
  206. return err;
  207. return 0;
  208. }
  209. static const struct of_device_id mvebu_devbus_of_match[] = {
  210. { .compatible = "marvell,mvebu-devbus" },
  211. {},
  212. };
  213. MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);
  214. static struct platform_driver mvebu_devbus_driver = {
  215. .probe = mvebu_devbus_probe,
  216. .driver = {
  217. .name = "mvebu-devbus",
  218. .owner = THIS_MODULE,
  219. .of_match_table = mvebu_devbus_of_match,
  220. },
  221. };
  222. static int __init mvebu_devbus_init(void)
  223. {
  224. return platform_driver_register(&mvebu_devbus_driver);
  225. }
  226. module_init(mvebu_devbus_init);
  227. MODULE_LICENSE("GPL v2");
  228. MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
  229. MODULE_DESCRIPTION("Marvell EBU SoC Device Bus controller");