atmel-isi.c 27 KB

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  1. /*
  2. * Copyright (c) 2011 Atmel Corporation
  3. * Josh Wu, <josh.wu@atmel.com>
  4. *
  5. * Based on previous work by Lars Haring, <lars.haring@atmel.com>
  6. * and Sedji Gaouaou
  7. * Based on the bttv driver for Bt848 with respective copyright holders
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/completion.h>
  15. #include <linux/delay.h>
  16. #include <linux/fs.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <media/atmel-isi.h>
  24. #include <media/soc_camera.h>
  25. #include <media/soc_mediabus.h>
  26. #include <media/videobuf2-dma-contig.h>
  27. #define MAX_BUFFER_NUM 32
  28. #define MAX_SUPPORT_WIDTH 2048
  29. #define MAX_SUPPORT_HEIGHT 2048
  30. #define VID_LIMIT_BYTES (16 * 1024 * 1024)
  31. #define MIN_FRAME_RATE 15
  32. #define FRAME_INTERVAL_MILLI_SEC (1000 / MIN_FRAME_RATE)
  33. /* ISI states */
  34. enum {
  35. ISI_STATE_IDLE = 0,
  36. ISI_STATE_READY,
  37. ISI_STATE_WAIT_SOF,
  38. };
  39. /* Frame buffer descriptor */
  40. struct fbd {
  41. /* Physical address of the frame buffer */
  42. u32 fb_address;
  43. /* DMA Control Register(only in HISI2) */
  44. u32 dma_ctrl;
  45. /* Physical address of the next fbd */
  46. u32 next_fbd_address;
  47. };
  48. static void set_dma_ctrl(struct fbd *fb_desc, u32 ctrl)
  49. {
  50. fb_desc->dma_ctrl = ctrl;
  51. }
  52. struct isi_dma_desc {
  53. struct list_head list;
  54. struct fbd *p_fbd;
  55. u32 fbd_phys;
  56. };
  57. /* Frame buffer data */
  58. struct frame_buffer {
  59. struct vb2_buffer vb;
  60. struct isi_dma_desc *p_dma_desc;
  61. struct list_head list;
  62. };
  63. struct atmel_isi {
  64. /* Protects the access of variables shared with the ISR */
  65. spinlock_t lock;
  66. void __iomem *regs;
  67. int sequence;
  68. /* State of the ISI module in capturing mode */
  69. int state;
  70. /* Wait queue for waiting for SOF */
  71. wait_queue_head_t vsync_wq;
  72. struct vb2_alloc_ctx *alloc_ctx;
  73. /* Allocate descriptors for dma buffer use */
  74. struct fbd *p_fb_descriptors;
  75. u32 fb_descriptors_phys;
  76. struct list_head dma_desc_head;
  77. struct isi_dma_desc dma_desc[MAX_BUFFER_NUM];
  78. struct completion complete;
  79. /* ISI peripherial clock */
  80. struct clk *pclk;
  81. /* ISI_MCK, feed to camera sensor to generate pixel clock */
  82. struct clk *mck;
  83. unsigned int irq;
  84. struct isi_platform_data *pdata;
  85. u16 width_flags; /* max 12 bits */
  86. struct list_head video_buffer_list;
  87. struct frame_buffer *active;
  88. struct soc_camera_host soc_host;
  89. };
  90. static void isi_writel(struct atmel_isi *isi, u32 reg, u32 val)
  91. {
  92. writel(val, isi->regs + reg);
  93. }
  94. static u32 isi_readl(struct atmel_isi *isi, u32 reg)
  95. {
  96. return readl(isi->regs + reg);
  97. }
  98. static int configure_geometry(struct atmel_isi *isi, u32 width,
  99. u32 height, enum v4l2_mbus_pixelcode code)
  100. {
  101. u32 cfg2, cr;
  102. switch (code) {
  103. /* YUV, including grey */
  104. case V4L2_MBUS_FMT_Y8_1X8:
  105. cr = ISI_CFG2_GRAYSCALE;
  106. break;
  107. case V4L2_MBUS_FMT_UYVY8_2X8:
  108. cr = ISI_CFG2_YCC_SWAP_MODE_3;
  109. break;
  110. case V4L2_MBUS_FMT_VYUY8_2X8:
  111. cr = ISI_CFG2_YCC_SWAP_MODE_2;
  112. break;
  113. case V4L2_MBUS_FMT_YUYV8_2X8:
  114. cr = ISI_CFG2_YCC_SWAP_MODE_1;
  115. break;
  116. case V4L2_MBUS_FMT_YVYU8_2X8:
  117. cr = ISI_CFG2_YCC_SWAP_DEFAULT;
  118. break;
  119. /* RGB, TODO */
  120. default:
  121. return -EINVAL;
  122. }
  123. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  124. cfg2 = isi_readl(isi, ISI_CFG2);
  125. cfg2 |= cr;
  126. /* Set width */
  127. cfg2 &= ~(ISI_CFG2_IM_HSIZE_MASK);
  128. cfg2 |= ((width - 1) << ISI_CFG2_IM_HSIZE_OFFSET) &
  129. ISI_CFG2_IM_HSIZE_MASK;
  130. /* Set height */
  131. cfg2 &= ~(ISI_CFG2_IM_VSIZE_MASK);
  132. cfg2 |= ((height - 1) << ISI_CFG2_IM_VSIZE_OFFSET)
  133. & ISI_CFG2_IM_VSIZE_MASK;
  134. isi_writel(isi, ISI_CFG2, cfg2);
  135. return 0;
  136. }
  137. static irqreturn_t atmel_isi_handle_streaming(struct atmel_isi *isi)
  138. {
  139. if (isi->active) {
  140. struct vb2_buffer *vb = &isi->active->vb;
  141. struct frame_buffer *buf = isi->active;
  142. list_del_init(&buf->list);
  143. v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
  144. vb->v4l2_buf.sequence = isi->sequence++;
  145. vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
  146. }
  147. if (list_empty(&isi->video_buffer_list)) {
  148. isi->active = NULL;
  149. } else {
  150. /* start next dma frame. */
  151. isi->active = list_entry(isi->video_buffer_list.next,
  152. struct frame_buffer, list);
  153. isi_writel(isi, ISI_DMA_C_DSCR,
  154. isi->active->p_dma_desc->fbd_phys);
  155. isi_writel(isi, ISI_DMA_C_CTRL,
  156. ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
  157. isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
  158. }
  159. return IRQ_HANDLED;
  160. }
  161. /* ISI interrupt service routine */
  162. static irqreturn_t isi_interrupt(int irq, void *dev_id)
  163. {
  164. struct atmel_isi *isi = dev_id;
  165. u32 status, mask, pending;
  166. irqreturn_t ret = IRQ_NONE;
  167. spin_lock(&isi->lock);
  168. status = isi_readl(isi, ISI_STATUS);
  169. mask = isi_readl(isi, ISI_INTMASK);
  170. pending = status & mask;
  171. if (pending & ISI_CTRL_SRST) {
  172. complete(&isi->complete);
  173. isi_writel(isi, ISI_INTDIS, ISI_CTRL_SRST);
  174. ret = IRQ_HANDLED;
  175. } else if (pending & ISI_CTRL_DIS) {
  176. complete(&isi->complete);
  177. isi_writel(isi, ISI_INTDIS, ISI_CTRL_DIS);
  178. ret = IRQ_HANDLED;
  179. } else {
  180. if ((pending & ISI_SR_VSYNC) &&
  181. (isi->state == ISI_STATE_IDLE)) {
  182. isi->state = ISI_STATE_READY;
  183. wake_up_interruptible(&isi->vsync_wq);
  184. ret = IRQ_HANDLED;
  185. }
  186. if (likely(pending & ISI_SR_CXFR_DONE))
  187. ret = atmel_isi_handle_streaming(isi);
  188. }
  189. spin_unlock(&isi->lock);
  190. return ret;
  191. }
  192. #define WAIT_ISI_RESET 1
  193. #define WAIT_ISI_DISABLE 0
  194. static int atmel_isi_wait_status(struct atmel_isi *isi, int wait_reset)
  195. {
  196. unsigned long timeout;
  197. /*
  198. * The reset or disable will only succeed if we have a
  199. * pixel clock from the camera.
  200. */
  201. init_completion(&isi->complete);
  202. if (wait_reset) {
  203. isi_writel(isi, ISI_INTEN, ISI_CTRL_SRST);
  204. isi_writel(isi, ISI_CTRL, ISI_CTRL_SRST);
  205. } else {
  206. isi_writel(isi, ISI_INTEN, ISI_CTRL_DIS);
  207. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  208. }
  209. timeout = wait_for_completion_timeout(&isi->complete,
  210. msecs_to_jiffies(100));
  211. if (timeout == 0)
  212. return -ETIMEDOUT;
  213. return 0;
  214. }
  215. /* ------------------------------------------------------------------
  216. Videobuf operations
  217. ------------------------------------------------------------------*/
  218. static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
  219. unsigned int *nbuffers, unsigned int *nplanes,
  220. unsigned int sizes[], void *alloc_ctxs[])
  221. {
  222. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  223. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  224. struct atmel_isi *isi = ici->priv;
  225. unsigned long size;
  226. int ret;
  227. /* Reset ISI */
  228. ret = atmel_isi_wait_status(isi, WAIT_ISI_RESET);
  229. if (ret < 0) {
  230. dev_err(icd->parent, "Reset ISI timed out\n");
  231. return ret;
  232. }
  233. /* Disable all interrupts */
  234. isi_writel(isi, ISI_INTDIS, ~0UL);
  235. size = icd->sizeimage;
  236. if (!*nbuffers || *nbuffers > MAX_BUFFER_NUM)
  237. *nbuffers = MAX_BUFFER_NUM;
  238. if (size * *nbuffers > VID_LIMIT_BYTES)
  239. *nbuffers = VID_LIMIT_BYTES / size;
  240. *nplanes = 1;
  241. sizes[0] = size;
  242. alloc_ctxs[0] = isi->alloc_ctx;
  243. isi->sequence = 0;
  244. isi->active = NULL;
  245. dev_dbg(icd->parent, "%s, count=%d, size=%ld\n", __func__,
  246. *nbuffers, size);
  247. return 0;
  248. }
  249. static int buffer_init(struct vb2_buffer *vb)
  250. {
  251. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  252. buf->p_dma_desc = NULL;
  253. INIT_LIST_HEAD(&buf->list);
  254. return 0;
  255. }
  256. static int buffer_prepare(struct vb2_buffer *vb)
  257. {
  258. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  259. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  260. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  261. struct atmel_isi *isi = ici->priv;
  262. unsigned long size;
  263. struct isi_dma_desc *desc;
  264. size = icd->sizeimage;
  265. if (vb2_plane_size(vb, 0) < size) {
  266. dev_err(icd->parent, "%s data will not fit into plane (%lu < %lu)\n",
  267. __func__, vb2_plane_size(vb, 0), size);
  268. return -EINVAL;
  269. }
  270. vb2_set_plane_payload(&buf->vb, 0, size);
  271. if (!buf->p_dma_desc) {
  272. if (list_empty(&isi->dma_desc_head)) {
  273. dev_err(icd->parent, "Not enough dma descriptors.\n");
  274. return -EINVAL;
  275. } else {
  276. /* Get an available descriptor */
  277. desc = list_entry(isi->dma_desc_head.next,
  278. struct isi_dma_desc, list);
  279. /* Delete the descriptor since now it is used */
  280. list_del_init(&desc->list);
  281. /* Initialize the dma descriptor */
  282. desc->p_fbd->fb_address =
  283. vb2_dma_contig_plane_dma_addr(vb, 0);
  284. desc->p_fbd->next_fbd_address = 0;
  285. set_dma_ctrl(desc->p_fbd, ISI_DMA_CTRL_WB);
  286. buf->p_dma_desc = desc;
  287. }
  288. }
  289. return 0;
  290. }
  291. static void buffer_cleanup(struct vb2_buffer *vb)
  292. {
  293. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  294. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  295. struct atmel_isi *isi = ici->priv;
  296. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  297. /* This descriptor is available now and we add to head list */
  298. if (buf->p_dma_desc)
  299. list_add(&buf->p_dma_desc->list, &isi->dma_desc_head);
  300. }
  301. static void start_dma(struct atmel_isi *isi, struct frame_buffer *buffer)
  302. {
  303. u32 ctrl, cfg1;
  304. cfg1 = isi_readl(isi, ISI_CFG1);
  305. /* Enable irq: cxfr for the codec path, pxfr for the preview path */
  306. isi_writel(isi, ISI_INTEN,
  307. ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
  308. /* Check if already in a frame */
  309. if (isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) {
  310. dev_err(isi->soc_host.icd->parent, "Already in frame handling.\n");
  311. return;
  312. }
  313. isi_writel(isi, ISI_DMA_C_DSCR, buffer->p_dma_desc->fbd_phys);
  314. isi_writel(isi, ISI_DMA_C_CTRL, ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
  315. isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
  316. /* Enable linked list */
  317. cfg1 |= isi->pdata->frate | ISI_CFG1_DISCR;
  318. /* Enable codec path and ISI */
  319. ctrl = ISI_CTRL_CDC | ISI_CTRL_EN;
  320. isi_writel(isi, ISI_CTRL, ctrl);
  321. isi_writel(isi, ISI_CFG1, cfg1);
  322. }
  323. static void buffer_queue(struct vb2_buffer *vb)
  324. {
  325. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  326. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  327. struct atmel_isi *isi = ici->priv;
  328. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  329. unsigned long flags = 0;
  330. spin_lock_irqsave(&isi->lock, flags);
  331. list_add_tail(&buf->list, &isi->video_buffer_list);
  332. if (isi->active == NULL) {
  333. isi->active = buf;
  334. if (vb2_is_streaming(vb->vb2_queue))
  335. start_dma(isi, buf);
  336. }
  337. spin_unlock_irqrestore(&isi->lock, flags);
  338. }
  339. static int start_streaming(struct vb2_queue *vq, unsigned int count)
  340. {
  341. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  342. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  343. struct atmel_isi *isi = ici->priv;
  344. u32 sr = 0;
  345. int ret;
  346. spin_lock_irq(&isi->lock);
  347. isi->state = ISI_STATE_IDLE;
  348. /* Clear any pending SOF interrupt */
  349. sr = isi_readl(isi, ISI_STATUS);
  350. /* Enable VSYNC interrupt for SOF */
  351. isi_writel(isi, ISI_INTEN, ISI_SR_VSYNC);
  352. isi_writel(isi, ISI_CTRL, ISI_CTRL_EN);
  353. spin_unlock_irq(&isi->lock);
  354. dev_dbg(icd->parent, "Waiting for SOF\n");
  355. ret = wait_event_interruptible(isi->vsync_wq,
  356. isi->state != ISI_STATE_IDLE);
  357. if (ret)
  358. goto err;
  359. if (isi->state != ISI_STATE_READY) {
  360. ret = -EIO;
  361. goto err;
  362. }
  363. spin_lock_irq(&isi->lock);
  364. isi->state = ISI_STATE_WAIT_SOF;
  365. isi_writel(isi, ISI_INTDIS, ISI_SR_VSYNC);
  366. if (count)
  367. start_dma(isi, isi->active);
  368. spin_unlock_irq(&isi->lock);
  369. return 0;
  370. err:
  371. isi->active = NULL;
  372. isi->sequence = 0;
  373. INIT_LIST_HEAD(&isi->video_buffer_list);
  374. return ret;
  375. }
  376. /* abort streaming and wait for last buffer */
  377. static int stop_streaming(struct vb2_queue *vq)
  378. {
  379. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  380. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  381. struct atmel_isi *isi = ici->priv;
  382. struct frame_buffer *buf, *node;
  383. int ret = 0;
  384. unsigned long timeout;
  385. spin_lock_irq(&isi->lock);
  386. isi->active = NULL;
  387. /* Release all active buffers */
  388. list_for_each_entry_safe(buf, node, &isi->video_buffer_list, list) {
  389. list_del_init(&buf->list);
  390. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  391. }
  392. spin_unlock_irq(&isi->lock);
  393. timeout = jiffies + FRAME_INTERVAL_MILLI_SEC * HZ;
  394. /* Wait until the end of the current frame. */
  395. while ((isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) &&
  396. time_before(jiffies, timeout))
  397. msleep(1);
  398. if (time_after(jiffies, timeout)) {
  399. dev_err(icd->parent,
  400. "Timeout waiting for finishing codec request\n");
  401. return -ETIMEDOUT;
  402. }
  403. /* Disable interrupts */
  404. isi_writel(isi, ISI_INTDIS,
  405. ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
  406. /* Disable ISI and wait for it is done */
  407. ret = atmel_isi_wait_status(isi, WAIT_ISI_DISABLE);
  408. if (ret < 0)
  409. dev_err(icd->parent, "Disable ISI timed out\n");
  410. return ret;
  411. }
  412. static struct vb2_ops isi_video_qops = {
  413. .queue_setup = queue_setup,
  414. .buf_init = buffer_init,
  415. .buf_prepare = buffer_prepare,
  416. .buf_cleanup = buffer_cleanup,
  417. .buf_queue = buffer_queue,
  418. .start_streaming = start_streaming,
  419. .stop_streaming = stop_streaming,
  420. .wait_prepare = soc_camera_unlock,
  421. .wait_finish = soc_camera_lock,
  422. };
  423. /* ------------------------------------------------------------------
  424. SOC camera operations for the device
  425. ------------------------------------------------------------------*/
  426. static int isi_camera_init_videobuf(struct vb2_queue *q,
  427. struct soc_camera_device *icd)
  428. {
  429. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  430. q->io_modes = VB2_MMAP;
  431. q->drv_priv = icd;
  432. q->buf_struct_size = sizeof(struct frame_buffer);
  433. q->ops = &isi_video_qops;
  434. q->mem_ops = &vb2_dma_contig_memops;
  435. q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  436. return vb2_queue_init(q);
  437. }
  438. static int isi_camera_set_fmt(struct soc_camera_device *icd,
  439. struct v4l2_format *f)
  440. {
  441. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  442. struct atmel_isi *isi = ici->priv;
  443. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  444. const struct soc_camera_format_xlate *xlate;
  445. struct v4l2_pix_format *pix = &f->fmt.pix;
  446. struct v4l2_mbus_framefmt mf;
  447. int ret;
  448. xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
  449. if (!xlate) {
  450. dev_warn(icd->parent, "Format %x not found\n",
  451. pix->pixelformat);
  452. return -EINVAL;
  453. }
  454. dev_dbg(icd->parent, "Plan to set format %dx%d\n",
  455. pix->width, pix->height);
  456. mf.width = pix->width;
  457. mf.height = pix->height;
  458. mf.field = pix->field;
  459. mf.colorspace = pix->colorspace;
  460. mf.code = xlate->code;
  461. ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
  462. if (ret < 0)
  463. return ret;
  464. if (mf.code != xlate->code)
  465. return -EINVAL;
  466. ret = configure_geometry(isi, pix->width, pix->height, xlate->code);
  467. if (ret < 0)
  468. return ret;
  469. pix->width = mf.width;
  470. pix->height = mf.height;
  471. pix->field = mf.field;
  472. pix->colorspace = mf.colorspace;
  473. icd->current_fmt = xlate;
  474. dev_dbg(icd->parent, "Finally set format %dx%d\n",
  475. pix->width, pix->height);
  476. return ret;
  477. }
  478. static int isi_camera_try_fmt(struct soc_camera_device *icd,
  479. struct v4l2_format *f)
  480. {
  481. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  482. const struct soc_camera_format_xlate *xlate;
  483. struct v4l2_pix_format *pix = &f->fmt.pix;
  484. struct v4l2_mbus_framefmt mf;
  485. u32 pixfmt = pix->pixelformat;
  486. int ret;
  487. xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
  488. if (pixfmt && !xlate) {
  489. dev_warn(icd->parent, "Format %x not found\n", pixfmt);
  490. return -EINVAL;
  491. }
  492. /* limit to Atmel ISI hardware capabilities */
  493. if (pix->height > MAX_SUPPORT_HEIGHT)
  494. pix->height = MAX_SUPPORT_HEIGHT;
  495. if (pix->width > MAX_SUPPORT_WIDTH)
  496. pix->width = MAX_SUPPORT_WIDTH;
  497. /* limit to sensor capabilities */
  498. mf.width = pix->width;
  499. mf.height = pix->height;
  500. mf.field = pix->field;
  501. mf.colorspace = pix->colorspace;
  502. mf.code = xlate->code;
  503. ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
  504. if (ret < 0)
  505. return ret;
  506. pix->width = mf.width;
  507. pix->height = mf.height;
  508. pix->colorspace = mf.colorspace;
  509. switch (mf.field) {
  510. case V4L2_FIELD_ANY:
  511. pix->field = V4L2_FIELD_NONE;
  512. break;
  513. case V4L2_FIELD_NONE:
  514. break;
  515. default:
  516. dev_err(icd->parent, "Field type %d unsupported.\n",
  517. mf.field);
  518. ret = -EINVAL;
  519. }
  520. return ret;
  521. }
  522. static const struct soc_mbus_pixelfmt isi_camera_formats[] = {
  523. {
  524. .fourcc = V4L2_PIX_FMT_YUYV,
  525. .name = "Packed YUV422 16 bit",
  526. .bits_per_sample = 8,
  527. .packing = SOC_MBUS_PACKING_2X8_PADHI,
  528. .order = SOC_MBUS_ORDER_LE,
  529. .layout = SOC_MBUS_LAYOUT_PACKED,
  530. },
  531. };
  532. /* This will be corrected as we get more formats */
  533. static bool isi_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
  534. {
  535. return fmt->packing == SOC_MBUS_PACKING_NONE ||
  536. (fmt->bits_per_sample == 8 &&
  537. fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
  538. (fmt->bits_per_sample > 8 &&
  539. fmt->packing == SOC_MBUS_PACKING_EXTEND16);
  540. }
  541. #define ISI_BUS_PARAM (V4L2_MBUS_MASTER | \
  542. V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
  543. V4L2_MBUS_HSYNC_ACTIVE_LOW | \
  544. V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
  545. V4L2_MBUS_VSYNC_ACTIVE_LOW | \
  546. V4L2_MBUS_PCLK_SAMPLE_RISING | \
  547. V4L2_MBUS_PCLK_SAMPLE_FALLING | \
  548. V4L2_MBUS_DATA_ACTIVE_HIGH)
  549. static int isi_camera_try_bus_param(struct soc_camera_device *icd,
  550. unsigned char buswidth)
  551. {
  552. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  553. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  554. struct atmel_isi *isi = ici->priv;
  555. struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
  556. unsigned long common_flags;
  557. int ret;
  558. ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
  559. if (!ret) {
  560. common_flags = soc_mbus_config_compatible(&cfg,
  561. ISI_BUS_PARAM);
  562. if (!common_flags) {
  563. dev_warn(icd->parent,
  564. "Flags incompatible: camera 0x%x, host 0x%x\n",
  565. cfg.flags, ISI_BUS_PARAM);
  566. return -EINVAL;
  567. }
  568. } else if (ret != -ENOIOCTLCMD) {
  569. return ret;
  570. }
  571. if ((1 << (buswidth - 1)) & isi->width_flags)
  572. return 0;
  573. return -EINVAL;
  574. }
  575. static int isi_camera_get_formats(struct soc_camera_device *icd,
  576. unsigned int idx,
  577. struct soc_camera_format_xlate *xlate)
  578. {
  579. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  580. int formats = 0, ret;
  581. /* sensor format */
  582. enum v4l2_mbus_pixelcode code;
  583. /* soc camera host format */
  584. const struct soc_mbus_pixelfmt *fmt;
  585. ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
  586. if (ret < 0)
  587. /* No more formats */
  588. return 0;
  589. fmt = soc_mbus_get_fmtdesc(code);
  590. if (!fmt) {
  591. dev_err(icd->parent,
  592. "Invalid format code #%u: %d\n", idx, code);
  593. return 0;
  594. }
  595. /* This also checks support for the requested bits-per-sample */
  596. ret = isi_camera_try_bus_param(icd, fmt->bits_per_sample);
  597. if (ret < 0) {
  598. dev_err(icd->parent,
  599. "Fail to try the bus parameters.\n");
  600. return 0;
  601. }
  602. switch (code) {
  603. case V4L2_MBUS_FMT_UYVY8_2X8:
  604. case V4L2_MBUS_FMT_VYUY8_2X8:
  605. case V4L2_MBUS_FMT_YUYV8_2X8:
  606. case V4L2_MBUS_FMT_YVYU8_2X8:
  607. formats++;
  608. if (xlate) {
  609. xlate->host_fmt = &isi_camera_formats[0];
  610. xlate->code = code;
  611. xlate++;
  612. dev_dbg(icd->parent, "Providing format %s using code %d\n",
  613. isi_camera_formats[0].name, code);
  614. }
  615. break;
  616. default:
  617. if (!isi_camera_packing_supported(fmt))
  618. return 0;
  619. if (xlate)
  620. dev_dbg(icd->parent,
  621. "Providing format %s in pass-through mode\n",
  622. fmt->name);
  623. }
  624. /* Generic pass-through */
  625. formats++;
  626. if (xlate) {
  627. xlate->host_fmt = fmt;
  628. xlate->code = code;
  629. xlate++;
  630. }
  631. return formats;
  632. }
  633. static int isi_camera_add_device(struct soc_camera_device *icd)
  634. {
  635. dev_dbg(icd->parent, "Atmel ISI Camera driver attached to camera %d\n",
  636. icd->devnum);
  637. return 0;
  638. }
  639. static void isi_camera_remove_device(struct soc_camera_device *icd)
  640. {
  641. dev_dbg(icd->parent, "Atmel ISI Camera driver detached from camera %d\n",
  642. icd->devnum);
  643. }
  644. /* Called with .host_lock held */
  645. static int isi_camera_clock_start(struct soc_camera_host *ici)
  646. {
  647. struct atmel_isi *isi = ici->priv;
  648. int ret;
  649. ret = clk_enable(isi->pclk);
  650. if (ret)
  651. return ret;
  652. ret = clk_enable(isi->mck);
  653. if (ret) {
  654. clk_disable(isi->pclk);
  655. return ret;
  656. }
  657. return 0;
  658. }
  659. /* Called with .host_lock held */
  660. static void isi_camera_clock_stop(struct soc_camera_host *ici)
  661. {
  662. struct atmel_isi *isi = ici->priv;
  663. clk_disable(isi->mck);
  664. clk_disable(isi->pclk);
  665. }
  666. static unsigned int isi_camera_poll(struct file *file, poll_table *pt)
  667. {
  668. struct soc_camera_device *icd = file->private_data;
  669. return vb2_poll(&icd->vb2_vidq, file, pt);
  670. }
  671. static int isi_camera_querycap(struct soc_camera_host *ici,
  672. struct v4l2_capability *cap)
  673. {
  674. strcpy(cap->driver, "atmel-isi");
  675. strcpy(cap->card, "Atmel Image Sensor Interface");
  676. cap->capabilities = (V4L2_CAP_VIDEO_CAPTURE |
  677. V4L2_CAP_STREAMING);
  678. return 0;
  679. }
  680. static int isi_camera_set_bus_param(struct soc_camera_device *icd)
  681. {
  682. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  683. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  684. struct atmel_isi *isi = ici->priv;
  685. struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
  686. unsigned long common_flags;
  687. int ret;
  688. u32 cfg1 = 0;
  689. ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
  690. if (!ret) {
  691. common_flags = soc_mbus_config_compatible(&cfg,
  692. ISI_BUS_PARAM);
  693. if (!common_flags) {
  694. dev_warn(icd->parent,
  695. "Flags incompatible: camera 0x%x, host 0x%x\n",
  696. cfg.flags, ISI_BUS_PARAM);
  697. return -EINVAL;
  698. }
  699. } else if (ret != -ENOIOCTLCMD) {
  700. return ret;
  701. } else {
  702. common_flags = ISI_BUS_PARAM;
  703. }
  704. dev_dbg(icd->parent, "Flags cam: 0x%x host: 0x%x common: 0x%lx\n",
  705. cfg.flags, ISI_BUS_PARAM, common_flags);
  706. /* Make choises, based on platform preferences */
  707. if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
  708. (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
  709. if (isi->pdata->hsync_act_low)
  710. common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
  711. else
  712. common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
  713. }
  714. if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
  715. (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
  716. if (isi->pdata->vsync_act_low)
  717. common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
  718. else
  719. common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
  720. }
  721. if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
  722. (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
  723. if (isi->pdata->pclk_act_falling)
  724. common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
  725. else
  726. common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
  727. }
  728. cfg.flags = common_flags;
  729. ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
  730. if (ret < 0 && ret != -ENOIOCTLCMD) {
  731. dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
  732. common_flags, ret);
  733. return ret;
  734. }
  735. /* set bus param for ISI */
  736. if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
  737. cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW;
  738. if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
  739. cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW;
  740. if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
  741. cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING;
  742. if (isi->pdata->has_emb_sync)
  743. cfg1 |= ISI_CFG1_EMB_SYNC;
  744. if (isi->pdata->full_mode)
  745. cfg1 |= ISI_CFG1_FULL_MODE;
  746. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  747. isi_writel(isi, ISI_CFG1, cfg1);
  748. return 0;
  749. }
  750. static struct soc_camera_host_ops isi_soc_camera_host_ops = {
  751. .owner = THIS_MODULE,
  752. .add = isi_camera_add_device,
  753. .remove = isi_camera_remove_device,
  754. .clock_start = isi_camera_clock_start,
  755. .clock_stop = isi_camera_clock_stop,
  756. .set_fmt = isi_camera_set_fmt,
  757. .try_fmt = isi_camera_try_fmt,
  758. .get_formats = isi_camera_get_formats,
  759. .init_videobuf2 = isi_camera_init_videobuf,
  760. .poll = isi_camera_poll,
  761. .querycap = isi_camera_querycap,
  762. .set_bus_param = isi_camera_set_bus_param,
  763. };
  764. /* -----------------------------------------------------------------------*/
  765. static int atmel_isi_remove(struct platform_device *pdev)
  766. {
  767. struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
  768. struct atmel_isi *isi = container_of(soc_host,
  769. struct atmel_isi, soc_host);
  770. free_irq(isi->irq, isi);
  771. soc_camera_host_unregister(soc_host);
  772. vb2_dma_contig_cleanup_ctx(isi->alloc_ctx);
  773. dma_free_coherent(&pdev->dev,
  774. sizeof(struct fbd) * MAX_BUFFER_NUM,
  775. isi->p_fb_descriptors,
  776. isi->fb_descriptors_phys);
  777. iounmap(isi->regs);
  778. clk_unprepare(isi->mck);
  779. clk_put(isi->mck);
  780. clk_unprepare(isi->pclk);
  781. clk_put(isi->pclk);
  782. kfree(isi);
  783. return 0;
  784. }
  785. static int atmel_isi_probe(struct platform_device *pdev)
  786. {
  787. unsigned int irq;
  788. struct atmel_isi *isi;
  789. struct clk *pclk;
  790. struct resource *regs;
  791. int ret, i;
  792. struct device *dev = &pdev->dev;
  793. struct soc_camera_host *soc_host;
  794. struct isi_platform_data *pdata;
  795. pdata = dev->platform_data;
  796. if (!pdata || !pdata->data_width_flags || !pdata->mck_hz) {
  797. dev_err(&pdev->dev,
  798. "No config available for Atmel ISI\n");
  799. return -EINVAL;
  800. }
  801. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  802. if (!regs)
  803. return -ENXIO;
  804. pclk = clk_get(&pdev->dev, "isi_clk");
  805. if (IS_ERR(pclk))
  806. return PTR_ERR(pclk);
  807. ret = clk_prepare(pclk);
  808. if (ret)
  809. goto err_clk_prepare_pclk;
  810. isi = kzalloc(sizeof(struct atmel_isi), GFP_KERNEL);
  811. if (!isi) {
  812. ret = -ENOMEM;
  813. dev_err(&pdev->dev, "Can't allocate interface!\n");
  814. goto err_alloc_isi;
  815. }
  816. isi->pclk = pclk;
  817. isi->pdata = pdata;
  818. isi->active = NULL;
  819. spin_lock_init(&isi->lock);
  820. init_waitqueue_head(&isi->vsync_wq);
  821. INIT_LIST_HEAD(&isi->video_buffer_list);
  822. INIT_LIST_HEAD(&isi->dma_desc_head);
  823. /* Get ISI_MCK, provided by programmable clock or external clock */
  824. isi->mck = clk_get(dev, "isi_mck");
  825. if (IS_ERR(isi->mck)) {
  826. dev_err(dev, "Failed to get isi_mck\n");
  827. ret = PTR_ERR(isi->mck);
  828. goto err_clk_get;
  829. }
  830. ret = clk_prepare(isi->mck);
  831. if (ret)
  832. goto err_clk_prepare_mck;
  833. /* Set ISI_MCK's frequency, it should be faster than pixel clock */
  834. ret = clk_set_rate(isi->mck, pdata->mck_hz);
  835. if (ret < 0)
  836. goto err_set_mck_rate;
  837. isi->p_fb_descriptors = dma_alloc_coherent(&pdev->dev,
  838. sizeof(struct fbd) * MAX_BUFFER_NUM,
  839. &isi->fb_descriptors_phys,
  840. GFP_KERNEL);
  841. if (!isi->p_fb_descriptors) {
  842. ret = -ENOMEM;
  843. dev_err(&pdev->dev, "Can't allocate descriptors!\n");
  844. goto err_alloc_descriptors;
  845. }
  846. for (i = 0; i < MAX_BUFFER_NUM; i++) {
  847. isi->dma_desc[i].p_fbd = isi->p_fb_descriptors + i;
  848. isi->dma_desc[i].fbd_phys = isi->fb_descriptors_phys +
  849. i * sizeof(struct fbd);
  850. list_add(&isi->dma_desc[i].list, &isi->dma_desc_head);
  851. }
  852. isi->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  853. if (IS_ERR(isi->alloc_ctx)) {
  854. ret = PTR_ERR(isi->alloc_ctx);
  855. goto err_alloc_ctx;
  856. }
  857. isi->regs = ioremap(regs->start, resource_size(regs));
  858. if (!isi->regs) {
  859. ret = -ENOMEM;
  860. goto err_ioremap;
  861. }
  862. if (pdata->data_width_flags & ISI_DATAWIDTH_8)
  863. isi->width_flags = 1 << 7;
  864. if (pdata->data_width_flags & ISI_DATAWIDTH_10)
  865. isi->width_flags |= 1 << 9;
  866. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  867. irq = platform_get_irq(pdev, 0);
  868. if (IS_ERR_VALUE(irq)) {
  869. ret = irq;
  870. goto err_req_irq;
  871. }
  872. ret = request_irq(irq, isi_interrupt, 0, "isi", isi);
  873. if (ret) {
  874. dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
  875. goto err_req_irq;
  876. }
  877. isi->irq = irq;
  878. soc_host = &isi->soc_host;
  879. soc_host->drv_name = "isi-camera";
  880. soc_host->ops = &isi_soc_camera_host_ops;
  881. soc_host->priv = isi;
  882. soc_host->v4l2_dev.dev = &pdev->dev;
  883. soc_host->nr = pdev->id;
  884. ret = soc_camera_host_register(soc_host);
  885. if (ret) {
  886. dev_err(&pdev->dev, "Unable to register soc camera host\n");
  887. goto err_register_soc_camera_host;
  888. }
  889. return 0;
  890. err_register_soc_camera_host:
  891. free_irq(isi->irq, isi);
  892. err_req_irq:
  893. iounmap(isi->regs);
  894. err_ioremap:
  895. vb2_dma_contig_cleanup_ctx(isi->alloc_ctx);
  896. err_alloc_ctx:
  897. dma_free_coherent(&pdev->dev,
  898. sizeof(struct fbd) * MAX_BUFFER_NUM,
  899. isi->p_fb_descriptors,
  900. isi->fb_descriptors_phys);
  901. err_alloc_descriptors:
  902. err_set_mck_rate:
  903. clk_unprepare(isi->mck);
  904. err_clk_prepare_mck:
  905. clk_put(isi->mck);
  906. err_clk_get:
  907. kfree(isi);
  908. err_alloc_isi:
  909. clk_unprepare(pclk);
  910. err_clk_prepare_pclk:
  911. clk_put(pclk);
  912. return ret;
  913. }
  914. static struct platform_driver atmel_isi_driver = {
  915. .remove = atmel_isi_remove,
  916. .driver = {
  917. .name = "atmel_isi",
  918. .owner = THIS_MODULE,
  919. },
  920. };
  921. module_platform_driver_probe(atmel_isi_driver, atmel_isi_probe);
  922. MODULE_AUTHOR("Josh Wu <josh.wu@atmel.com>");
  923. MODULE_DESCRIPTION("The V4L2 driver for Atmel Linux");
  924. MODULE_LICENSE("GPL");
  925. MODULE_SUPPORTED_DEVICE("video");