ppi.c 8.2 KB

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  1. /*
  2. * ppi.c Analog Devices Parallel Peripheral Interface driver
  3. *
  4. * Copyright (c) 2011 Analog Devices Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/module.h>
  20. #include <linux/slab.h>
  21. #include <asm/bfin_ppi.h>
  22. #include <asm/blackfin.h>
  23. #include <asm/cacheflush.h>
  24. #include <asm/dma.h>
  25. #include <asm/portmux.h>
  26. #include <media/blackfin/ppi.h>
  27. static int ppi_attach_irq(struct ppi_if *ppi, irq_handler_t handler);
  28. static void ppi_detach_irq(struct ppi_if *ppi);
  29. static int ppi_start(struct ppi_if *ppi);
  30. static int ppi_stop(struct ppi_if *ppi);
  31. static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params);
  32. static void ppi_update_addr(struct ppi_if *ppi, unsigned long addr);
  33. static const struct ppi_ops ppi_ops = {
  34. .attach_irq = ppi_attach_irq,
  35. .detach_irq = ppi_detach_irq,
  36. .start = ppi_start,
  37. .stop = ppi_stop,
  38. .set_params = ppi_set_params,
  39. .update_addr = ppi_update_addr,
  40. };
  41. static irqreturn_t ppi_irq_err(int irq, void *dev_id)
  42. {
  43. struct ppi_if *ppi = dev_id;
  44. const struct ppi_info *info = ppi->info;
  45. switch (info->type) {
  46. case PPI_TYPE_PPI:
  47. {
  48. struct bfin_ppi_regs *reg = info->base;
  49. unsigned short status;
  50. /* register on bf561 is cleared when read
  51. * others are W1C
  52. */
  53. status = bfin_read16(&reg->status);
  54. if (status & 0x3000)
  55. ppi->err = true;
  56. bfin_write16(&reg->status, 0xff00);
  57. break;
  58. }
  59. case PPI_TYPE_EPPI:
  60. {
  61. struct bfin_eppi_regs *reg = info->base;
  62. unsigned short status;
  63. status = bfin_read16(&reg->status);
  64. if (status & 0x2)
  65. ppi->err = true;
  66. bfin_write16(&reg->status, 0xffff);
  67. break;
  68. }
  69. case PPI_TYPE_EPPI3:
  70. {
  71. struct bfin_eppi3_regs *reg = info->base;
  72. unsigned long stat;
  73. stat = bfin_read32(&reg->stat);
  74. if (stat & 0x2)
  75. ppi->err = true;
  76. bfin_write32(&reg->stat, 0xc0ff);
  77. break;
  78. }
  79. default:
  80. break;
  81. }
  82. return IRQ_HANDLED;
  83. }
  84. static int ppi_attach_irq(struct ppi_if *ppi, irq_handler_t handler)
  85. {
  86. const struct ppi_info *info = ppi->info;
  87. int ret;
  88. ret = request_dma(info->dma_ch, "PPI_DMA");
  89. if (ret) {
  90. pr_err("Unable to allocate DMA channel for PPI\n");
  91. return ret;
  92. }
  93. set_dma_callback(info->dma_ch, handler, ppi);
  94. if (ppi->err_int) {
  95. ret = request_irq(info->irq_err, ppi_irq_err, 0, "PPI ERROR", ppi);
  96. if (ret) {
  97. pr_err("Unable to allocate IRQ for PPI\n");
  98. free_dma(info->dma_ch);
  99. }
  100. }
  101. return ret;
  102. }
  103. static void ppi_detach_irq(struct ppi_if *ppi)
  104. {
  105. const struct ppi_info *info = ppi->info;
  106. if (ppi->err_int)
  107. free_irq(info->irq_err, ppi);
  108. free_dma(info->dma_ch);
  109. }
  110. static int ppi_start(struct ppi_if *ppi)
  111. {
  112. const struct ppi_info *info = ppi->info;
  113. /* enable DMA */
  114. enable_dma(info->dma_ch);
  115. /* enable PPI */
  116. ppi->ppi_control |= PORT_EN;
  117. switch (info->type) {
  118. case PPI_TYPE_PPI:
  119. {
  120. struct bfin_ppi_regs *reg = info->base;
  121. bfin_write16(&reg->control, ppi->ppi_control);
  122. break;
  123. }
  124. case PPI_TYPE_EPPI:
  125. {
  126. struct bfin_eppi_regs *reg = info->base;
  127. bfin_write32(&reg->control, ppi->ppi_control);
  128. break;
  129. }
  130. case PPI_TYPE_EPPI3:
  131. {
  132. struct bfin_eppi3_regs *reg = info->base;
  133. bfin_write32(&reg->ctl, ppi->ppi_control);
  134. break;
  135. }
  136. default:
  137. return -EINVAL;
  138. }
  139. SSYNC();
  140. return 0;
  141. }
  142. static int ppi_stop(struct ppi_if *ppi)
  143. {
  144. const struct ppi_info *info = ppi->info;
  145. /* disable PPI */
  146. ppi->ppi_control &= ~PORT_EN;
  147. switch (info->type) {
  148. case PPI_TYPE_PPI:
  149. {
  150. struct bfin_ppi_regs *reg = info->base;
  151. bfin_write16(&reg->control, ppi->ppi_control);
  152. break;
  153. }
  154. case PPI_TYPE_EPPI:
  155. {
  156. struct bfin_eppi_regs *reg = info->base;
  157. bfin_write32(&reg->control, ppi->ppi_control);
  158. break;
  159. }
  160. case PPI_TYPE_EPPI3:
  161. {
  162. struct bfin_eppi3_regs *reg = info->base;
  163. bfin_write32(&reg->ctl, ppi->ppi_control);
  164. break;
  165. }
  166. default:
  167. return -EINVAL;
  168. }
  169. /* disable DMA */
  170. clear_dma_irqstat(info->dma_ch);
  171. disable_dma(info->dma_ch);
  172. SSYNC();
  173. return 0;
  174. }
  175. static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params)
  176. {
  177. const struct ppi_info *info = ppi->info;
  178. int dma32 = 0;
  179. int dma_config, bytes_per_line;
  180. int hcount, hdelay, samples_per_line;
  181. bytes_per_line = params->width * params->bpp / 8;
  182. /* convert parameters unit from pixels to samples */
  183. hcount = params->width * params->bpp / params->dlen;
  184. hdelay = params->hdelay * params->bpp / params->dlen;
  185. samples_per_line = params->line * params->bpp / params->dlen;
  186. if (params->int_mask == 0xFFFFFFFF)
  187. ppi->err_int = false;
  188. else
  189. ppi->err_int = true;
  190. dma_config = (DMA_FLOW_STOP | RESTART | DMA2D | DI_EN_Y);
  191. ppi->ppi_control = params->ppi_control & ~PORT_EN;
  192. if (!(ppi->ppi_control & PORT_DIR))
  193. dma_config |= WNR;
  194. switch (info->type) {
  195. case PPI_TYPE_PPI:
  196. {
  197. struct bfin_ppi_regs *reg = info->base;
  198. if (params->ppi_control & DMA32)
  199. dma32 = 1;
  200. bfin_write16(&reg->control, ppi->ppi_control);
  201. bfin_write16(&reg->count, samples_per_line - 1);
  202. bfin_write16(&reg->frame, params->frame);
  203. break;
  204. }
  205. case PPI_TYPE_EPPI:
  206. {
  207. struct bfin_eppi_regs *reg = info->base;
  208. if ((params->ppi_control & PACK_EN)
  209. || (params->ppi_control & 0x38000) > DLEN_16)
  210. dma32 = 1;
  211. bfin_write32(&reg->control, ppi->ppi_control);
  212. bfin_write16(&reg->line, samples_per_line);
  213. bfin_write16(&reg->frame, params->frame);
  214. bfin_write16(&reg->hdelay, hdelay);
  215. bfin_write16(&reg->vdelay, params->vdelay);
  216. bfin_write16(&reg->hcount, hcount);
  217. bfin_write16(&reg->vcount, params->height);
  218. break;
  219. }
  220. case PPI_TYPE_EPPI3:
  221. {
  222. struct bfin_eppi3_regs *reg = info->base;
  223. if ((params->ppi_control & PACK_EN)
  224. || (params->ppi_control & 0x70000) > DLEN_16)
  225. dma32 = 1;
  226. bfin_write32(&reg->ctl, ppi->ppi_control);
  227. bfin_write32(&reg->line, samples_per_line);
  228. bfin_write32(&reg->frame, params->frame);
  229. bfin_write32(&reg->hdly, hdelay);
  230. bfin_write32(&reg->vdly, params->vdelay);
  231. bfin_write32(&reg->hcnt, hcount);
  232. bfin_write32(&reg->vcnt, params->height);
  233. if (params->int_mask)
  234. bfin_write32(&reg->imsk, params->int_mask & 0xFF);
  235. if (ppi->ppi_control & PORT_DIR) {
  236. u32 hsync_width, vsync_width, vsync_period;
  237. hsync_width = params->hsync
  238. * params->bpp / params->dlen;
  239. vsync_width = params->vsync * samples_per_line;
  240. vsync_period = samples_per_line * params->frame;
  241. bfin_write32(&reg->fs1_wlhb, hsync_width);
  242. bfin_write32(&reg->fs1_paspl, samples_per_line);
  243. bfin_write32(&reg->fs2_wlvb, vsync_width);
  244. bfin_write32(&reg->fs2_palpf, vsync_period);
  245. }
  246. break;
  247. }
  248. default:
  249. return -EINVAL;
  250. }
  251. if (dma32) {
  252. dma_config |= WDSIZE_32 | PSIZE_32;
  253. set_dma_x_count(info->dma_ch, bytes_per_line >> 2);
  254. set_dma_x_modify(info->dma_ch, 4);
  255. set_dma_y_modify(info->dma_ch, 4);
  256. } else {
  257. dma_config |= WDSIZE_16 | PSIZE_16;
  258. set_dma_x_count(info->dma_ch, bytes_per_line >> 1);
  259. set_dma_x_modify(info->dma_ch, 2);
  260. set_dma_y_modify(info->dma_ch, 2);
  261. }
  262. set_dma_y_count(info->dma_ch, params->height);
  263. set_dma_config(info->dma_ch, dma_config);
  264. SSYNC();
  265. return 0;
  266. }
  267. static void ppi_update_addr(struct ppi_if *ppi, unsigned long addr)
  268. {
  269. set_dma_start_addr(ppi->info->dma_ch, addr);
  270. }
  271. struct ppi_if *ppi_create_instance(const struct ppi_info *info)
  272. {
  273. struct ppi_if *ppi;
  274. if (!info || !info->pin_req)
  275. return NULL;
  276. if (peripheral_request_list(info->pin_req, KBUILD_MODNAME)) {
  277. pr_err("request peripheral failed\n");
  278. return NULL;
  279. }
  280. ppi = kzalloc(sizeof(*ppi), GFP_KERNEL);
  281. if (!ppi) {
  282. peripheral_free_list(info->pin_req);
  283. pr_err("unable to allocate memory for ppi handle\n");
  284. return NULL;
  285. }
  286. ppi->ops = &ppi_ops;
  287. ppi->info = info;
  288. pr_info("ppi probe success\n");
  289. return ppi;
  290. }
  291. EXPORT_SYMBOL(ppi_create_instance);
  292. void ppi_delete_instance(struct ppi_if *ppi)
  293. {
  294. peripheral_free_list(ppi->info->pin_req);
  295. kfree(ppi);
  296. }
  297. EXPORT_SYMBOL(ppi_delete_instance);
  298. MODULE_DESCRIPTION("Analog Devices PPI driver");
  299. MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
  300. MODULE_LICENSE("GPL v2");