saa7164-core.c 40 KB

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  1. /*
  2. * Driver for the NXP SAA7164 PCIe bridge
  3. *
  4. * Copyright (c) 2010 Steven Toth <stoth@kernellabs.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/list.h>
  23. #include <linux/module.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/kmod.h>
  26. #include <linux/kernel.h>
  27. #include <linux/slab.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/delay.h>
  30. #include <asm/div64.h>
  31. #ifdef CONFIG_PROC_FS
  32. #include <linux/proc_fs.h>
  33. #endif
  34. #include "saa7164.h"
  35. MODULE_DESCRIPTION("Driver for NXP SAA7164 based TV cards");
  36. MODULE_AUTHOR("Steven Toth <stoth@kernellabs.com>");
  37. MODULE_LICENSE("GPL");
  38. /*
  39. * 1 Basic
  40. * 2
  41. * 4 i2c
  42. * 8 api
  43. * 16 cmd
  44. * 32 bus
  45. */
  46. unsigned int saa_debug;
  47. module_param_named(debug, saa_debug, int, 0644);
  48. MODULE_PARM_DESC(debug, "enable debug messages");
  49. unsigned int fw_debug;
  50. module_param(fw_debug, int, 0644);
  51. MODULE_PARM_DESC(fw_debug, "Firmware debug level def:2");
  52. unsigned int encoder_buffers = SAA7164_MAX_ENCODER_BUFFERS;
  53. module_param(encoder_buffers, int, 0644);
  54. MODULE_PARM_DESC(encoder_buffers, "Total buffers in read queue 16-512 def:64");
  55. unsigned int vbi_buffers = SAA7164_MAX_VBI_BUFFERS;
  56. module_param(vbi_buffers, int, 0644);
  57. MODULE_PARM_DESC(vbi_buffers, "Total buffers in read queue 16-512 def:64");
  58. unsigned int waitsecs = 10;
  59. module_param(waitsecs, int, 0644);
  60. MODULE_PARM_DESC(waitsecs, "timeout on firmware messages");
  61. static unsigned int card[] = {[0 ... (SAA7164_MAXBOARDS - 1)] = UNSET };
  62. module_param_array(card, int, NULL, 0444);
  63. MODULE_PARM_DESC(card, "card type");
  64. unsigned int print_histogram = 64;
  65. module_param(print_histogram, int, 0644);
  66. MODULE_PARM_DESC(print_histogram, "print histogram values once");
  67. unsigned int crc_checking = 1;
  68. module_param(crc_checking, int, 0644);
  69. MODULE_PARM_DESC(crc_checking, "enable crc sanity checking on buffers");
  70. unsigned int guard_checking = 1;
  71. module_param(guard_checking, int, 0644);
  72. MODULE_PARM_DESC(guard_checking,
  73. "enable dma sanity checking for buffer overruns");
  74. static unsigned int saa7164_devcount;
  75. static DEFINE_MUTEX(devlist);
  76. LIST_HEAD(saa7164_devlist);
  77. #define INT_SIZE 16
  78. static void saa7164_pack_verifier(struct saa7164_buffer *buf)
  79. {
  80. u8 *p = (u8 *)buf->cpu;
  81. int i;
  82. for (i = 0; i < buf->actual_size; i += 2048) {
  83. if ((*(p + i + 0) != 0x00) || (*(p + i + 1) != 0x00) ||
  84. (*(p + i + 2) != 0x01) || (*(p + i + 3) != 0xBA)) {
  85. printk(KERN_ERR "No pack at 0x%x\n", i);
  86. #if 0
  87. print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
  88. p + 1, 32, false);
  89. #endif
  90. }
  91. }
  92. }
  93. #define FIXED_VIDEO_PID 0xf1
  94. #define FIXED_AUDIO_PID 0xf2
  95. static void saa7164_ts_verifier(struct saa7164_buffer *buf)
  96. {
  97. struct saa7164_port *port = buf->port;
  98. u32 i;
  99. u8 cc, a;
  100. u16 pid;
  101. u8 __iomem *bufcpu = (u8 *)buf->cpu;
  102. port->sync_errors = 0;
  103. port->v_cc_errors = 0;
  104. port->a_cc_errors = 0;
  105. for (i = 0; i < buf->actual_size; i += 188) {
  106. if (*(bufcpu + i) != 0x47)
  107. port->sync_errors++;
  108. /* TODO: Query pid lower 8 bits, ignoring upper bits intensionally */
  109. pid = ((*(bufcpu + i + 1) & 0x1f) << 8) | *(bufcpu + i + 2);
  110. cc = *(bufcpu + i + 3) & 0x0f;
  111. if (pid == FIXED_VIDEO_PID) {
  112. a = ((port->last_v_cc + 1) & 0x0f);
  113. if (a != cc) {
  114. printk(KERN_ERR "video cc last = %x current = %x i = %d\n",
  115. port->last_v_cc, cc, i);
  116. port->v_cc_errors++;
  117. }
  118. port->last_v_cc = cc;
  119. } else
  120. if (pid == FIXED_AUDIO_PID) {
  121. a = ((port->last_a_cc + 1) & 0x0f);
  122. if (a != cc) {
  123. printk(KERN_ERR "audio cc last = %x current = %x i = %d\n",
  124. port->last_a_cc, cc, i);
  125. port->a_cc_errors++;
  126. }
  127. port->last_a_cc = cc;
  128. }
  129. }
  130. /* Only report errors if we've been through this function atleast
  131. * once already and the cached cc values are primed. First time through
  132. * always generates errors.
  133. */
  134. if (port->v_cc_errors && (port->done_first_interrupt > 1))
  135. printk(KERN_ERR "video pid cc, %d errors\n", port->v_cc_errors);
  136. if (port->a_cc_errors && (port->done_first_interrupt > 1))
  137. printk(KERN_ERR "audio pid cc, %d errors\n", port->a_cc_errors);
  138. if (port->sync_errors && (port->done_first_interrupt > 1))
  139. printk(KERN_ERR "sync_errors = %d\n", port->sync_errors);
  140. if (port->done_first_interrupt == 1)
  141. port->done_first_interrupt++;
  142. }
  143. static void saa7164_histogram_reset(struct saa7164_histogram *hg, char *name)
  144. {
  145. int i;
  146. memset(hg, 0, sizeof(struct saa7164_histogram));
  147. strcpy(hg->name, name);
  148. /* First 30ms x 1ms */
  149. for (i = 0; i < 30; i++)
  150. hg->counter1[0 + i].val = i;
  151. /* 30 - 200ms x 10ms */
  152. for (i = 0; i < 18; i++)
  153. hg->counter1[30 + i].val = 30 + (i * 10);
  154. /* 200 - 2000ms x 100ms */
  155. for (i = 0; i < 15; i++)
  156. hg->counter1[48 + i].val = 200 + (i * 200);
  157. /* Catch all massive value (2secs) */
  158. hg->counter1[55].val = 2000;
  159. /* Catch all massive value (4secs) */
  160. hg->counter1[56].val = 4000;
  161. /* Catch all massive value (8secs) */
  162. hg->counter1[57].val = 8000;
  163. /* Catch all massive value (15secs) */
  164. hg->counter1[58].val = 15000;
  165. /* Catch all massive value (30secs) */
  166. hg->counter1[59].val = 30000;
  167. /* Catch all massive value (60secs) */
  168. hg->counter1[60].val = 60000;
  169. /* Catch all massive value (5mins) */
  170. hg->counter1[61].val = 300000;
  171. /* Catch all massive value (15mins) */
  172. hg->counter1[62].val = 900000;
  173. /* Catch all massive values (1hr) */
  174. hg->counter1[63].val = 3600000;
  175. }
  176. void saa7164_histogram_update(struct saa7164_histogram *hg, u32 val)
  177. {
  178. int i;
  179. for (i = 0; i < 64; i++) {
  180. if (val <= hg->counter1[i].val) {
  181. hg->counter1[i].count++;
  182. hg->counter1[i].update_time = jiffies;
  183. break;
  184. }
  185. }
  186. }
  187. static void saa7164_histogram_print(struct saa7164_port *port,
  188. struct saa7164_histogram *hg)
  189. {
  190. u32 entries = 0;
  191. int i;
  192. printk(KERN_ERR "Histogram named %s (ms, count, last_update_jiffy)\n", hg->name);
  193. for (i = 0; i < 64; i++) {
  194. if (hg->counter1[i].count == 0)
  195. continue;
  196. printk(KERN_ERR " %4d %12d %Ld\n",
  197. hg->counter1[i].val,
  198. hg->counter1[i].count,
  199. hg->counter1[i].update_time);
  200. entries++;
  201. }
  202. printk(KERN_ERR "Total: %d\n", entries);
  203. }
  204. static void saa7164_work_enchandler_helper(struct saa7164_port *port, int bufnr)
  205. {
  206. struct saa7164_dev *dev = port->dev;
  207. struct saa7164_buffer *buf = NULL;
  208. struct saa7164_user_buffer *ubuf = NULL;
  209. struct list_head *c, *n;
  210. int i = 0;
  211. u8 __iomem *p;
  212. mutex_lock(&port->dmaqueue_lock);
  213. list_for_each_safe(c, n, &port->dmaqueue.list) {
  214. buf = list_entry(c, struct saa7164_buffer, list);
  215. if (i++ > port->hwcfg.buffercount) {
  216. printk(KERN_ERR "%s() illegal i count %d\n",
  217. __func__, i);
  218. break;
  219. }
  220. if (buf->idx == bufnr) {
  221. /* Found the buffer, deal with it */
  222. dprintk(DBGLVL_IRQ, "%s() bufnr: %d\n", __func__, bufnr);
  223. if (crc_checking) {
  224. /* Throw a new checksum on the dma buffer */
  225. buf->crc = crc32(0, buf->cpu, buf->actual_size);
  226. }
  227. if (guard_checking) {
  228. p = (u8 *)buf->cpu;
  229. if ((*(p + buf->actual_size + 0) != 0xff) ||
  230. (*(p + buf->actual_size + 1) != 0xff) ||
  231. (*(p + buf->actual_size + 2) != 0xff) ||
  232. (*(p + buf->actual_size + 3) != 0xff) ||
  233. (*(p + buf->actual_size + 0x10) != 0xff) ||
  234. (*(p + buf->actual_size + 0x11) != 0xff) ||
  235. (*(p + buf->actual_size + 0x12) != 0xff) ||
  236. (*(p + buf->actual_size + 0x13) != 0xff)) {
  237. printk(KERN_ERR "%s() buf %p guard buffer breach\n",
  238. __func__, buf);
  239. #if 0
  240. print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
  241. p + buf->actual_size - 32, 64, false);
  242. #endif
  243. }
  244. }
  245. if ((port->nr != SAA7164_PORT_VBI1) && (port->nr != SAA7164_PORT_VBI2)) {
  246. /* Validate the incoming buffer content */
  247. if (port->encoder_params.stream_type == V4L2_MPEG_STREAM_TYPE_MPEG2_TS)
  248. saa7164_ts_verifier(buf);
  249. else if (port->encoder_params.stream_type == V4L2_MPEG_STREAM_TYPE_MPEG2_PS)
  250. saa7164_pack_verifier(buf);
  251. }
  252. /* find a free user buffer and clone to it */
  253. if (!list_empty(&port->list_buf_free.list)) {
  254. /* Pull the first buffer from the used list */
  255. ubuf = list_first_entry(&port->list_buf_free.list,
  256. struct saa7164_user_buffer, list);
  257. if (buf->actual_size <= ubuf->actual_size) {
  258. memcpy_fromio(ubuf->data, buf->cpu,
  259. ubuf->actual_size);
  260. if (crc_checking) {
  261. /* Throw a new checksum on the read buffer */
  262. ubuf->crc = crc32(0, ubuf->data, ubuf->actual_size);
  263. }
  264. /* Requeue the buffer on the free list */
  265. ubuf->pos = 0;
  266. list_move_tail(&ubuf->list,
  267. &port->list_buf_used.list);
  268. /* Flag any userland waiters */
  269. wake_up_interruptible(&port->wait_read);
  270. } else {
  271. printk(KERN_ERR "buf %p bufsize fails match\n", buf);
  272. }
  273. } else
  274. printk(KERN_ERR "encirq no free buffers, increase param encoder_buffers\n");
  275. /* Ensure offset into buffer remains 0, fill buffer
  276. * with known bad data. We check for this data at a later point
  277. * in time. */
  278. saa7164_buffer_zero_offsets(port, bufnr);
  279. memset_io(buf->cpu, 0xff, buf->pci_size);
  280. if (crc_checking) {
  281. /* Throw yet aanother new checksum on the dma buffer */
  282. buf->crc = crc32(0, buf->cpu, buf->actual_size);
  283. }
  284. break;
  285. }
  286. }
  287. mutex_unlock(&port->dmaqueue_lock);
  288. }
  289. static void saa7164_work_enchandler(struct work_struct *w)
  290. {
  291. struct saa7164_port *port =
  292. container_of(w, struct saa7164_port, workenc);
  293. struct saa7164_dev *dev = port->dev;
  294. u32 wp, mcb, rp, cnt = 0;
  295. port->last_svc_msecs_diff = port->last_svc_msecs;
  296. port->last_svc_msecs = jiffies_to_msecs(jiffies);
  297. port->last_svc_msecs_diff = port->last_svc_msecs -
  298. port->last_svc_msecs_diff;
  299. saa7164_histogram_update(&port->svc_interval,
  300. port->last_svc_msecs_diff);
  301. port->last_irq_svc_msecs_diff = port->last_svc_msecs -
  302. port->last_irq_msecs;
  303. saa7164_histogram_update(&port->irq_svc_interval,
  304. port->last_irq_svc_msecs_diff);
  305. dprintk(DBGLVL_IRQ,
  306. "%s() %Ldms elapsed irq->deferred %Ldms wp: %d rp: %d\n",
  307. __func__,
  308. port->last_svc_msecs_diff,
  309. port->last_irq_svc_msecs_diff,
  310. port->last_svc_wp,
  311. port->last_svc_rp
  312. );
  313. /* Current write position */
  314. wp = saa7164_readl(port->bufcounter);
  315. if (wp > (port->hwcfg.buffercount - 1)) {
  316. printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp);
  317. return;
  318. }
  319. /* Most current complete buffer */
  320. if (wp == 0)
  321. mcb = (port->hwcfg.buffercount - 1);
  322. else
  323. mcb = wp - 1;
  324. while (1) {
  325. if (port->done_first_interrupt == 0) {
  326. port->done_first_interrupt++;
  327. rp = mcb;
  328. } else
  329. rp = (port->last_svc_rp + 1) % 8;
  330. if (rp > (port->hwcfg.buffercount - 1)) {
  331. printk(KERN_ERR "%s() illegal rp count %d\n", __func__, rp);
  332. break;
  333. }
  334. saa7164_work_enchandler_helper(port, rp);
  335. port->last_svc_rp = rp;
  336. cnt++;
  337. if (rp == mcb)
  338. break;
  339. }
  340. /* TODO: Convert this into a /proc/saa7164 style readable file */
  341. if (print_histogram == port->nr) {
  342. saa7164_histogram_print(port, &port->irq_interval);
  343. saa7164_histogram_print(port, &port->svc_interval);
  344. saa7164_histogram_print(port, &port->irq_svc_interval);
  345. saa7164_histogram_print(port, &port->read_interval);
  346. saa7164_histogram_print(port, &port->poll_interval);
  347. /* TODO: fix this to preserve any previous state */
  348. print_histogram = 64 + port->nr;
  349. }
  350. }
  351. static void saa7164_work_vbihandler(struct work_struct *w)
  352. {
  353. struct saa7164_port *port =
  354. container_of(w, struct saa7164_port, workenc);
  355. struct saa7164_dev *dev = port->dev;
  356. u32 wp, mcb, rp, cnt = 0;
  357. port->last_svc_msecs_diff = port->last_svc_msecs;
  358. port->last_svc_msecs = jiffies_to_msecs(jiffies);
  359. port->last_svc_msecs_diff = port->last_svc_msecs -
  360. port->last_svc_msecs_diff;
  361. saa7164_histogram_update(&port->svc_interval,
  362. port->last_svc_msecs_diff);
  363. port->last_irq_svc_msecs_diff = port->last_svc_msecs -
  364. port->last_irq_msecs;
  365. saa7164_histogram_update(&port->irq_svc_interval,
  366. port->last_irq_svc_msecs_diff);
  367. dprintk(DBGLVL_IRQ,
  368. "%s() %Ldms elapsed irq->deferred %Ldms wp: %d rp: %d\n",
  369. __func__,
  370. port->last_svc_msecs_diff,
  371. port->last_irq_svc_msecs_diff,
  372. port->last_svc_wp,
  373. port->last_svc_rp
  374. );
  375. /* Current write position */
  376. wp = saa7164_readl(port->bufcounter);
  377. if (wp > (port->hwcfg.buffercount - 1)) {
  378. printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp);
  379. return;
  380. }
  381. /* Most current complete buffer */
  382. if (wp == 0)
  383. mcb = (port->hwcfg.buffercount - 1);
  384. else
  385. mcb = wp - 1;
  386. while (1) {
  387. if (port->done_first_interrupt == 0) {
  388. port->done_first_interrupt++;
  389. rp = mcb;
  390. } else
  391. rp = (port->last_svc_rp + 1) % 8;
  392. if (rp > (port->hwcfg.buffercount - 1)) {
  393. printk(KERN_ERR "%s() illegal rp count %d\n", __func__, rp);
  394. break;
  395. }
  396. saa7164_work_enchandler_helper(port, rp);
  397. port->last_svc_rp = rp;
  398. cnt++;
  399. if (rp == mcb)
  400. break;
  401. }
  402. /* TODO: Convert this into a /proc/saa7164 style readable file */
  403. if (print_histogram == port->nr) {
  404. saa7164_histogram_print(port, &port->irq_interval);
  405. saa7164_histogram_print(port, &port->svc_interval);
  406. saa7164_histogram_print(port, &port->irq_svc_interval);
  407. saa7164_histogram_print(port, &port->read_interval);
  408. saa7164_histogram_print(port, &port->poll_interval);
  409. /* TODO: fix this to preserve any previous state */
  410. print_histogram = 64 + port->nr;
  411. }
  412. }
  413. static void saa7164_work_cmdhandler(struct work_struct *w)
  414. {
  415. struct saa7164_dev *dev = container_of(w, struct saa7164_dev, workcmd);
  416. /* Wake up any complete commands */
  417. saa7164_irq_dequeue(dev);
  418. }
  419. static void saa7164_buffer_deliver(struct saa7164_buffer *buf)
  420. {
  421. struct saa7164_port *port = buf->port;
  422. /* Feed the transport payload into the kernel demux */
  423. dvb_dmx_swfilter_packets(&port->dvb.demux, (u8 *)buf->cpu,
  424. SAA7164_TS_NUMBER_OF_LINES);
  425. }
  426. static irqreturn_t saa7164_irq_vbi(struct saa7164_port *port)
  427. {
  428. struct saa7164_dev *dev = port->dev;
  429. /* Store old time */
  430. port->last_irq_msecs_diff = port->last_irq_msecs;
  431. /* Collect new stats */
  432. port->last_irq_msecs = jiffies_to_msecs(jiffies);
  433. /* Calculate stats */
  434. port->last_irq_msecs_diff = port->last_irq_msecs -
  435. port->last_irq_msecs_diff;
  436. saa7164_histogram_update(&port->irq_interval,
  437. port->last_irq_msecs_diff);
  438. dprintk(DBGLVL_IRQ, "%s() %Ldms elapsed\n", __func__,
  439. port->last_irq_msecs_diff);
  440. /* Tis calls the vbi irq handler */
  441. schedule_work(&port->workenc);
  442. return 0;
  443. }
  444. static irqreturn_t saa7164_irq_encoder(struct saa7164_port *port)
  445. {
  446. struct saa7164_dev *dev = port->dev;
  447. /* Store old time */
  448. port->last_irq_msecs_diff = port->last_irq_msecs;
  449. /* Collect new stats */
  450. port->last_irq_msecs = jiffies_to_msecs(jiffies);
  451. /* Calculate stats */
  452. port->last_irq_msecs_diff = port->last_irq_msecs -
  453. port->last_irq_msecs_diff;
  454. saa7164_histogram_update(&port->irq_interval,
  455. port->last_irq_msecs_diff);
  456. dprintk(DBGLVL_IRQ, "%s() %Ldms elapsed\n", __func__,
  457. port->last_irq_msecs_diff);
  458. schedule_work(&port->workenc);
  459. return 0;
  460. }
  461. static irqreturn_t saa7164_irq_ts(struct saa7164_port *port)
  462. {
  463. struct saa7164_dev *dev = port->dev;
  464. struct saa7164_buffer *buf;
  465. struct list_head *c, *n;
  466. int wp, i = 0, rp;
  467. /* Find the current write point from the hardware */
  468. wp = saa7164_readl(port->bufcounter);
  469. if (wp > (port->hwcfg.buffercount - 1))
  470. BUG();
  471. /* Find the previous buffer to the current write point */
  472. if (wp == 0)
  473. rp = (port->hwcfg.buffercount - 1);
  474. else
  475. rp = wp - 1;
  476. /* Lookup the WP in the buffer list */
  477. /* TODO: turn this into a worker thread */
  478. list_for_each_safe(c, n, &port->dmaqueue.list) {
  479. buf = list_entry(c, struct saa7164_buffer, list);
  480. if (i++ > port->hwcfg.buffercount)
  481. BUG();
  482. if (buf->idx == rp) {
  483. /* Found the buffer, deal with it */
  484. dprintk(DBGLVL_IRQ, "%s() wp: %d processing: %d\n",
  485. __func__, wp, rp);
  486. saa7164_buffer_deliver(buf);
  487. break;
  488. }
  489. }
  490. return 0;
  491. }
  492. /* Primary IRQ handler and dispatch mechanism */
  493. static irqreturn_t saa7164_irq(int irq, void *dev_id)
  494. {
  495. struct saa7164_dev *dev = dev_id;
  496. struct saa7164_port *porta = &dev->ports[SAA7164_PORT_TS1];
  497. struct saa7164_port *portb = &dev->ports[SAA7164_PORT_TS2];
  498. struct saa7164_port *portc = &dev->ports[SAA7164_PORT_ENC1];
  499. struct saa7164_port *portd = &dev->ports[SAA7164_PORT_ENC2];
  500. struct saa7164_port *porte = &dev->ports[SAA7164_PORT_VBI1];
  501. struct saa7164_port *portf = &dev->ports[SAA7164_PORT_VBI2];
  502. u32 intid, intstat[INT_SIZE/4];
  503. int i, handled = 0, bit;
  504. if (dev == NULL) {
  505. printk(KERN_ERR "%s() No device specified\n", __func__);
  506. handled = 0;
  507. goto out;
  508. }
  509. /* Check that the hardware is accessible. If the status bytes are
  510. * 0xFF then the device is not accessible, the the IRQ belongs
  511. * to another driver.
  512. * 4 x u32 interrupt registers.
  513. */
  514. for (i = 0; i < INT_SIZE/4; i++) {
  515. /* TODO: Convert into saa7164_readl() */
  516. /* Read the 4 hardware interrupt registers */
  517. intstat[i] = saa7164_readl(dev->int_status + (i * 4));
  518. if (intstat[i])
  519. handled = 1;
  520. }
  521. if (handled == 0)
  522. goto out;
  523. /* For each of the HW interrupt registers */
  524. for (i = 0; i < INT_SIZE/4; i++) {
  525. if (intstat[i]) {
  526. /* Each function of the board has it's own interruptid.
  527. * Find the function that triggered then call
  528. * it's handler.
  529. */
  530. for (bit = 0; bit < 32; bit++) {
  531. if (((intstat[i] >> bit) & 0x00000001) == 0)
  532. continue;
  533. /* Calculate the interrupt id (0x00 to 0x7f) */
  534. intid = (i * 32) + bit;
  535. if (intid == dev->intfdesc.bInterruptId) {
  536. /* A response to an cmd/api call */
  537. schedule_work(&dev->workcmd);
  538. } else if (intid == porta->hwcfg.interruptid) {
  539. /* Transport path 1 */
  540. saa7164_irq_ts(porta);
  541. } else if (intid == portb->hwcfg.interruptid) {
  542. /* Transport path 2 */
  543. saa7164_irq_ts(portb);
  544. } else if (intid == portc->hwcfg.interruptid) {
  545. /* Encoder path 1 */
  546. saa7164_irq_encoder(portc);
  547. } else if (intid == portd->hwcfg.interruptid) {
  548. /* Encoder path 2 */
  549. saa7164_irq_encoder(portd);
  550. } else if (intid == porte->hwcfg.interruptid) {
  551. /* VBI path 1 */
  552. saa7164_irq_vbi(porte);
  553. } else if (intid == portf->hwcfg.interruptid) {
  554. /* VBI path 2 */
  555. saa7164_irq_vbi(portf);
  556. } else {
  557. /* Find the function */
  558. dprintk(DBGLVL_IRQ,
  559. "%s() unhandled interrupt "
  560. "reg 0x%x bit 0x%x "
  561. "intid = 0x%x\n",
  562. __func__, i, bit, intid);
  563. }
  564. }
  565. /* Ack it */
  566. saa7164_writel(dev->int_ack + (i * 4), intstat[i]);
  567. }
  568. }
  569. out:
  570. return IRQ_RETVAL(handled);
  571. }
  572. void saa7164_getfirmwarestatus(struct saa7164_dev *dev)
  573. {
  574. struct saa7164_fw_status *s = &dev->fw_status;
  575. dev->fw_status.status = saa7164_readl(SAA_DEVICE_SYSINIT_STATUS);
  576. dev->fw_status.mode = saa7164_readl(SAA_DEVICE_SYSINIT_MODE);
  577. dev->fw_status.spec = saa7164_readl(SAA_DEVICE_SYSINIT_SPEC);
  578. dev->fw_status.inst = saa7164_readl(SAA_DEVICE_SYSINIT_INST);
  579. dev->fw_status.cpuload = saa7164_readl(SAA_DEVICE_SYSINIT_CPULOAD);
  580. dev->fw_status.remainheap =
  581. saa7164_readl(SAA_DEVICE_SYSINIT_REMAINHEAP);
  582. dprintk(1, "Firmware status:\n");
  583. dprintk(1, " .status = 0x%08x\n", s->status);
  584. dprintk(1, " .mode = 0x%08x\n", s->mode);
  585. dprintk(1, " .spec = 0x%08x\n", s->spec);
  586. dprintk(1, " .inst = 0x%08x\n", s->inst);
  587. dprintk(1, " .cpuload = 0x%08x\n", s->cpuload);
  588. dprintk(1, " .remainheap = 0x%08x\n", s->remainheap);
  589. }
  590. u32 saa7164_getcurrentfirmwareversion(struct saa7164_dev *dev)
  591. {
  592. u32 reg;
  593. reg = saa7164_readl(SAA_DEVICE_VERSION);
  594. dprintk(1, "Device running firmware version %d.%d.%d.%d (0x%x)\n",
  595. (reg & 0x0000fc00) >> 10,
  596. (reg & 0x000003e0) >> 5,
  597. (reg & 0x0000001f),
  598. (reg & 0xffff0000) >> 16,
  599. reg);
  600. return reg;
  601. }
  602. /* TODO: Debugging func, remove */
  603. void saa7164_dumpregs(struct saa7164_dev *dev, u32 addr)
  604. {
  605. int i;
  606. dprintk(1, "--------------------> "
  607. "00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n");
  608. for (i = 0; i < 0x100; i += 16)
  609. dprintk(1, "region0[0x%08x] = "
  610. "%02x %02x %02x %02x %02x %02x %02x %02x"
  611. " %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
  612. (u8)saa7164_readb(addr + i + 0),
  613. (u8)saa7164_readb(addr + i + 1),
  614. (u8)saa7164_readb(addr + i + 2),
  615. (u8)saa7164_readb(addr + i + 3),
  616. (u8)saa7164_readb(addr + i + 4),
  617. (u8)saa7164_readb(addr + i + 5),
  618. (u8)saa7164_readb(addr + i + 6),
  619. (u8)saa7164_readb(addr + i + 7),
  620. (u8)saa7164_readb(addr + i + 8),
  621. (u8)saa7164_readb(addr + i + 9),
  622. (u8)saa7164_readb(addr + i + 10),
  623. (u8)saa7164_readb(addr + i + 11),
  624. (u8)saa7164_readb(addr + i + 12),
  625. (u8)saa7164_readb(addr + i + 13),
  626. (u8)saa7164_readb(addr + i + 14),
  627. (u8)saa7164_readb(addr + i + 15)
  628. );
  629. }
  630. static void saa7164_dump_hwdesc(struct saa7164_dev *dev)
  631. {
  632. dprintk(1, "@0x%p hwdesc sizeof(struct tmComResHWDescr) = %d bytes\n",
  633. &dev->hwdesc, (u32)sizeof(struct tmComResHWDescr));
  634. dprintk(1, " .bLength = 0x%x\n", dev->hwdesc.bLength);
  635. dprintk(1, " .bDescriptorType = 0x%x\n", dev->hwdesc.bDescriptorType);
  636. dprintk(1, " .bDescriptorSubtype = 0x%x\n",
  637. dev->hwdesc.bDescriptorSubtype);
  638. dprintk(1, " .bcdSpecVersion = 0x%x\n", dev->hwdesc.bcdSpecVersion);
  639. dprintk(1, " .dwClockFrequency = 0x%x\n", dev->hwdesc.dwClockFrequency);
  640. dprintk(1, " .dwClockUpdateRes = 0x%x\n", dev->hwdesc.dwClockUpdateRes);
  641. dprintk(1, " .bCapabilities = 0x%x\n", dev->hwdesc.bCapabilities);
  642. dprintk(1, " .dwDeviceRegistersLocation = 0x%x\n",
  643. dev->hwdesc.dwDeviceRegistersLocation);
  644. dprintk(1, " .dwHostMemoryRegion = 0x%x\n",
  645. dev->hwdesc.dwHostMemoryRegion);
  646. dprintk(1, " .dwHostMemoryRegionSize = 0x%x\n",
  647. dev->hwdesc.dwHostMemoryRegionSize);
  648. dprintk(1, " .dwHostHibernatMemRegion = 0x%x\n",
  649. dev->hwdesc.dwHostHibernatMemRegion);
  650. dprintk(1, " .dwHostHibernatMemRegionSize = 0x%x\n",
  651. dev->hwdesc.dwHostHibernatMemRegionSize);
  652. }
  653. static void saa7164_dump_intfdesc(struct saa7164_dev *dev)
  654. {
  655. dprintk(1, "@0x%p intfdesc "
  656. "sizeof(struct tmComResInterfaceDescr) = %d bytes\n",
  657. &dev->intfdesc, (u32)sizeof(struct tmComResInterfaceDescr));
  658. dprintk(1, " .bLength = 0x%x\n", dev->intfdesc.bLength);
  659. dprintk(1, " .bDescriptorType = 0x%x\n", dev->intfdesc.bDescriptorType);
  660. dprintk(1, " .bDescriptorSubtype = 0x%x\n",
  661. dev->intfdesc.bDescriptorSubtype);
  662. dprintk(1, " .bFlags = 0x%x\n", dev->intfdesc.bFlags);
  663. dprintk(1, " .bInterfaceType = 0x%x\n", dev->intfdesc.bInterfaceType);
  664. dprintk(1, " .bInterfaceId = 0x%x\n", dev->intfdesc.bInterfaceId);
  665. dprintk(1, " .bBaseInterface = 0x%x\n", dev->intfdesc.bBaseInterface);
  666. dprintk(1, " .bInterruptId = 0x%x\n", dev->intfdesc.bInterruptId);
  667. dprintk(1, " .bDebugInterruptId = 0x%x\n",
  668. dev->intfdesc.bDebugInterruptId);
  669. dprintk(1, " .BARLocation = 0x%x\n", dev->intfdesc.BARLocation);
  670. }
  671. static void saa7164_dump_busdesc(struct saa7164_dev *dev)
  672. {
  673. dprintk(1, "@0x%p busdesc sizeof(struct tmComResBusDescr) = %d bytes\n",
  674. &dev->busdesc, (u32)sizeof(struct tmComResBusDescr));
  675. dprintk(1, " .CommandRing = 0x%016Lx\n", dev->busdesc.CommandRing);
  676. dprintk(1, " .ResponseRing = 0x%016Lx\n", dev->busdesc.ResponseRing);
  677. dprintk(1, " .CommandWrite = 0x%x\n", dev->busdesc.CommandWrite);
  678. dprintk(1, " .CommandRead = 0x%x\n", dev->busdesc.CommandRead);
  679. dprintk(1, " .ResponseWrite = 0x%x\n", dev->busdesc.ResponseWrite);
  680. dprintk(1, " .ResponseRead = 0x%x\n", dev->busdesc.ResponseRead);
  681. }
  682. /* Much of the hardware configuration and PCI registers are configured
  683. * dynamically depending on firmware. We have to cache some initial
  684. * structures then use these to locate other important structures
  685. * from PCI space.
  686. */
  687. static void saa7164_get_descriptors(struct saa7164_dev *dev)
  688. {
  689. memcpy_fromio(&dev->hwdesc, dev->bmmio, sizeof(struct tmComResHWDescr));
  690. memcpy_fromio(&dev->intfdesc, dev->bmmio + sizeof(struct tmComResHWDescr),
  691. sizeof(struct tmComResInterfaceDescr));
  692. memcpy_fromio(&dev->busdesc, dev->bmmio + dev->intfdesc.BARLocation,
  693. sizeof(struct tmComResBusDescr));
  694. if (dev->hwdesc.bLength != sizeof(struct tmComResHWDescr)) {
  695. printk(KERN_ERR "Structure struct tmComResHWDescr is mangled\n");
  696. printk(KERN_ERR "Need %x got %d\n", dev->hwdesc.bLength,
  697. (u32)sizeof(struct tmComResHWDescr));
  698. } else
  699. saa7164_dump_hwdesc(dev);
  700. if (dev->intfdesc.bLength != sizeof(struct tmComResInterfaceDescr)) {
  701. printk(KERN_ERR "struct struct tmComResInterfaceDescr is mangled\n");
  702. printk(KERN_ERR "Need %x got %d\n", dev->intfdesc.bLength,
  703. (u32)sizeof(struct tmComResInterfaceDescr));
  704. } else
  705. saa7164_dump_intfdesc(dev);
  706. saa7164_dump_busdesc(dev);
  707. }
  708. static int saa7164_pci_quirks(struct saa7164_dev *dev)
  709. {
  710. return 0;
  711. }
  712. static int get_resources(struct saa7164_dev *dev)
  713. {
  714. if (request_mem_region(pci_resource_start(dev->pci, 0),
  715. pci_resource_len(dev->pci, 0), dev->name)) {
  716. if (request_mem_region(pci_resource_start(dev->pci, 2),
  717. pci_resource_len(dev->pci, 2), dev->name))
  718. return 0;
  719. }
  720. printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx or 0x%llx\n",
  721. dev->name,
  722. (u64)pci_resource_start(dev->pci, 0),
  723. (u64)pci_resource_start(dev->pci, 2));
  724. return -EBUSY;
  725. }
  726. static int saa7164_port_init(struct saa7164_dev *dev, int portnr)
  727. {
  728. struct saa7164_port *port = NULL;
  729. if ((portnr < 0) || (portnr >= SAA7164_MAX_PORTS))
  730. BUG();
  731. port = &dev->ports[portnr];
  732. port->dev = dev;
  733. port->nr = portnr;
  734. if ((portnr == SAA7164_PORT_TS1) || (portnr == SAA7164_PORT_TS2))
  735. port->type = SAA7164_MPEG_DVB;
  736. else
  737. if ((portnr == SAA7164_PORT_ENC1) || (portnr == SAA7164_PORT_ENC2)) {
  738. port->type = SAA7164_MPEG_ENCODER;
  739. /* We need a deferred interrupt handler for cmd handling */
  740. INIT_WORK(&port->workenc, saa7164_work_enchandler);
  741. } else if ((portnr == SAA7164_PORT_VBI1) || (portnr == SAA7164_PORT_VBI2)) {
  742. port->type = SAA7164_MPEG_VBI;
  743. /* We need a deferred interrupt handler for cmd handling */
  744. INIT_WORK(&port->workenc, saa7164_work_vbihandler);
  745. } else
  746. BUG();
  747. /* Init all the critical resources */
  748. mutex_init(&port->dvb.lock);
  749. INIT_LIST_HEAD(&port->dmaqueue.list);
  750. mutex_init(&port->dmaqueue_lock);
  751. INIT_LIST_HEAD(&port->list_buf_used.list);
  752. INIT_LIST_HEAD(&port->list_buf_free.list);
  753. init_waitqueue_head(&port->wait_read);
  754. saa7164_histogram_reset(&port->irq_interval, "irq intervals");
  755. saa7164_histogram_reset(&port->svc_interval, "deferred intervals");
  756. saa7164_histogram_reset(&port->irq_svc_interval,
  757. "irq to deferred intervals");
  758. saa7164_histogram_reset(&port->read_interval,
  759. "encoder/vbi read() intervals");
  760. saa7164_histogram_reset(&port->poll_interval,
  761. "encoder/vbi poll() intervals");
  762. return 0;
  763. }
  764. static int saa7164_dev_setup(struct saa7164_dev *dev)
  765. {
  766. int i;
  767. mutex_init(&dev->lock);
  768. atomic_inc(&dev->refcount);
  769. dev->nr = saa7164_devcount++;
  770. snprintf(dev->name, sizeof(dev->name), "saa7164[%d]", dev->nr);
  771. mutex_lock(&devlist);
  772. list_add_tail(&dev->devlist, &saa7164_devlist);
  773. mutex_unlock(&devlist);
  774. /* board config */
  775. dev->board = UNSET;
  776. if (card[dev->nr] < saa7164_bcount)
  777. dev->board = card[dev->nr];
  778. for (i = 0; UNSET == dev->board && i < saa7164_idcount; i++)
  779. if (dev->pci->subsystem_vendor == saa7164_subids[i].subvendor &&
  780. dev->pci->subsystem_device ==
  781. saa7164_subids[i].subdevice)
  782. dev->board = saa7164_subids[i].card;
  783. if (UNSET == dev->board) {
  784. dev->board = SAA7164_BOARD_UNKNOWN;
  785. saa7164_card_list(dev);
  786. }
  787. dev->pci_bus = dev->pci->bus->number;
  788. dev->pci_slot = PCI_SLOT(dev->pci->devfn);
  789. /* I2C Defaults / setup */
  790. dev->i2c_bus[0].dev = dev;
  791. dev->i2c_bus[0].nr = 0;
  792. dev->i2c_bus[1].dev = dev;
  793. dev->i2c_bus[1].nr = 1;
  794. dev->i2c_bus[2].dev = dev;
  795. dev->i2c_bus[2].nr = 2;
  796. /* Transport + Encoder ports 1, 2, 3, 4 - Defaults / setup */
  797. saa7164_port_init(dev, SAA7164_PORT_TS1);
  798. saa7164_port_init(dev, SAA7164_PORT_TS2);
  799. saa7164_port_init(dev, SAA7164_PORT_ENC1);
  800. saa7164_port_init(dev, SAA7164_PORT_ENC2);
  801. saa7164_port_init(dev, SAA7164_PORT_VBI1);
  802. saa7164_port_init(dev, SAA7164_PORT_VBI2);
  803. if (get_resources(dev) < 0) {
  804. printk(KERN_ERR "CORE %s No more PCIe resources for "
  805. "subsystem: %04x:%04x\n",
  806. dev->name, dev->pci->subsystem_vendor,
  807. dev->pci->subsystem_device);
  808. saa7164_devcount--;
  809. return -ENODEV;
  810. }
  811. /* PCI/e allocations */
  812. dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
  813. pci_resource_len(dev->pci, 0));
  814. dev->lmmio2 = ioremap(pci_resource_start(dev->pci, 2),
  815. pci_resource_len(dev->pci, 2));
  816. dev->bmmio = (u8 __iomem *)dev->lmmio;
  817. dev->bmmio2 = (u8 __iomem *)dev->lmmio2;
  818. /* Inerrupt and ack register locations offset of bmmio */
  819. dev->int_status = 0x183000 + 0xf80;
  820. dev->int_ack = 0x183000 + 0xf90;
  821. printk(KERN_INFO
  822. "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
  823. dev->name, dev->pci->subsystem_vendor,
  824. dev->pci->subsystem_device, saa7164_boards[dev->board].name,
  825. dev->board, card[dev->nr] == dev->board ?
  826. "insmod option" : "autodetected");
  827. saa7164_pci_quirks(dev);
  828. return 0;
  829. }
  830. static void saa7164_dev_unregister(struct saa7164_dev *dev)
  831. {
  832. dprintk(1, "%s()\n", __func__);
  833. release_mem_region(pci_resource_start(dev->pci, 0),
  834. pci_resource_len(dev->pci, 0));
  835. release_mem_region(pci_resource_start(dev->pci, 2),
  836. pci_resource_len(dev->pci, 2));
  837. if (!atomic_dec_and_test(&dev->refcount))
  838. return;
  839. iounmap(dev->lmmio);
  840. iounmap(dev->lmmio2);
  841. return;
  842. }
  843. #ifdef CONFIG_PROC_FS
  844. static int saa7164_proc_show(struct seq_file *m, void *v)
  845. {
  846. struct saa7164_dev *dev;
  847. struct tmComResBusInfo *b;
  848. struct list_head *list;
  849. int i, c;
  850. if (saa7164_devcount == 0)
  851. return 0;
  852. list_for_each(list, &saa7164_devlist) {
  853. dev = list_entry(list, struct saa7164_dev, devlist);
  854. seq_printf(m, "%s = %p\n", dev->name, dev);
  855. /* Lock the bus from any other access */
  856. b = &dev->bus;
  857. mutex_lock(&b->lock);
  858. seq_printf(m, " .m_pdwSetWritePos = 0x%x (0x%08x)\n",
  859. b->m_dwSetReadPos, saa7164_readl(b->m_dwSetReadPos));
  860. seq_printf(m, " .m_pdwSetReadPos = 0x%x (0x%08x)\n",
  861. b->m_dwSetWritePos, saa7164_readl(b->m_dwSetWritePos));
  862. seq_printf(m, " .m_pdwGetWritePos = 0x%x (0x%08x)\n",
  863. b->m_dwGetReadPos, saa7164_readl(b->m_dwGetReadPos));
  864. seq_printf(m, " .m_pdwGetReadPos = 0x%x (0x%08x)\n",
  865. b->m_dwGetWritePos, saa7164_readl(b->m_dwGetWritePos));
  866. c = 0;
  867. seq_printf(m, "\n Set Ring:\n");
  868. seq_printf(m, "\n addr 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n");
  869. for (i = 0; i < b->m_dwSizeSetRing; i++) {
  870. if (c == 0)
  871. seq_printf(m, " %04x:", i);
  872. seq_printf(m, " %02x", *(b->m_pdwSetRing + i));
  873. if (++c == 16) {
  874. seq_printf(m, "\n");
  875. c = 0;
  876. }
  877. }
  878. c = 0;
  879. seq_printf(m, "\n Get Ring:\n");
  880. seq_printf(m, "\n addr 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n");
  881. for (i = 0; i < b->m_dwSizeGetRing; i++) {
  882. if (c == 0)
  883. seq_printf(m, " %04x:", i);
  884. seq_printf(m, " %02x", *(b->m_pdwGetRing + i));
  885. if (++c == 16) {
  886. seq_printf(m, "\n");
  887. c = 0;
  888. }
  889. }
  890. mutex_unlock(&b->lock);
  891. }
  892. return 0;
  893. }
  894. static int saa7164_proc_open(struct inode *inode, struct file *filp)
  895. {
  896. return single_open(filp, saa7164_proc_show, NULL);
  897. }
  898. static const struct file_operations saa7164_proc_fops = {
  899. .open = saa7164_proc_open,
  900. .read = seq_read,
  901. .llseek = seq_lseek,
  902. .release = single_release,
  903. };
  904. static int saa7164_proc_create(void)
  905. {
  906. struct proc_dir_entry *pe;
  907. pe = proc_create("saa7164", S_IRUGO, NULL, &saa7164_proc_fops);
  908. if (!pe)
  909. return -ENOMEM;
  910. return 0;
  911. }
  912. #endif
  913. static int saa7164_thread_function(void *data)
  914. {
  915. struct saa7164_dev *dev = data;
  916. struct tmFwInfoStruct fwinfo;
  917. u64 last_poll_time = 0;
  918. dprintk(DBGLVL_THR, "thread started\n");
  919. set_freezable();
  920. while (1) {
  921. msleep_interruptible(100);
  922. if (kthread_should_stop())
  923. break;
  924. try_to_freeze();
  925. dprintk(DBGLVL_THR, "thread running\n");
  926. /* Dump the firmware debug message to console */
  927. /* Polling this costs us 1-2% of the arm CPU */
  928. /* convert this into a respnde to interrupt 0x7a */
  929. saa7164_api_collect_debug(dev);
  930. /* Monitor CPU load every 1 second */
  931. if ((last_poll_time + 1000 /* ms */) < jiffies_to_msecs(jiffies)) {
  932. saa7164_api_get_load_info(dev, &fwinfo);
  933. last_poll_time = jiffies_to_msecs(jiffies);
  934. }
  935. }
  936. dprintk(DBGLVL_THR, "thread exiting\n");
  937. return 0;
  938. }
  939. static int saa7164_initdev(struct pci_dev *pci_dev,
  940. const struct pci_device_id *pci_id)
  941. {
  942. struct saa7164_dev *dev;
  943. int err, i;
  944. u32 version;
  945. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  946. if (NULL == dev)
  947. return -ENOMEM;
  948. err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
  949. if (err < 0) {
  950. dev_err(&pci_dev->dev, "v4l2_device_register failed\n");
  951. goto fail_free;
  952. }
  953. /* pci init */
  954. dev->pci = pci_dev;
  955. if (pci_enable_device(pci_dev)) {
  956. err = -EIO;
  957. goto fail_free;
  958. }
  959. if (saa7164_dev_setup(dev) < 0) {
  960. err = -EINVAL;
  961. goto fail_free;
  962. }
  963. /* print pci info */
  964. dev->pci_rev = pci_dev->revision;
  965. pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
  966. printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
  967. "latency: %d, mmio: 0x%llx\n", dev->name,
  968. pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
  969. dev->pci_lat,
  970. (unsigned long long)pci_resource_start(pci_dev, 0));
  971. pci_set_master(pci_dev);
  972. /* TODO */
  973. if (!pci_dma_supported(pci_dev, 0xffffffff)) {
  974. printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
  975. err = -EIO;
  976. goto fail_irq;
  977. }
  978. err = request_irq(pci_dev->irq, saa7164_irq,
  979. IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
  980. if (err < 0) {
  981. printk(KERN_ERR "%s: can't get IRQ %d\n", dev->name,
  982. pci_dev->irq);
  983. err = -EIO;
  984. goto fail_irq;
  985. }
  986. pci_set_drvdata(pci_dev, dev);
  987. /* Init the internal command list */
  988. for (i = 0; i < SAA_CMD_MAX_MSG_UNITS; i++) {
  989. dev->cmds[i].seqno = i;
  990. dev->cmds[i].inuse = 0;
  991. mutex_init(&dev->cmds[i].lock);
  992. init_waitqueue_head(&dev->cmds[i].wait);
  993. }
  994. /* We need a deferred interrupt handler for cmd handling */
  995. INIT_WORK(&dev->workcmd, saa7164_work_cmdhandler);
  996. /* Only load the firmware if we know the board */
  997. if (dev->board != SAA7164_BOARD_UNKNOWN) {
  998. err = saa7164_downloadfirmware(dev);
  999. if (err < 0) {
  1000. printk(KERN_ERR
  1001. "Failed to boot firmware, no features "
  1002. "registered\n");
  1003. goto fail_fw;
  1004. }
  1005. saa7164_get_descriptors(dev);
  1006. saa7164_dumpregs(dev, 0);
  1007. saa7164_getcurrentfirmwareversion(dev);
  1008. saa7164_getfirmwarestatus(dev);
  1009. err = saa7164_bus_setup(dev);
  1010. if (err < 0)
  1011. printk(KERN_ERR
  1012. "Failed to setup the bus, will continue\n");
  1013. saa7164_bus_dump(dev);
  1014. /* Ping the running firmware via the command bus and get the
  1015. * firmware version, this checks the bus is running OK.
  1016. */
  1017. version = 0;
  1018. if (saa7164_api_get_fw_version(dev, &version) == SAA_OK)
  1019. dprintk(1, "Bus is operating correctly using "
  1020. "version %d.%d.%d.%d (0x%x)\n",
  1021. (version & 0x0000fc00) >> 10,
  1022. (version & 0x000003e0) >> 5,
  1023. (version & 0x0000001f),
  1024. (version & 0xffff0000) >> 16,
  1025. version);
  1026. else
  1027. printk(KERN_ERR
  1028. "Failed to communicate with the firmware\n");
  1029. /* Bring up the I2C buses */
  1030. saa7164_i2c_register(&dev->i2c_bus[0]);
  1031. saa7164_i2c_register(&dev->i2c_bus[1]);
  1032. saa7164_i2c_register(&dev->i2c_bus[2]);
  1033. saa7164_gpio_setup(dev);
  1034. saa7164_card_setup(dev);
  1035. /* Parse the dynamic device configuration, find various
  1036. * media endpoints (MPEG, WMV, PS, TS) and cache their
  1037. * configuration details into the driver, so we can
  1038. * reference them later during simething_register() func,
  1039. * interrupt handlers, deferred work handlers etc.
  1040. */
  1041. saa7164_api_enum_subdevs(dev);
  1042. /* Begin to create the video sub-systems and register funcs */
  1043. if (saa7164_boards[dev->board].porta == SAA7164_MPEG_DVB) {
  1044. if (saa7164_dvb_register(&dev->ports[SAA7164_PORT_TS1]) < 0) {
  1045. printk(KERN_ERR "%s() Failed to register "
  1046. "dvb adapters on porta\n",
  1047. __func__);
  1048. }
  1049. }
  1050. if (saa7164_boards[dev->board].portb == SAA7164_MPEG_DVB) {
  1051. if (saa7164_dvb_register(&dev->ports[SAA7164_PORT_TS2]) < 0) {
  1052. printk(KERN_ERR"%s() Failed to register "
  1053. "dvb adapters on portb\n",
  1054. __func__);
  1055. }
  1056. }
  1057. if (saa7164_boards[dev->board].portc == SAA7164_MPEG_ENCODER) {
  1058. if (saa7164_encoder_register(&dev->ports[SAA7164_PORT_ENC1]) < 0) {
  1059. printk(KERN_ERR"%s() Failed to register "
  1060. "mpeg encoder\n", __func__);
  1061. }
  1062. }
  1063. if (saa7164_boards[dev->board].portd == SAA7164_MPEG_ENCODER) {
  1064. if (saa7164_encoder_register(&dev->ports[SAA7164_PORT_ENC2]) < 0) {
  1065. printk(KERN_ERR"%s() Failed to register "
  1066. "mpeg encoder\n", __func__);
  1067. }
  1068. }
  1069. if (saa7164_boards[dev->board].porte == SAA7164_MPEG_VBI) {
  1070. if (saa7164_vbi_register(&dev->ports[SAA7164_PORT_VBI1]) < 0) {
  1071. printk(KERN_ERR"%s() Failed to register "
  1072. "vbi device\n", __func__);
  1073. }
  1074. }
  1075. if (saa7164_boards[dev->board].portf == SAA7164_MPEG_VBI) {
  1076. if (saa7164_vbi_register(&dev->ports[SAA7164_PORT_VBI2]) < 0) {
  1077. printk(KERN_ERR"%s() Failed to register "
  1078. "vbi device\n", __func__);
  1079. }
  1080. }
  1081. saa7164_api_set_debug(dev, fw_debug);
  1082. if (fw_debug) {
  1083. dev->kthread = kthread_run(saa7164_thread_function, dev,
  1084. "saa7164 debug");
  1085. if (!dev->kthread)
  1086. printk(KERN_ERR "%s() Failed to create "
  1087. "debug kernel thread\n", __func__);
  1088. }
  1089. } /* != BOARD_UNKNOWN */
  1090. else
  1091. printk(KERN_ERR "%s() Unsupported board detected, "
  1092. "registering without firmware\n", __func__);
  1093. dprintk(1, "%s() parameter debug = %d\n", __func__, saa_debug);
  1094. dprintk(1, "%s() parameter waitsecs = %d\n", __func__, waitsecs);
  1095. fail_fw:
  1096. return 0;
  1097. fail_irq:
  1098. saa7164_dev_unregister(dev);
  1099. fail_free:
  1100. v4l2_device_unregister(&dev->v4l2_dev);
  1101. kfree(dev);
  1102. return err;
  1103. }
  1104. static void saa7164_shutdown(struct saa7164_dev *dev)
  1105. {
  1106. dprintk(1, "%s()\n", __func__);
  1107. }
  1108. static void saa7164_finidev(struct pci_dev *pci_dev)
  1109. {
  1110. struct saa7164_dev *dev = pci_get_drvdata(pci_dev);
  1111. if (dev->board != SAA7164_BOARD_UNKNOWN) {
  1112. if (fw_debug && dev->kthread) {
  1113. kthread_stop(dev->kthread);
  1114. dev->kthread = NULL;
  1115. }
  1116. if (dev->firmwareloaded)
  1117. saa7164_api_set_debug(dev, 0x00);
  1118. }
  1119. saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1],
  1120. &dev->ports[SAA7164_PORT_ENC1].irq_interval);
  1121. saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1],
  1122. &dev->ports[SAA7164_PORT_ENC1].svc_interval);
  1123. saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1],
  1124. &dev->ports[SAA7164_PORT_ENC1].irq_svc_interval);
  1125. saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1],
  1126. &dev->ports[SAA7164_PORT_ENC1].read_interval);
  1127. saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1],
  1128. &dev->ports[SAA7164_PORT_ENC1].poll_interval);
  1129. saa7164_histogram_print(&dev->ports[SAA7164_PORT_VBI1],
  1130. &dev->ports[SAA7164_PORT_VBI1].read_interval);
  1131. saa7164_histogram_print(&dev->ports[SAA7164_PORT_VBI2],
  1132. &dev->ports[SAA7164_PORT_VBI2].poll_interval);
  1133. saa7164_shutdown(dev);
  1134. if (saa7164_boards[dev->board].porta == SAA7164_MPEG_DVB)
  1135. saa7164_dvb_unregister(&dev->ports[SAA7164_PORT_TS1]);
  1136. if (saa7164_boards[dev->board].portb == SAA7164_MPEG_DVB)
  1137. saa7164_dvb_unregister(&dev->ports[SAA7164_PORT_TS2]);
  1138. if (saa7164_boards[dev->board].portc == SAA7164_MPEG_ENCODER)
  1139. saa7164_encoder_unregister(&dev->ports[SAA7164_PORT_ENC1]);
  1140. if (saa7164_boards[dev->board].portd == SAA7164_MPEG_ENCODER)
  1141. saa7164_encoder_unregister(&dev->ports[SAA7164_PORT_ENC2]);
  1142. if (saa7164_boards[dev->board].porte == SAA7164_MPEG_VBI)
  1143. saa7164_vbi_unregister(&dev->ports[SAA7164_PORT_VBI1]);
  1144. if (saa7164_boards[dev->board].portf == SAA7164_MPEG_VBI)
  1145. saa7164_vbi_unregister(&dev->ports[SAA7164_PORT_VBI2]);
  1146. saa7164_i2c_unregister(&dev->i2c_bus[0]);
  1147. saa7164_i2c_unregister(&dev->i2c_bus[1]);
  1148. saa7164_i2c_unregister(&dev->i2c_bus[2]);
  1149. pci_disable_device(pci_dev);
  1150. /* unregister stuff */
  1151. free_irq(pci_dev->irq, dev);
  1152. pci_set_drvdata(pci_dev, NULL);
  1153. mutex_lock(&devlist);
  1154. list_del(&dev->devlist);
  1155. mutex_unlock(&devlist);
  1156. saa7164_dev_unregister(dev);
  1157. v4l2_device_unregister(&dev->v4l2_dev);
  1158. kfree(dev);
  1159. }
  1160. static struct pci_device_id saa7164_pci_tbl[] = {
  1161. {
  1162. /* SAA7164 */
  1163. .vendor = 0x1131,
  1164. .device = 0x7164,
  1165. .subvendor = PCI_ANY_ID,
  1166. .subdevice = PCI_ANY_ID,
  1167. }, {
  1168. /* --- end of list --- */
  1169. }
  1170. };
  1171. MODULE_DEVICE_TABLE(pci, saa7164_pci_tbl);
  1172. static struct pci_driver saa7164_pci_driver = {
  1173. .name = "saa7164",
  1174. .id_table = saa7164_pci_tbl,
  1175. .probe = saa7164_initdev,
  1176. .remove = saa7164_finidev,
  1177. /* TODO */
  1178. .suspend = NULL,
  1179. .resume = NULL,
  1180. };
  1181. static int __init saa7164_init(void)
  1182. {
  1183. printk(KERN_INFO "saa7164 driver loaded\n");
  1184. #ifdef CONFIG_PROC_FS
  1185. saa7164_proc_create();
  1186. #endif
  1187. return pci_register_driver(&saa7164_pci_driver);
  1188. }
  1189. static void __exit saa7164_fini(void)
  1190. {
  1191. #ifdef CONFIG_PROC_FS
  1192. remove_proc_entry("saa7164", NULL);
  1193. #endif
  1194. pci_unregister_driver(&saa7164_pci_driver);
  1195. }
  1196. module_init(saa7164_init);
  1197. module_exit(saa7164_fini);