saa7191.c 15 KB

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  1. /*
  2. * saa7191.c - Philips SAA7191 video decoder driver
  3. *
  4. * Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
  5. * Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/errno.h>
  13. #include <linux/fs.h>
  14. #include <linux/init.h>
  15. #include <linux/kernel.h>
  16. #include <linux/major.h>
  17. #include <linux/module.h>
  18. #include <linux/mm.h>
  19. #include <linux/slab.h>
  20. #include <linux/videodev2.h>
  21. #include <linux/i2c.h>
  22. #include <media/v4l2-device.h>
  23. #include "saa7191.h"
  24. #define SAA7191_MODULE_VERSION "0.0.5"
  25. MODULE_DESCRIPTION("Philips SAA7191 video decoder driver");
  26. MODULE_VERSION(SAA7191_MODULE_VERSION);
  27. MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>");
  28. MODULE_LICENSE("GPL");
  29. // #define SAA7191_DEBUG
  30. #ifdef SAA7191_DEBUG
  31. #define dprintk(x...) printk("SAA7191: " x);
  32. #else
  33. #define dprintk(x...)
  34. #endif
  35. #define SAA7191_SYNC_COUNT 30
  36. #define SAA7191_SYNC_DELAY 100 /* milliseconds */
  37. struct saa7191 {
  38. struct v4l2_subdev sd;
  39. /* the register values are stored here as the actual
  40. * I2C-registers are write-only */
  41. u8 reg[25];
  42. int input;
  43. v4l2_std_id norm;
  44. };
  45. static inline struct saa7191 *to_saa7191(struct v4l2_subdev *sd)
  46. {
  47. return container_of(sd, struct saa7191, sd);
  48. }
  49. static const u8 initseq[] = {
  50. 0, /* Subaddress */
  51. 0x50, /* (0x50) SAA7191_REG_IDEL */
  52. /* 50 Hz signal timing */
  53. 0x30, /* (0x30) SAA7191_REG_HSYB */
  54. 0x00, /* (0x00) SAA7191_REG_HSYS */
  55. 0xe8, /* (0xe8) SAA7191_REG_HCLB */
  56. 0xb6, /* (0xb6) SAA7191_REG_HCLS */
  57. 0xf4, /* (0xf4) SAA7191_REG_HPHI */
  58. /* control */
  59. SAA7191_LUMA_APER_1, /* (0x01) SAA7191_REG_LUMA - CVBS mode */
  60. 0x00, /* (0x00) SAA7191_REG_HUEC */
  61. 0xf8, /* (0xf8) SAA7191_REG_CKTQ */
  62. 0xf8, /* (0xf8) SAA7191_REG_CKTS */
  63. 0x90, /* (0x90) SAA7191_REG_PLSE */
  64. 0x90, /* (0x90) SAA7191_REG_SESE */
  65. 0x00, /* (0x00) SAA7191_REG_GAIN */
  66. SAA7191_STDC_NFEN | SAA7191_STDC_HRMV, /* (0x0c) SAA7191_REG_STDC
  67. * - not SECAM,
  68. * slow time constant */
  69. SAA7191_IOCK_OEDC | SAA7191_IOCK_OEHS | SAA7191_IOCK_OEVS
  70. | SAA7191_IOCK_OEDY, /* (0x78) SAA7191_REG_IOCK
  71. * - chroma from CVBS, GPSW1 & 2 off */
  72. SAA7191_CTL3_AUFD | SAA7191_CTL3_SCEN | SAA7191_CTL3_OFTS
  73. | SAA7191_CTL3_YDEL0, /* (0x99) SAA7191_REG_CTL3
  74. * - automatic field detection */
  75. 0x00, /* (0x00) SAA7191_REG_CTL4 */
  76. 0x2c, /* (0x2c) SAA7191_REG_CHCV - PAL nominal value */
  77. 0x00, /* unused */
  78. 0x00, /* unused */
  79. /* 60 Hz signal timing */
  80. 0x34, /* (0x34) SAA7191_REG_HS6B */
  81. 0x0a, /* (0x0a) SAA7191_REG_HS6S */
  82. 0xf4, /* (0xf4) SAA7191_REG_HC6B */
  83. 0xce, /* (0xce) SAA7191_REG_HC6S */
  84. 0xf4, /* (0xf4) SAA7191_REG_HP6I */
  85. };
  86. /* SAA7191 register handling */
  87. static u8 saa7191_read_reg(struct v4l2_subdev *sd, u8 reg)
  88. {
  89. return to_saa7191(sd)->reg[reg];
  90. }
  91. static int saa7191_read_status(struct v4l2_subdev *sd, u8 *value)
  92. {
  93. struct i2c_client *client = v4l2_get_subdevdata(sd);
  94. int ret;
  95. ret = i2c_master_recv(client, value, 1);
  96. if (ret < 0) {
  97. printk(KERN_ERR "SAA7191: saa7191_read_status(): read failed\n");
  98. return ret;
  99. }
  100. return 0;
  101. }
  102. static int saa7191_write_reg(struct v4l2_subdev *sd, u8 reg, u8 value)
  103. {
  104. struct i2c_client *client = v4l2_get_subdevdata(sd);
  105. to_saa7191(sd)->reg[reg] = value;
  106. return i2c_smbus_write_byte_data(client, reg, value);
  107. }
  108. /* the first byte of data must be the first subaddress number (register) */
  109. static int saa7191_write_block(struct v4l2_subdev *sd,
  110. u8 length, const u8 *data)
  111. {
  112. struct i2c_client *client = v4l2_get_subdevdata(sd);
  113. struct saa7191 *decoder = to_saa7191(sd);
  114. int i;
  115. int ret;
  116. for (i = 0; i < (length - 1); i++) {
  117. decoder->reg[data[0] + i] = data[i + 1];
  118. }
  119. ret = i2c_master_send(client, data, length);
  120. if (ret < 0) {
  121. printk(KERN_ERR "SAA7191: saa7191_write_block(): "
  122. "write failed\n");
  123. return ret;
  124. }
  125. return 0;
  126. }
  127. /* Helper functions */
  128. static int saa7191_s_routing(struct v4l2_subdev *sd,
  129. u32 input, u32 output, u32 config)
  130. {
  131. struct saa7191 *decoder = to_saa7191(sd);
  132. u8 luma = saa7191_read_reg(sd, SAA7191_REG_LUMA);
  133. u8 iock = saa7191_read_reg(sd, SAA7191_REG_IOCK);
  134. int err;
  135. switch (input) {
  136. case SAA7191_INPUT_COMPOSITE: /* Set Composite input */
  137. iock &= ~(SAA7191_IOCK_CHRS | SAA7191_IOCK_GPSW1
  138. | SAA7191_IOCK_GPSW2);
  139. /* Chrominance trap active */
  140. luma &= ~SAA7191_LUMA_BYPS;
  141. break;
  142. case SAA7191_INPUT_SVIDEO: /* Set S-Video input */
  143. iock |= SAA7191_IOCK_CHRS | SAA7191_IOCK_GPSW2;
  144. /* Chrominance trap bypassed */
  145. luma |= SAA7191_LUMA_BYPS;
  146. break;
  147. default:
  148. return -EINVAL;
  149. }
  150. err = saa7191_write_reg(sd, SAA7191_REG_LUMA, luma);
  151. if (err)
  152. return -EIO;
  153. err = saa7191_write_reg(sd, SAA7191_REG_IOCK, iock);
  154. if (err)
  155. return -EIO;
  156. decoder->input = input;
  157. return 0;
  158. }
  159. static int saa7191_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
  160. {
  161. struct saa7191 *decoder = to_saa7191(sd);
  162. u8 stdc = saa7191_read_reg(sd, SAA7191_REG_STDC);
  163. u8 ctl3 = saa7191_read_reg(sd, SAA7191_REG_CTL3);
  164. u8 chcv = saa7191_read_reg(sd, SAA7191_REG_CHCV);
  165. int err;
  166. if (norm & V4L2_STD_PAL) {
  167. stdc &= ~SAA7191_STDC_SECS;
  168. ctl3 &= ~(SAA7191_CTL3_AUFD | SAA7191_CTL3_FSEL);
  169. chcv = SAA7191_CHCV_PAL;
  170. } else if (norm & V4L2_STD_NTSC) {
  171. stdc &= ~SAA7191_STDC_SECS;
  172. ctl3 &= ~SAA7191_CTL3_AUFD;
  173. ctl3 |= SAA7191_CTL3_FSEL;
  174. chcv = SAA7191_CHCV_NTSC;
  175. } else if (norm & V4L2_STD_SECAM) {
  176. stdc |= SAA7191_STDC_SECS;
  177. ctl3 &= ~(SAA7191_CTL3_AUFD | SAA7191_CTL3_FSEL);
  178. chcv = SAA7191_CHCV_PAL;
  179. } else {
  180. return -EINVAL;
  181. }
  182. err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
  183. if (err)
  184. return -EIO;
  185. err = saa7191_write_reg(sd, SAA7191_REG_STDC, stdc);
  186. if (err)
  187. return -EIO;
  188. err = saa7191_write_reg(sd, SAA7191_REG_CHCV, chcv);
  189. if (err)
  190. return -EIO;
  191. decoder->norm = norm;
  192. dprintk("ctl3: %02x stdc: %02x chcv: %02x\n", ctl3,
  193. stdc, chcv);
  194. dprintk("norm: %llx\n", norm);
  195. return 0;
  196. }
  197. static int saa7191_wait_for_signal(struct v4l2_subdev *sd, u8 *status)
  198. {
  199. int i = 0;
  200. dprintk("Checking for signal...\n");
  201. for (i = 0; i < SAA7191_SYNC_COUNT; i++) {
  202. if (saa7191_read_status(sd, status))
  203. return -EIO;
  204. if (((*status) & SAA7191_STATUS_HLCK) == 0) {
  205. dprintk("Signal found\n");
  206. return 0;
  207. }
  208. msleep(SAA7191_SYNC_DELAY);
  209. }
  210. dprintk("No signal\n");
  211. return -EBUSY;
  212. }
  213. static int saa7191_querystd(struct v4l2_subdev *sd, v4l2_std_id *norm)
  214. {
  215. struct saa7191 *decoder = to_saa7191(sd);
  216. u8 stdc = saa7191_read_reg(sd, SAA7191_REG_STDC);
  217. u8 ctl3 = saa7191_read_reg(sd, SAA7191_REG_CTL3);
  218. u8 status;
  219. v4l2_std_id old_norm = decoder->norm;
  220. int err = 0;
  221. dprintk("SAA7191 extended signal auto-detection...\n");
  222. *norm &= V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM;
  223. stdc &= ~SAA7191_STDC_SECS;
  224. ctl3 &= ~(SAA7191_CTL3_FSEL);
  225. err = saa7191_write_reg(sd, SAA7191_REG_STDC, stdc);
  226. if (err) {
  227. err = -EIO;
  228. goto out;
  229. }
  230. err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
  231. if (err) {
  232. err = -EIO;
  233. goto out;
  234. }
  235. ctl3 |= SAA7191_CTL3_AUFD;
  236. err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
  237. if (err) {
  238. err = -EIO;
  239. goto out;
  240. }
  241. msleep(SAA7191_SYNC_DELAY);
  242. err = saa7191_wait_for_signal(sd, &status);
  243. if (err)
  244. goto out;
  245. if (status & SAA7191_STATUS_FIDT) {
  246. /* 60Hz signal -> NTSC */
  247. dprintk("60Hz signal: NTSC\n");
  248. *norm &= V4L2_STD_NTSC;
  249. return 0;
  250. }
  251. /* 50Hz signal */
  252. dprintk("50Hz signal: Trying PAL...\n");
  253. /* try PAL first */
  254. err = saa7191_s_std(sd, V4L2_STD_PAL);
  255. if (err)
  256. goto out;
  257. msleep(SAA7191_SYNC_DELAY);
  258. err = saa7191_wait_for_signal(sd, &status);
  259. if (err)
  260. goto out;
  261. /* not 50Hz ? */
  262. if (status & SAA7191_STATUS_FIDT) {
  263. dprintk("No 50Hz signal\n");
  264. saa7191_s_std(sd, old_norm);
  265. *norm = V4L2_STD_UNKNOWN;
  266. return 0;
  267. }
  268. if (status & SAA7191_STATUS_CODE) {
  269. dprintk("PAL\n");
  270. *norm &= V4L2_STD_PAL;
  271. return saa7191_s_std(sd, old_norm);
  272. }
  273. dprintk("No color detected with PAL - Trying SECAM...\n");
  274. /* no color detected ? -> try SECAM */
  275. err = saa7191_s_std(sd, V4L2_STD_SECAM);
  276. if (err)
  277. goto out;
  278. msleep(SAA7191_SYNC_DELAY);
  279. err = saa7191_wait_for_signal(sd, &status);
  280. if (err)
  281. goto out;
  282. /* not 50Hz ? */
  283. if (status & SAA7191_STATUS_FIDT) {
  284. dprintk("No 50Hz signal\n");
  285. *norm = V4L2_STD_UNKNOWN;
  286. goto out;
  287. }
  288. if (status & SAA7191_STATUS_CODE) {
  289. /* Color detected -> SECAM */
  290. dprintk("SECAM\n");
  291. *norm &= V4L2_STD_SECAM;
  292. return saa7191_s_std(sd, old_norm);
  293. }
  294. dprintk("No color detected with SECAM - Going back to PAL.\n");
  295. *norm = V4L2_STD_UNKNOWN;
  296. out:
  297. return saa7191_s_std(sd, old_norm);
  298. }
  299. static int saa7191_autodetect_norm(struct v4l2_subdev *sd)
  300. {
  301. u8 status;
  302. dprintk("SAA7191 signal auto-detection...\n");
  303. dprintk("Reading status...\n");
  304. if (saa7191_read_status(sd, &status))
  305. return -EIO;
  306. dprintk("Checking for signal...\n");
  307. /* no signal ? */
  308. if (status & SAA7191_STATUS_HLCK) {
  309. dprintk("No signal\n");
  310. return -EBUSY;
  311. }
  312. dprintk("Signal found\n");
  313. if (status & SAA7191_STATUS_FIDT) {
  314. /* 60hz signal -> NTSC */
  315. dprintk("NTSC\n");
  316. return saa7191_s_std(sd, V4L2_STD_NTSC);
  317. } else {
  318. /* 50hz signal -> PAL */
  319. dprintk("PAL\n");
  320. return saa7191_s_std(sd, V4L2_STD_PAL);
  321. }
  322. }
  323. static int saa7191_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
  324. {
  325. u8 reg;
  326. int ret = 0;
  327. switch (ctrl->id) {
  328. case SAA7191_CONTROL_BANDPASS:
  329. case SAA7191_CONTROL_BANDPASS_WEIGHT:
  330. case SAA7191_CONTROL_CORING:
  331. reg = saa7191_read_reg(sd, SAA7191_REG_LUMA);
  332. switch (ctrl->id) {
  333. case SAA7191_CONTROL_BANDPASS:
  334. ctrl->value = ((s32)reg & SAA7191_LUMA_BPSS_MASK)
  335. >> SAA7191_LUMA_BPSS_SHIFT;
  336. break;
  337. case SAA7191_CONTROL_BANDPASS_WEIGHT:
  338. ctrl->value = ((s32)reg & SAA7191_LUMA_APER_MASK)
  339. >> SAA7191_LUMA_APER_SHIFT;
  340. break;
  341. case SAA7191_CONTROL_CORING:
  342. ctrl->value = ((s32)reg & SAA7191_LUMA_CORI_MASK)
  343. >> SAA7191_LUMA_CORI_SHIFT;
  344. break;
  345. }
  346. break;
  347. case SAA7191_CONTROL_FORCE_COLOUR:
  348. case SAA7191_CONTROL_CHROMA_GAIN:
  349. reg = saa7191_read_reg(sd, SAA7191_REG_GAIN);
  350. if (ctrl->id == SAA7191_CONTROL_FORCE_COLOUR)
  351. ctrl->value = ((s32)reg & SAA7191_GAIN_COLO) ? 1 : 0;
  352. else
  353. ctrl->value = ((s32)reg & SAA7191_GAIN_LFIS_MASK)
  354. >> SAA7191_GAIN_LFIS_SHIFT;
  355. break;
  356. case V4L2_CID_HUE:
  357. reg = saa7191_read_reg(sd, SAA7191_REG_HUEC);
  358. if (reg < 0x80)
  359. reg += 0x80;
  360. else
  361. reg -= 0x80;
  362. ctrl->value = (s32)reg;
  363. break;
  364. case SAA7191_CONTROL_VTRC:
  365. reg = saa7191_read_reg(sd, SAA7191_REG_STDC);
  366. ctrl->value = ((s32)reg & SAA7191_STDC_VTRC) ? 1 : 0;
  367. break;
  368. case SAA7191_CONTROL_LUMA_DELAY:
  369. reg = saa7191_read_reg(sd, SAA7191_REG_CTL3);
  370. ctrl->value = ((s32)reg & SAA7191_CTL3_YDEL_MASK)
  371. >> SAA7191_CTL3_YDEL_SHIFT;
  372. if (ctrl->value >= 4)
  373. ctrl->value -= 8;
  374. break;
  375. case SAA7191_CONTROL_VNR:
  376. reg = saa7191_read_reg(sd, SAA7191_REG_CTL4);
  377. ctrl->value = ((s32)reg & SAA7191_CTL4_VNOI_MASK)
  378. >> SAA7191_CTL4_VNOI_SHIFT;
  379. break;
  380. default:
  381. ret = -EINVAL;
  382. }
  383. return ret;
  384. }
  385. static int saa7191_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
  386. {
  387. u8 reg;
  388. int ret = 0;
  389. switch (ctrl->id) {
  390. case SAA7191_CONTROL_BANDPASS:
  391. case SAA7191_CONTROL_BANDPASS_WEIGHT:
  392. case SAA7191_CONTROL_CORING:
  393. reg = saa7191_read_reg(sd, SAA7191_REG_LUMA);
  394. switch (ctrl->id) {
  395. case SAA7191_CONTROL_BANDPASS:
  396. reg &= ~SAA7191_LUMA_BPSS_MASK;
  397. reg |= (ctrl->value << SAA7191_LUMA_BPSS_SHIFT)
  398. & SAA7191_LUMA_BPSS_MASK;
  399. break;
  400. case SAA7191_CONTROL_BANDPASS_WEIGHT:
  401. reg &= ~SAA7191_LUMA_APER_MASK;
  402. reg |= (ctrl->value << SAA7191_LUMA_APER_SHIFT)
  403. & SAA7191_LUMA_APER_MASK;
  404. break;
  405. case SAA7191_CONTROL_CORING:
  406. reg &= ~SAA7191_LUMA_CORI_MASK;
  407. reg |= (ctrl->value << SAA7191_LUMA_CORI_SHIFT)
  408. & SAA7191_LUMA_CORI_MASK;
  409. break;
  410. }
  411. ret = saa7191_write_reg(sd, SAA7191_REG_LUMA, reg);
  412. break;
  413. case SAA7191_CONTROL_FORCE_COLOUR:
  414. case SAA7191_CONTROL_CHROMA_GAIN:
  415. reg = saa7191_read_reg(sd, SAA7191_REG_GAIN);
  416. if (ctrl->id == SAA7191_CONTROL_FORCE_COLOUR) {
  417. if (ctrl->value)
  418. reg |= SAA7191_GAIN_COLO;
  419. else
  420. reg &= ~SAA7191_GAIN_COLO;
  421. } else {
  422. reg &= ~SAA7191_GAIN_LFIS_MASK;
  423. reg |= (ctrl->value << SAA7191_GAIN_LFIS_SHIFT)
  424. & SAA7191_GAIN_LFIS_MASK;
  425. }
  426. ret = saa7191_write_reg(sd, SAA7191_REG_GAIN, reg);
  427. break;
  428. case V4L2_CID_HUE:
  429. reg = ctrl->value & 0xff;
  430. if (reg < 0x80)
  431. reg += 0x80;
  432. else
  433. reg -= 0x80;
  434. ret = saa7191_write_reg(sd, SAA7191_REG_HUEC, reg);
  435. break;
  436. case SAA7191_CONTROL_VTRC:
  437. reg = saa7191_read_reg(sd, SAA7191_REG_STDC);
  438. if (ctrl->value)
  439. reg |= SAA7191_STDC_VTRC;
  440. else
  441. reg &= ~SAA7191_STDC_VTRC;
  442. ret = saa7191_write_reg(sd, SAA7191_REG_STDC, reg);
  443. break;
  444. case SAA7191_CONTROL_LUMA_DELAY: {
  445. s32 value = ctrl->value;
  446. if (value < 0)
  447. value += 8;
  448. reg = saa7191_read_reg(sd, SAA7191_REG_CTL3);
  449. reg &= ~SAA7191_CTL3_YDEL_MASK;
  450. reg |= (value << SAA7191_CTL3_YDEL_SHIFT)
  451. & SAA7191_CTL3_YDEL_MASK;
  452. ret = saa7191_write_reg(sd, SAA7191_REG_CTL3, reg);
  453. break;
  454. }
  455. case SAA7191_CONTROL_VNR:
  456. reg = saa7191_read_reg(sd, SAA7191_REG_CTL4);
  457. reg &= ~SAA7191_CTL4_VNOI_MASK;
  458. reg |= (ctrl->value << SAA7191_CTL4_VNOI_SHIFT)
  459. & SAA7191_CTL4_VNOI_MASK;
  460. ret = saa7191_write_reg(sd, SAA7191_REG_CTL4, reg);
  461. break;
  462. default:
  463. ret = -EINVAL;
  464. }
  465. return ret;
  466. }
  467. /* I2C-interface */
  468. static int saa7191_g_input_status(struct v4l2_subdev *sd, u32 *status)
  469. {
  470. u8 status_reg;
  471. int res = V4L2_IN_ST_NO_SIGNAL;
  472. if (saa7191_read_status(sd, &status_reg))
  473. return -EIO;
  474. if ((status_reg & SAA7191_STATUS_HLCK) == 0)
  475. res = 0;
  476. if (!(status_reg & SAA7191_STATUS_CODE))
  477. res |= V4L2_IN_ST_NO_COLOR;
  478. *status = res;
  479. return 0;
  480. }
  481. /* ----------------------------------------------------------------------- */
  482. static const struct v4l2_subdev_core_ops saa7191_core_ops = {
  483. .g_ctrl = saa7191_g_ctrl,
  484. .s_ctrl = saa7191_s_ctrl,
  485. .s_std = saa7191_s_std,
  486. };
  487. static const struct v4l2_subdev_video_ops saa7191_video_ops = {
  488. .s_routing = saa7191_s_routing,
  489. .querystd = saa7191_querystd,
  490. .g_input_status = saa7191_g_input_status,
  491. };
  492. static const struct v4l2_subdev_ops saa7191_ops = {
  493. .core = &saa7191_core_ops,
  494. .video = &saa7191_video_ops,
  495. };
  496. static int saa7191_probe(struct i2c_client *client,
  497. const struct i2c_device_id *id)
  498. {
  499. int err = 0;
  500. struct saa7191 *decoder;
  501. struct v4l2_subdev *sd;
  502. v4l_info(client, "chip found @ 0x%x (%s)\n",
  503. client->addr << 1, client->adapter->name);
  504. decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
  505. if (!decoder)
  506. return -ENOMEM;
  507. sd = &decoder->sd;
  508. v4l2_i2c_subdev_init(sd, client, &saa7191_ops);
  509. err = saa7191_write_block(sd, sizeof(initseq), initseq);
  510. if (err) {
  511. printk(KERN_ERR "SAA7191 initialization failed\n");
  512. return err;
  513. }
  514. printk(KERN_INFO "SAA7191 initialized\n");
  515. decoder->input = SAA7191_INPUT_COMPOSITE;
  516. decoder->norm = V4L2_STD_PAL;
  517. err = saa7191_autodetect_norm(sd);
  518. if (err && (err != -EBUSY))
  519. printk(KERN_ERR "SAA7191: Signal auto-detection failed\n");
  520. return 0;
  521. }
  522. static int saa7191_remove(struct i2c_client *client)
  523. {
  524. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  525. v4l2_device_unregister_subdev(sd);
  526. return 0;
  527. }
  528. static const struct i2c_device_id saa7191_id[] = {
  529. { "saa7191", 0 },
  530. { }
  531. };
  532. MODULE_DEVICE_TABLE(i2c, saa7191_id);
  533. static struct i2c_driver saa7191_driver = {
  534. .driver = {
  535. .owner = THIS_MODULE,
  536. .name = "saa7191",
  537. },
  538. .probe = saa7191_probe,
  539. .remove = saa7191_remove,
  540. .id_table = saa7191_id,
  541. };
  542. module_i2c_driver(saa7191_driver);