adv7343.c 13 KB

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  1. /*
  2. * adv7343 - ADV7343 Video Encoder Driver
  3. *
  4. * The encoder hardware does not support SECAM.
  5. *
  6. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2.
  11. *
  12. * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/ctype.h>
  20. #include <linux/slab.h>
  21. #include <linux/i2c.h>
  22. #include <linux/device.h>
  23. #include <linux/delay.h>
  24. #include <linux/module.h>
  25. #include <linux/videodev2.h>
  26. #include <linux/uaccess.h>
  27. #include <media/adv7343.h>
  28. #include <media/v4l2-async.h>
  29. #include <media/v4l2-device.h>
  30. #include <media/v4l2-ctrls.h>
  31. #include <media/v4l2-of.h>
  32. #include "adv7343_regs.h"
  33. MODULE_DESCRIPTION("ADV7343 video encoder driver");
  34. MODULE_LICENSE("GPL");
  35. static int debug;
  36. module_param(debug, int, 0644);
  37. MODULE_PARM_DESC(debug, "Debug level 0-1");
  38. struct adv7343_state {
  39. struct v4l2_subdev sd;
  40. struct v4l2_ctrl_handler hdl;
  41. const struct adv7343_platform_data *pdata;
  42. u8 reg00;
  43. u8 reg01;
  44. u8 reg02;
  45. u8 reg35;
  46. u8 reg80;
  47. u8 reg82;
  48. u32 output;
  49. v4l2_std_id std;
  50. };
  51. static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
  52. {
  53. return container_of(sd, struct adv7343_state, sd);
  54. }
  55. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  56. {
  57. return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
  58. }
  59. static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
  60. {
  61. struct i2c_client *client = v4l2_get_subdevdata(sd);
  62. return i2c_smbus_write_byte_data(client, reg, value);
  63. }
  64. static const u8 adv7343_init_reg_val[] = {
  65. ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
  66. ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
  67. ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
  68. ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
  69. ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
  70. ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
  71. ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
  72. ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
  73. ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
  74. ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
  75. ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
  76. ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
  77. ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
  78. ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
  79. ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
  80. ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
  81. ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
  82. ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
  83. ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
  84. ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
  85. };
  86. /*
  87. * 2^32
  88. * FSC(reg) = FSC (HZ) * --------
  89. * 27000000
  90. */
  91. static const struct adv7343_std_info stdinfo[] = {
  92. {
  93. /* FSC(Hz) = 3,579,545.45 Hz */
  94. SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
  95. }, {
  96. /* FSC(Hz) = 3,575,611.00 Hz */
  97. SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
  98. }, {
  99. /* FSC(Hz) = 3,582,056.00 */
  100. SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
  101. }, {
  102. /* FSC(Hz) = 4,433,618.75 Hz */
  103. SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
  104. }, {
  105. /* FSC(Hz) = 4,433,618.75 Hz */
  106. SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
  107. }, {
  108. /* FSC(Hz) = 4,433,618.75 Hz */
  109. SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
  110. }, {
  111. /* FSC(Hz) = 4,433,618.75 Hz */
  112. SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
  113. },
  114. };
  115. static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
  116. {
  117. struct adv7343_state *state = to_state(sd);
  118. struct adv7343_std_info *std_info;
  119. int num_std;
  120. char *fsc_ptr;
  121. u8 reg, val;
  122. int err = 0;
  123. int i = 0;
  124. std_info = (struct adv7343_std_info *)stdinfo;
  125. num_std = ARRAY_SIZE(stdinfo);
  126. for (i = 0; i < num_std; i++) {
  127. if (std_info[i].stdid & std)
  128. break;
  129. }
  130. if (i == num_std) {
  131. v4l2_dbg(1, debug, sd,
  132. "Invalid std or std is not supported: %llx\n",
  133. (unsigned long long)std);
  134. return -EINVAL;
  135. }
  136. /* Set the standard */
  137. val = state->reg80 & (~(SD_STD_MASK));
  138. val |= std_info[i].standard_val3;
  139. err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
  140. if (err < 0)
  141. goto setstd_exit;
  142. state->reg80 = val;
  143. /* Configure the input mode register */
  144. val = state->reg01 & (~((u8) INPUT_MODE_MASK));
  145. val |= SD_INPUT_MODE;
  146. err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
  147. if (err < 0)
  148. goto setstd_exit;
  149. state->reg01 = val;
  150. /* Program the sub carrier frequency registers */
  151. fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
  152. reg = ADV7343_FSC_REG0;
  153. for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
  154. err = adv7343_write(sd, reg, *fsc_ptr);
  155. if (err < 0)
  156. goto setstd_exit;
  157. }
  158. val = state->reg80;
  159. /* Filter settings */
  160. if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
  161. val &= 0x03;
  162. else if (std & ~V4L2_STD_SECAM)
  163. val |= 0x04;
  164. err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
  165. if (err < 0)
  166. goto setstd_exit;
  167. state->reg80 = val;
  168. setstd_exit:
  169. if (err != 0)
  170. v4l2_err(sd, "Error setting std, write failed\n");
  171. return err;
  172. }
  173. static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
  174. {
  175. struct adv7343_state *state = to_state(sd);
  176. unsigned char val;
  177. int err = 0;
  178. if (output_type > ADV7343_SVIDEO_ID) {
  179. v4l2_dbg(1, debug, sd,
  180. "Invalid output type or output type not supported:%d\n",
  181. output_type);
  182. return -EINVAL;
  183. }
  184. /* Enable Appropriate DAC */
  185. val = state->reg00 & 0x03;
  186. /* configure default configuration */
  187. if (!state->pdata)
  188. if (output_type == ADV7343_COMPOSITE_ID)
  189. val |= ADV7343_COMPOSITE_POWER_VALUE;
  190. else if (output_type == ADV7343_COMPONENT_ID)
  191. val |= ADV7343_COMPONENT_POWER_VALUE;
  192. else
  193. val |= ADV7343_SVIDEO_POWER_VALUE;
  194. else
  195. val = state->pdata->mode_config.sleep_mode << 0 |
  196. state->pdata->mode_config.pll_control << 1 |
  197. state->pdata->mode_config.dac[2] << 2 |
  198. state->pdata->mode_config.dac[1] << 3 |
  199. state->pdata->mode_config.dac[0] << 4 |
  200. state->pdata->mode_config.dac[5] << 5 |
  201. state->pdata->mode_config.dac[4] << 6 |
  202. state->pdata->mode_config.dac[3] << 7;
  203. err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
  204. if (err < 0)
  205. goto setoutput_exit;
  206. state->reg00 = val;
  207. /* Enable YUV output */
  208. val = state->reg02 | YUV_OUTPUT_SELECT;
  209. err = adv7343_write(sd, ADV7343_MODE_REG0, val);
  210. if (err < 0)
  211. goto setoutput_exit;
  212. state->reg02 = val;
  213. /* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
  214. val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
  215. if (state->pdata && state->pdata->sd_config.sd_dac_out[0])
  216. val = val | (state->pdata->sd_config.sd_dac_out[0] << 1);
  217. else if (state->pdata && !state->pdata->sd_config.sd_dac_out[0])
  218. val = val & ~(state->pdata->sd_config.sd_dac_out[0] << 1);
  219. if (state->pdata && state->pdata->sd_config.sd_dac_out[1])
  220. val = val | (state->pdata->sd_config.sd_dac_out[1] << 2);
  221. else if (state->pdata && !state->pdata->sd_config.sd_dac_out[1])
  222. val = val & ~(state->pdata->sd_config.sd_dac_out[1] << 2);
  223. err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
  224. if (err < 0)
  225. goto setoutput_exit;
  226. state->reg82 = val;
  227. /* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
  228. * zero */
  229. val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
  230. err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
  231. if (err < 0)
  232. goto setoutput_exit;
  233. state->reg35 = val;
  234. setoutput_exit:
  235. if (err != 0)
  236. v4l2_err(sd, "Error setting output, write failed\n");
  237. return err;
  238. }
  239. static int adv7343_log_status(struct v4l2_subdev *sd)
  240. {
  241. struct adv7343_state *state = to_state(sd);
  242. v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
  243. v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
  244. ((state->output == 1) ? "Component" : "S-Video"));
  245. return 0;
  246. }
  247. static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
  248. {
  249. struct v4l2_subdev *sd = to_sd(ctrl);
  250. switch (ctrl->id) {
  251. case V4L2_CID_BRIGHTNESS:
  252. return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
  253. ctrl->val);
  254. case V4L2_CID_HUE:
  255. return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);
  256. case V4L2_CID_GAIN:
  257. return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
  258. }
  259. return -EINVAL;
  260. }
  261. static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
  262. .s_ctrl = adv7343_s_ctrl,
  263. };
  264. static const struct v4l2_subdev_core_ops adv7343_core_ops = {
  265. .log_status = adv7343_log_status,
  266. .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
  267. .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
  268. .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
  269. .g_ctrl = v4l2_subdev_g_ctrl,
  270. .s_ctrl = v4l2_subdev_s_ctrl,
  271. .queryctrl = v4l2_subdev_queryctrl,
  272. .querymenu = v4l2_subdev_querymenu,
  273. };
  274. static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
  275. {
  276. struct adv7343_state *state = to_state(sd);
  277. int err = 0;
  278. if (state->std == std)
  279. return 0;
  280. err = adv7343_setstd(sd, std);
  281. if (!err)
  282. state->std = std;
  283. return err;
  284. }
  285. static int adv7343_s_routing(struct v4l2_subdev *sd,
  286. u32 input, u32 output, u32 config)
  287. {
  288. struct adv7343_state *state = to_state(sd);
  289. int err = 0;
  290. if (state->output == output)
  291. return 0;
  292. err = adv7343_setoutput(sd, output);
  293. if (!err)
  294. state->output = output;
  295. return err;
  296. }
  297. static const struct v4l2_subdev_video_ops adv7343_video_ops = {
  298. .s_std_output = adv7343_s_std_output,
  299. .s_routing = adv7343_s_routing,
  300. };
  301. static const struct v4l2_subdev_ops adv7343_ops = {
  302. .core = &adv7343_core_ops,
  303. .video = &adv7343_video_ops,
  304. };
  305. static int adv7343_initialize(struct v4l2_subdev *sd)
  306. {
  307. struct adv7343_state *state = to_state(sd);
  308. int err = 0;
  309. int i;
  310. for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
  311. err = adv7343_write(sd, adv7343_init_reg_val[i],
  312. adv7343_init_reg_val[i+1]);
  313. if (err) {
  314. v4l2_err(sd, "Error initializing\n");
  315. return err;
  316. }
  317. }
  318. /* Configure for default video standard */
  319. err = adv7343_setoutput(sd, state->output);
  320. if (err < 0) {
  321. v4l2_err(sd, "Error setting output during init\n");
  322. return -EINVAL;
  323. }
  324. err = adv7343_setstd(sd, state->std);
  325. if (err < 0) {
  326. v4l2_err(sd, "Error setting std during init\n");
  327. return -EINVAL;
  328. }
  329. return err;
  330. }
  331. static struct adv7343_platform_data *
  332. adv7343_get_pdata(struct i2c_client *client)
  333. {
  334. struct adv7343_platform_data *pdata;
  335. struct device_node *np;
  336. if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
  337. return client->dev.platform_data;
  338. np = v4l2_of_get_next_endpoint(client->dev.of_node, NULL);
  339. if (!np)
  340. return NULL;
  341. pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
  342. if (!pdata)
  343. goto done;
  344. pdata->mode_config.sleep_mode =
  345. of_property_read_bool(np, "adi,power-mode-sleep-mode");
  346. pdata->mode_config.pll_control =
  347. of_property_read_bool(np, "adi,power-mode-pll-ctrl");
  348. of_property_read_u32_array(np, "adi,dac-enable",
  349. pdata->mode_config.dac, 6);
  350. of_property_read_u32_array(np, "adi,sd-dac-enable",
  351. pdata->sd_config.sd_dac_out, 2);
  352. done:
  353. of_node_put(np);
  354. return pdata;
  355. }
  356. static int adv7343_probe(struct i2c_client *client,
  357. const struct i2c_device_id *id)
  358. {
  359. struct adv7343_state *state;
  360. int err;
  361. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  362. return -ENODEV;
  363. v4l_info(client, "chip found @ 0x%x (%s)\n",
  364. client->addr << 1, client->adapter->name);
  365. state = devm_kzalloc(&client->dev, sizeof(struct adv7343_state),
  366. GFP_KERNEL);
  367. if (state == NULL)
  368. return -ENOMEM;
  369. /* Copy board specific information here */
  370. state->pdata = adv7343_get_pdata(client);
  371. state->reg00 = 0x80;
  372. state->reg01 = 0x00;
  373. state->reg02 = 0x20;
  374. state->reg35 = 0x00;
  375. state->reg80 = ADV7343_SD_MODE_REG1_DEFAULT;
  376. state->reg82 = ADV7343_SD_MODE_REG2_DEFAULT;
  377. state->output = ADV7343_COMPOSITE_ID;
  378. state->std = V4L2_STD_NTSC;
  379. v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
  380. v4l2_ctrl_handler_init(&state->hdl, 2);
  381. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  382. V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
  383. ADV7343_BRIGHTNESS_MAX, 1,
  384. ADV7343_BRIGHTNESS_DEF);
  385. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  386. V4L2_CID_HUE, ADV7343_HUE_MIN,
  387. ADV7343_HUE_MAX, 1,
  388. ADV7343_HUE_DEF);
  389. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  390. V4L2_CID_GAIN, ADV7343_GAIN_MIN,
  391. ADV7343_GAIN_MAX, 1,
  392. ADV7343_GAIN_DEF);
  393. state->sd.ctrl_handler = &state->hdl;
  394. if (state->hdl.error) {
  395. err = state->hdl.error;
  396. goto done;
  397. }
  398. v4l2_ctrl_handler_setup(&state->hdl);
  399. err = adv7343_initialize(&state->sd);
  400. if (err)
  401. goto done;
  402. err = v4l2_async_register_subdev(&state->sd);
  403. done:
  404. if (err < 0)
  405. v4l2_ctrl_handler_free(&state->hdl);
  406. return err;
  407. }
  408. static int adv7343_remove(struct i2c_client *client)
  409. {
  410. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  411. struct adv7343_state *state = to_state(sd);
  412. v4l2_async_unregister_subdev(&state->sd);
  413. v4l2_device_unregister_subdev(sd);
  414. v4l2_ctrl_handler_free(&state->hdl);
  415. return 0;
  416. }
  417. static const struct i2c_device_id adv7343_id[] = {
  418. {"adv7343", 0},
  419. {},
  420. };
  421. MODULE_DEVICE_TABLE(i2c, adv7343_id);
  422. #if IS_ENABLED(CONFIG_OF)
  423. static const struct of_device_id adv7343_of_match[] = {
  424. {.compatible = "adi,adv7343", },
  425. { /* sentinel */ },
  426. };
  427. MODULE_DEVICE_TABLE(of, adv7343_of_match);
  428. #endif
  429. static struct i2c_driver adv7343_driver = {
  430. .driver = {
  431. .of_match_table = of_match_ptr(adv7343_of_match),
  432. .owner = THIS_MODULE,
  433. .name = "adv7343",
  434. },
  435. .probe = adv7343_probe,
  436. .remove = adv7343_remove,
  437. .id_table = adv7343_id,
  438. };
  439. module_i2c_driver(adv7343_driver);