i2c-mpc.c 21 KB

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  1. /*
  2. * (C) Copyright 2003-2004
  3. * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
  4. * This is a combined i2c adapter and algorithm driver for the
  5. * MPC107/Tsi107 PowerPC northbridge and processors that include
  6. * the same I2C unit (8240, 8245, 85xx).
  7. *
  8. * Release 0.8
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without any
  12. * warranty of any kind, whether express or implied.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/sched.h>
  17. #include <linux/init.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/slab.h>
  20. #include <linux/clk.h>
  21. #include <linux/io.h>
  22. #include <linux/fsl_devices.h>
  23. #include <linux/i2c.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/delay.h>
  26. #include <asm/mpc52xx.h>
  27. #include <sysdev/fsl_soc.h>
  28. #define DRV_NAME "mpc-i2c"
  29. #define MPC_I2C_CLOCK_LEGACY 0
  30. #define MPC_I2C_CLOCK_PRESERVE (~0U)
  31. #define MPC_I2C_FDR 0x04
  32. #define MPC_I2C_CR 0x08
  33. #define MPC_I2C_SR 0x0c
  34. #define MPC_I2C_DR 0x10
  35. #define MPC_I2C_DFSRR 0x14
  36. #define CCR_MEN 0x80
  37. #define CCR_MIEN 0x40
  38. #define CCR_MSTA 0x20
  39. #define CCR_MTX 0x10
  40. #define CCR_TXAK 0x08
  41. #define CCR_RSTA 0x04
  42. #define CSR_MCF 0x80
  43. #define CSR_MAAS 0x40
  44. #define CSR_MBB 0x20
  45. #define CSR_MAL 0x10
  46. #define CSR_SRW 0x04
  47. #define CSR_MIF 0x02
  48. #define CSR_RXAK 0x01
  49. struct mpc_i2c {
  50. struct device *dev;
  51. void __iomem *base;
  52. u32 interrupt;
  53. wait_queue_head_t queue;
  54. struct i2c_adapter adap;
  55. int irq;
  56. u32 real_clk;
  57. #ifdef CONFIG_PM_SLEEP
  58. u8 fdr, dfsrr;
  59. #endif
  60. struct clk *clk_per;
  61. };
  62. struct mpc_i2c_divider {
  63. u16 divider;
  64. u16 fdr; /* including dfsrr */
  65. };
  66. struct mpc_i2c_data {
  67. void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
  68. u32 clock, u32 prescaler);
  69. u32 prescaler;
  70. };
  71. static inline void writeccr(struct mpc_i2c *i2c, u32 x)
  72. {
  73. writeb(x, i2c->base + MPC_I2C_CR);
  74. }
  75. static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
  76. {
  77. struct mpc_i2c *i2c = dev_id;
  78. if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
  79. /* Read again to allow register to stabilise */
  80. i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
  81. writeb(0, i2c->base + MPC_I2C_SR);
  82. wake_up(&i2c->queue);
  83. }
  84. return IRQ_HANDLED;
  85. }
  86. /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
  87. * the bus, because it wants to send ACK.
  88. * Following sequence of enabling/disabling and sending start/stop generates
  89. * the 9 pulses, so it's all OK.
  90. */
  91. static void mpc_i2c_fixup(struct mpc_i2c *i2c)
  92. {
  93. int k;
  94. u32 delay_val = 1000000 / i2c->real_clk + 1;
  95. if (delay_val < 2)
  96. delay_val = 2;
  97. for (k = 9; k; k--) {
  98. writeccr(i2c, 0);
  99. writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
  100. udelay(delay_val);
  101. writeccr(i2c, CCR_MEN);
  102. udelay(delay_val << 1);
  103. }
  104. }
  105. static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
  106. {
  107. unsigned long orig_jiffies = jiffies;
  108. u32 x;
  109. int result = 0;
  110. if (!i2c->irq) {
  111. while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
  112. schedule();
  113. if (time_after(jiffies, orig_jiffies + timeout)) {
  114. dev_dbg(i2c->dev, "timeout\n");
  115. writeccr(i2c, 0);
  116. result = -EIO;
  117. break;
  118. }
  119. }
  120. x = readb(i2c->base + MPC_I2C_SR);
  121. writeb(0, i2c->base + MPC_I2C_SR);
  122. } else {
  123. /* Interrupt mode */
  124. result = wait_event_timeout(i2c->queue,
  125. (i2c->interrupt & CSR_MIF), timeout);
  126. if (unlikely(!(i2c->interrupt & CSR_MIF))) {
  127. dev_dbg(i2c->dev, "wait timeout\n");
  128. writeccr(i2c, 0);
  129. result = -ETIMEDOUT;
  130. }
  131. x = i2c->interrupt;
  132. i2c->interrupt = 0;
  133. }
  134. if (result < 0)
  135. return result;
  136. if (!(x & CSR_MCF)) {
  137. dev_dbg(i2c->dev, "unfinished\n");
  138. return -EIO;
  139. }
  140. if (x & CSR_MAL) {
  141. dev_dbg(i2c->dev, "MAL\n");
  142. return -EIO;
  143. }
  144. if (writing && (x & CSR_RXAK)) {
  145. dev_dbg(i2c->dev, "No RXAK\n");
  146. /* generate stop */
  147. writeccr(i2c, CCR_MEN);
  148. return -EIO;
  149. }
  150. return 0;
  151. }
  152. #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
  153. static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
  154. {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
  155. {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
  156. {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
  157. {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
  158. {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
  159. {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
  160. {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
  161. {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
  162. {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
  163. {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
  164. {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
  165. {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
  166. {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
  167. {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
  168. {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
  169. {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
  170. {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
  171. {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
  172. };
  173. static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
  174. int prescaler, u32 *real_clk)
  175. {
  176. const struct mpc_i2c_divider *div = NULL;
  177. unsigned int pvr = mfspr(SPRN_PVR);
  178. u32 divider;
  179. int i;
  180. if (clock == MPC_I2C_CLOCK_LEGACY) {
  181. /* see below - default fdr = 0x3f -> div = 2048 */
  182. *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
  183. return -EINVAL;
  184. }
  185. /* Determine divider value */
  186. divider = mpc5xxx_get_bus_frequency(node) / clock;
  187. /*
  188. * We want to choose an FDR/DFSR that generates an I2C bus speed that
  189. * is equal to or lower than the requested speed.
  190. */
  191. for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
  192. div = &mpc_i2c_dividers_52xx[i];
  193. /* Old MPC5200 rev A CPUs do not support the high bits */
  194. if (div->fdr & 0xc0 && pvr == 0x80822011)
  195. continue;
  196. if (div->divider >= divider)
  197. break;
  198. }
  199. *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
  200. return (int)div->fdr;
  201. }
  202. static void mpc_i2c_setup_52xx(struct device_node *node,
  203. struct mpc_i2c *i2c,
  204. u32 clock, u32 prescaler)
  205. {
  206. int ret, fdr;
  207. if (clock == MPC_I2C_CLOCK_PRESERVE) {
  208. dev_dbg(i2c->dev, "using fdr %d\n",
  209. readb(i2c->base + MPC_I2C_FDR));
  210. return;
  211. }
  212. ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);
  213. fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
  214. writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
  215. if (ret >= 0)
  216. dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
  217. fdr);
  218. }
  219. #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
  220. static void mpc_i2c_setup_52xx(struct device_node *node,
  221. struct mpc_i2c *i2c,
  222. u32 clock, u32 prescaler)
  223. {
  224. }
  225. #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
  226. #ifdef CONFIG_PPC_MPC512x
  227. static void mpc_i2c_setup_512x(struct device_node *node,
  228. struct mpc_i2c *i2c,
  229. u32 clock, u32 prescaler)
  230. {
  231. struct device_node *node_ctrl;
  232. void __iomem *ctrl;
  233. const u32 *pval;
  234. u32 idx;
  235. /* Enable I2C interrupts for mpc5121 */
  236. node_ctrl = of_find_compatible_node(NULL, NULL,
  237. "fsl,mpc5121-i2c-ctrl");
  238. if (node_ctrl) {
  239. ctrl = of_iomap(node_ctrl, 0);
  240. if (ctrl) {
  241. /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
  242. pval = of_get_property(node, "reg", NULL);
  243. idx = (*pval & 0xff) / 0x20;
  244. setbits32(ctrl, 1 << (24 + idx * 2));
  245. iounmap(ctrl);
  246. }
  247. of_node_put(node_ctrl);
  248. }
  249. /* The clock setup for the 52xx works also fine for the 512x */
  250. mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
  251. }
  252. #else /* CONFIG_PPC_MPC512x */
  253. static void mpc_i2c_setup_512x(struct device_node *node,
  254. struct mpc_i2c *i2c,
  255. u32 clock, u32 prescaler)
  256. {
  257. }
  258. #endif /* CONFIG_PPC_MPC512x */
  259. #ifdef CONFIG_FSL_SOC
  260. static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
  261. {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
  262. {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
  263. {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
  264. {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
  265. {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
  266. {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
  267. {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
  268. {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
  269. {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
  270. {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
  271. {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
  272. {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
  273. {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
  274. {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
  275. {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
  276. {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
  277. {49152, 0x011e}, {61440, 0x011f}
  278. };
  279. static u32 mpc_i2c_get_sec_cfg_8xxx(void)
  280. {
  281. struct device_node *node = NULL;
  282. u32 __iomem *reg;
  283. u32 val = 0;
  284. node = of_find_node_by_name(NULL, "global-utilities");
  285. if (node) {
  286. const u32 *prop = of_get_property(node, "reg", NULL);
  287. if (prop) {
  288. /*
  289. * Map and check POR Device Status Register 2
  290. * (PORDEVSR2) at 0xE0014
  291. */
  292. reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
  293. if (!reg)
  294. printk(KERN_ERR
  295. "Error: couldn't map PORDEVSR2\n");
  296. else
  297. val = in_be32(reg) & 0x00000080; /* sec-cfg */
  298. iounmap(reg);
  299. }
  300. }
  301. if (node)
  302. of_node_put(node);
  303. return val;
  304. }
  305. static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
  306. u32 prescaler, u32 *real_clk)
  307. {
  308. const struct mpc_i2c_divider *div = NULL;
  309. u32 divider;
  310. int i;
  311. if (clock == MPC_I2C_CLOCK_LEGACY) {
  312. /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
  313. *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
  314. return -EINVAL;
  315. }
  316. /* Determine proper divider value */
  317. if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
  318. prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
  319. if (!prescaler)
  320. prescaler = 1;
  321. divider = fsl_get_sys_freq() / clock / prescaler;
  322. pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
  323. fsl_get_sys_freq(), clock, divider);
  324. /*
  325. * We want to choose an FDR/DFSR that generates an I2C bus speed that
  326. * is equal to or lower than the requested speed.
  327. */
  328. for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
  329. div = &mpc_i2c_dividers_8xxx[i];
  330. if (div->divider >= divider)
  331. break;
  332. }
  333. *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
  334. return div ? (int)div->fdr : -EINVAL;
  335. }
  336. static void mpc_i2c_setup_8xxx(struct device_node *node,
  337. struct mpc_i2c *i2c,
  338. u32 clock, u32 prescaler)
  339. {
  340. int ret, fdr;
  341. if (clock == MPC_I2C_CLOCK_PRESERVE) {
  342. dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
  343. readb(i2c->base + MPC_I2C_DFSRR),
  344. readb(i2c->base + MPC_I2C_FDR));
  345. return;
  346. }
  347. ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);
  348. fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
  349. writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
  350. writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
  351. if (ret >= 0)
  352. dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
  353. i2c->real_clk, fdr >> 8, fdr & 0xff);
  354. }
  355. #else /* !CONFIG_FSL_SOC */
  356. static void mpc_i2c_setup_8xxx(struct device_node *node,
  357. struct mpc_i2c *i2c,
  358. u32 clock, u32 prescaler)
  359. {
  360. }
  361. #endif /* CONFIG_FSL_SOC */
  362. static void mpc_i2c_start(struct mpc_i2c *i2c)
  363. {
  364. /* Clear arbitration */
  365. writeb(0, i2c->base + MPC_I2C_SR);
  366. /* Start with MEN */
  367. writeccr(i2c, CCR_MEN);
  368. }
  369. static void mpc_i2c_stop(struct mpc_i2c *i2c)
  370. {
  371. writeccr(i2c, CCR_MEN);
  372. }
  373. static int mpc_write(struct mpc_i2c *i2c, int target,
  374. const u8 *data, int length, int restart)
  375. {
  376. int i, result;
  377. unsigned timeout = i2c->adap.timeout;
  378. u32 flags = restart ? CCR_RSTA : 0;
  379. /* Start as master */
  380. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
  381. /* Write target byte */
  382. writeb((target << 1), i2c->base + MPC_I2C_DR);
  383. result = i2c_wait(i2c, timeout, 1);
  384. if (result < 0)
  385. return result;
  386. for (i = 0; i < length; i++) {
  387. /* Write data byte */
  388. writeb(data[i], i2c->base + MPC_I2C_DR);
  389. result = i2c_wait(i2c, timeout, 1);
  390. if (result < 0)
  391. return result;
  392. }
  393. return 0;
  394. }
  395. static int mpc_read(struct mpc_i2c *i2c, int target,
  396. u8 *data, int length, int restart, bool recv_len)
  397. {
  398. unsigned timeout = i2c->adap.timeout;
  399. int i, result;
  400. u32 flags = restart ? CCR_RSTA : 0;
  401. /* Switch to read - restart */
  402. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
  403. /* Write target address byte - this time with the read flag set */
  404. writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
  405. result = i2c_wait(i2c, timeout, 1);
  406. if (result < 0)
  407. return result;
  408. if (length) {
  409. if (length == 1 && !recv_len)
  410. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
  411. else
  412. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
  413. /* Dummy read */
  414. readb(i2c->base + MPC_I2C_DR);
  415. }
  416. for (i = 0; i < length; i++) {
  417. u8 byte;
  418. result = i2c_wait(i2c, timeout, 0);
  419. if (result < 0)
  420. return result;
  421. /*
  422. * For block reads, we have to know the total length (1st byte)
  423. * before we can determine if we are done.
  424. */
  425. if (i || !recv_len) {
  426. /* Generate txack on next to last byte */
  427. if (i == length - 2)
  428. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
  429. | CCR_TXAK);
  430. /* Do not generate stop on last byte */
  431. if (i == length - 1)
  432. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
  433. | CCR_MTX);
  434. }
  435. byte = readb(i2c->base + MPC_I2C_DR);
  436. /*
  437. * Adjust length if first received byte is length.
  438. * The length is 1 length byte plus actually data length
  439. */
  440. if (i == 0 && recv_len) {
  441. if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
  442. return -EPROTO;
  443. length += byte;
  444. /*
  445. * For block reads, generate txack here if data length
  446. * is 1 byte (total length is 2 bytes).
  447. */
  448. if (length == 2)
  449. writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
  450. | CCR_TXAK);
  451. }
  452. data[i] = byte;
  453. }
  454. return length;
  455. }
  456. static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  457. {
  458. struct i2c_msg *pmsg;
  459. int i;
  460. int ret = 0;
  461. unsigned long orig_jiffies = jiffies;
  462. struct mpc_i2c *i2c = i2c_get_adapdata(adap);
  463. mpc_i2c_start(i2c);
  464. /* Allow bus up to 1s to become not busy */
  465. while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
  466. if (signal_pending(current)) {
  467. dev_dbg(i2c->dev, "Interrupted\n");
  468. writeccr(i2c, 0);
  469. return -EINTR;
  470. }
  471. if (time_after(jiffies, orig_jiffies + HZ)) {
  472. u8 status = readb(i2c->base + MPC_I2C_SR);
  473. dev_dbg(i2c->dev, "timeout\n");
  474. if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
  475. writeb(status & ~CSR_MAL,
  476. i2c->base + MPC_I2C_SR);
  477. mpc_i2c_fixup(i2c);
  478. }
  479. return -EIO;
  480. }
  481. schedule();
  482. }
  483. for (i = 0; ret >= 0 && i < num; i++) {
  484. pmsg = &msgs[i];
  485. dev_dbg(i2c->dev,
  486. "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
  487. pmsg->flags & I2C_M_RD ? "read" : "write",
  488. pmsg->len, pmsg->addr, i + 1, num);
  489. if (pmsg->flags & I2C_M_RD) {
  490. bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
  491. ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
  492. recv_len);
  493. if (recv_len && ret > 0)
  494. pmsg->len = ret;
  495. } else {
  496. ret =
  497. mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
  498. }
  499. }
  500. mpc_i2c_stop(i2c); /* Initiate STOP */
  501. orig_jiffies = jiffies;
  502. /* Wait until STOP is seen, allow up to 1 s */
  503. while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
  504. if (time_after(jiffies, orig_jiffies + HZ)) {
  505. u8 status = readb(i2c->base + MPC_I2C_SR);
  506. dev_dbg(i2c->dev, "timeout\n");
  507. if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
  508. writeb(status & ~CSR_MAL,
  509. i2c->base + MPC_I2C_SR);
  510. mpc_i2c_fixup(i2c);
  511. }
  512. return -EIO;
  513. }
  514. cond_resched();
  515. }
  516. return (ret < 0) ? ret : num;
  517. }
  518. static u32 mpc_functionality(struct i2c_adapter *adap)
  519. {
  520. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
  521. | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
  522. }
  523. static const struct i2c_algorithm mpc_algo = {
  524. .master_xfer = mpc_xfer,
  525. .functionality = mpc_functionality,
  526. };
  527. static struct i2c_adapter mpc_ops = {
  528. .owner = THIS_MODULE,
  529. .algo = &mpc_algo,
  530. .timeout = HZ,
  531. };
  532. static const struct of_device_id mpc_i2c_of_match[];
  533. static int fsl_i2c_probe(struct platform_device *op)
  534. {
  535. const struct of_device_id *match;
  536. struct mpc_i2c *i2c;
  537. const u32 *prop;
  538. u32 clock = MPC_I2C_CLOCK_LEGACY;
  539. int result = 0;
  540. int plen;
  541. struct resource res;
  542. struct clk *clk;
  543. int err;
  544. match = of_match_device(mpc_i2c_of_match, &op->dev);
  545. if (!match)
  546. return -EINVAL;
  547. i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
  548. if (!i2c)
  549. return -ENOMEM;
  550. i2c->dev = &op->dev; /* for debug and error output */
  551. init_waitqueue_head(&i2c->queue);
  552. i2c->base = of_iomap(op->dev.of_node, 0);
  553. if (!i2c->base) {
  554. dev_err(i2c->dev, "failed to map controller\n");
  555. result = -ENOMEM;
  556. goto fail_map;
  557. }
  558. i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
  559. if (i2c->irq) { /* no i2c->irq implies polling */
  560. result = request_irq(i2c->irq, mpc_i2c_isr,
  561. IRQF_SHARED, "i2c-mpc", i2c);
  562. if (result < 0) {
  563. dev_err(i2c->dev, "failed to attach interrupt\n");
  564. goto fail_request;
  565. }
  566. }
  567. /*
  568. * enable clock for the I2C peripheral (non fatal),
  569. * keep a reference upon successful allocation
  570. */
  571. clk = devm_clk_get(&op->dev, NULL);
  572. if (!IS_ERR(clk)) {
  573. err = clk_prepare_enable(clk);
  574. if (err) {
  575. dev_err(&op->dev, "failed to enable clock\n");
  576. goto fail_request;
  577. } else {
  578. i2c->clk_per = clk;
  579. }
  580. }
  581. if (of_get_property(op->dev.of_node, "fsl,preserve-clocking", NULL)) {
  582. clock = MPC_I2C_CLOCK_PRESERVE;
  583. } else {
  584. prop = of_get_property(op->dev.of_node, "clock-frequency",
  585. &plen);
  586. if (prop && plen == sizeof(u32))
  587. clock = *prop;
  588. }
  589. if (match->data) {
  590. const struct mpc_i2c_data *data = match->data;
  591. data->setup(op->dev.of_node, i2c, clock, data->prescaler);
  592. } else {
  593. /* Backwards compatibility */
  594. if (of_get_property(op->dev.of_node, "dfsrr", NULL))
  595. mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0);
  596. }
  597. prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
  598. if (prop && plen == sizeof(u32)) {
  599. mpc_ops.timeout = *prop * HZ / 1000000;
  600. if (mpc_ops.timeout < 5)
  601. mpc_ops.timeout = 5;
  602. }
  603. dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
  604. platform_set_drvdata(op, i2c);
  605. i2c->adap = mpc_ops;
  606. of_address_to_resource(op->dev.of_node, 0, &res);
  607. scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
  608. "MPC adapter at 0x%llx", (unsigned long long)res.start);
  609. i2c_set_adapdata(&i2c->adap, i2c);
  610. i2c->adap.dev.parent = &op->dev;
  611. i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
  612. result = i2c_add_adapter(&i2c->adap);
  613. if (result < 0) {
  614. dev_err(i2c->dev, "failed to add adapter\n");
  615. goto fail_add;
  616. }
  617. return result;
  618. fail_add:
  619. if (i2c->clk_per)
  620. clk_disable_unprepare(i2c->clk_per);
  621. free_irq(i2c->irq, i2c);
  622. fail_request:
  623. irq_dispose_mapping(i2c->irq);
  624. iounmap(i2c->base);
  625. fail_map:
  626. kfree(i2c);
  627. return result;
  628. };
  629. static int fsl_i2c_remove(struct platform_device *op)
  630. {
  631. struct mpc_i2c *i2c = platform_get_drvdata(op);
  632. i2c_del_adapter(&i2c->adap);
  633. if (i2c->clk_per)
  634. clk_disable_unprepare(i2c->clk_per);
  635. if (i2c->irq)
  636. free_irq(i2c->irq, i2c);
  637. irq_dispose_mapping(i2c->irq);
  638. iounmap(i2c->base);
  639. kfree(i2c);
  640. return 0;
  641. };
  642. #ifdef CONFIG_PM_SLEEP
  643. static int mpc_i2c_suspend(struct device *dev)
  644. {
  645. struct mpc_i2c *i2c = dev_get_drvdata(dev);
  646. i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
  647. i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
  648. return 0;
  649. }
  650. static int mpc_i2c_resume(struct device *dev)
  651. {
  652. struct mpc_i2c *i2c = dev_get_drvdata(dev);
  653. writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
  654. writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
  655. return 0;
  656. }
  657. static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
  658. #define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops)
  659. #else
  660. #define MPC_I2C_PM_OPS NULL
  661. #endif
  662. static const struct mpc_i2c_data mpc_i2c_data_512x = {
  663. .setup = mpc_i2c_setup_512x,
  664. };
  665. static const struct mpc_i2c_data mpc_i2c_data_52xx = {
  666. .setup = mpc_i2c_setup_52xx,
  667. };
  668. static const struct mpc_i2c_data mpc_i2c_data_8313 = {
  669. .setup = mpc_i2c_setup_8xxx,
  670. };
  671. static const struct mpc_i2c_data mpc_i2c_data_8543 = {
  672. .setup = mpc_i2c_setup_8xxx,
  673. .prescaler = 2,
  674. };
  675. static const struct mpc_i2c_data mpc_i2c_data_8544 = {
  676. .setup = mpc_i2c_setup_8xxx,
  677. .prescaler = 3,
  678. };
  679. static const struct of_device_id mpc_i2c_of_match[] = {
  680. {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
  681. {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
  682. {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
  683. {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
  684. {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
  685. {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
  686. {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
  687. /* Backward compatibility */
  688. {.compatible = "fsl-i2c", },
  689. {},
  690. };
  691. MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
  692. /* Structure for a device driver */
  693. static struct platform_driver mpc_i2c_driver = {
  694. .probe = fsl_i2c_probe,
  695. .remove = fsl_i2c_remove,
  696. .driver = {
  697. .owner = THIS_MODULE,
  698. .name = DRV_NAME,
  699. .of_match_table = mpc_i2c_of_match,
  700. .pm = MPC_I2C_PM_OPS,
  701. },
  702. };
  703. module_platform_driver(mpc_i2c_driver);
  704. MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
  705. MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
  706. "MPC824x/83xx/85xx/86xx/512x/52xx processors");
  707. MODULE_LICENSE("GPL");