i2c-imx.c 22 KB

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  1. /*
  2. * Copyright (C) 2002 Motorola GSG-China
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation; either version 2
  7. * of the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
  17. * USA.
  18. *
  19. * Author:
  20. * Darius Augulis, Teltonika Inc.
  21. *
  22. * Desc.:
  23. * Implementation of I2C Adapter/Algorithm Driver
  24. * for I2C Bus integrated in Freescale i.MX/MXC processors
  25. *
  26. * Derived from Motorola GSG China I2C example driver
  27. *
  28. * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  29. * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  30. * Copyright (C) 2007 RightHand Technologies, Inc.
  31. * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  32. *
  33. * Copyright 2013 Freescale Semiconductor, Inc.
  34. *
  35. */
  36. /** Includes *******************************************************************
  37. *******************************************************************************/
  38. #include <linux/init.h>
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/errno.h>
  42. #include <linux/err.h>
  43. #include <linux/interrupt.h>
  44. #include <linux/delay.h>
  45. #include <linux/i2c.h>
  46. #include <linux/io.h>
  47. #include <linux/sched.h>
  48. #include <linux/platform_device.h>
  49. #include <linux/clk.h>
  50. #include <linux/slab.h>
  51. #include <linux/of.h>
  52. #include <linux/of_device.h>
  53. #include <linux/platform_data/i2c-imx.h>
  54. /** Defines ********************************************************************
  55. *******************************************************************************/
  56. /* This will be the driver name the kernel reports */
  57. #define DRIVER_NAME "imx-i2c"
  58. /* Default value */
  59. #define IMX_I2C_BIT_RATE 100000 /* 100kHz */
  60. /* IMX I2C registers:
  61. * the I2C register offset is different between SoCs,
  62. * to provid support for all these chips, split the
  63. * register offset into a fixed base address and a
  64. * variable shift value, then the full register offset
  65. * will be calculated by
  66. * reg_off = ( reg_base_addr << reg_shift)
  67. */
  68. #define IMX_I2C_IADR 0x00 /* i2c slave address */
  69. #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
  70. #define IMX_I2C_I2CR 0x02 /* i2c control */
  71. #define IMX_I2C_I2SR 0x03 /* i2c status */
  72. #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
  73. #define IMX_I2C_REGSHIFT 2
  74. #define VF610_I2C_REGSHIFT 0
  75. /* Bits of IMX I2C registers */
  76. #define I2SR_RXAK 0x01
  77. #define I2SR_IIF 0x02
  78. #define I2SR_SRW 0x04
  79. #define I2SR_IAL 0x10
  80. #define I2SR_IBB 0x20
  81. #define I2SR_IAAS 0x40
  82. #define I2SR_ICF 0x80
  83. #define I2CR_RSTA 0x04
  84. #define I2CR_TXAK 0x08
  85. #define I2CR_MTX 0x10
  86. #define I2CR_MSTA 0x20
  87. #define I2CR_IIEN 0x40
  88. #define I2CR_IEN 0x80
  89. /* register bits different operating codes definition:
  90. * 1) I2SR: Interrupt flags clear operation differ between SoCs:
  91. * - write zero to clear(w0c) INT flag on i.MX,
  92. * - but write one to clear(w1c) INT flag on Vybrid.
  93. * 2) I2CR: I2C module enable operation also differ between SoCs:
  94. * - set I2CR_IEN bit enable the module on i.MX,
  95. * - but clear I2CR_IEN bit enable the module on Vybrid.
  96. */
  97. #define I2SR_CLR_OPCODE_W0C 0x0
  98. #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
  99. #define I2CR_IEN_OPCODE_0 0x0
  100. #define I2CR_IEN_OPCODE_1 I2CR_IEN
  101. /** Variables ******************************************************************
  102. *******************************************************************************/
  103. /*
  104. * sorted list of clock divider, register value pairs
  105. * taken from table 26-5, p.26-9, Freescale i.MX
  106. * Integrated Portable System Processor Reference Manual
  107. * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
  108. *
  109. * Duplicated divider values removed from list
  110. */
  111. struct imx_i2c_clk_pair {
  112. u16 div;
  113. u16 val;
  114. };
  115. static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
  116. { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
  117. { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
  118. { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
  119. { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
  120. { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
  121. { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
  122. { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
  123. { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
  124. { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
  125. { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
  126. { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
  127. { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
  128. { 3072, 0x1E }, { 3840, 0x1F }
  129. };
  130. /* Vybrid VF610 clock divider, register value pairs */
  131. static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
  132. { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
  133. { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
  134. { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
  135. { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
  136. { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
  137. { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
  138. { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
  139. { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
  140. { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
  141. { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
  142. { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
  143. { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
  144. { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
  145. { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
  146. { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
  147. };
  148. enum imx_i2c_type {
  149. IMX1_I2C,
  150. IMX21_I2C,
  151. VF610_I2C,
  152. };
  153. struct imx_i2c_hwdata {
  154. enum imx_i2c_type devtype;
  155. unsigned regshift;
  156. struct imx_i2c_clk_pair *clk_div;
  157. unsigned ndivs;
  158. unsigned i2sr_clr_opcode;
  159. unsigned i2cr_ien_opcode;
  160. };
  161. struct imx_i2c_struct {
  162. struct i2c_adapter adapter;
  163. struct clk *clk;
  164. void __iomem *base;
  165. wait_queue_head_t queue;
  166. unsigned long i2csr;
  167. unsigned int disable_delay;
  168. int stopped;
  169. unsigned int ifdr; /* IMX_I2C_IFDR */
  170. const struct imx_i2c_hwdata *hwdata;
  171. };
  172. static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
  173. .devtype = IMX1_I2C,
  174. .regshift = IMX_I2C_REGSHIFT,
  175. .clk_div = imx_i2c_clk_div,
  176. .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
  177. .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
  178. .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
  179. };
  180. static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
  181. .devtype = IMX21_I2C,
  182. .regshift = IMX_I2C_REGSHIFT,
  183. .clk_div = imx_i2c_clk_div,
  184. .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
  185. .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
  186. .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
  187. };
  188. static struct imx_i2c_hwdata vf610_i2c_hwdata = {
  189. .devtype = VF610_I2C,
  190. .regshift = VF610_I2C_REGSHIFT,
  191. .clk_div = vf610_i2c_clk_div,
  192. .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
  193. .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
  194. .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
  195. };
  196. static struct platform_device_id imx_i2c_devtype[] = {
  197. {
  198. .name = "imx1-i2c",
  199. .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
  200. }, {
  201. .name = "imx21-i2c",
  202. .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
  203. }, {
  204. /* sentinel */
  205. }
  206. };
  207. MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
  208. static const struct of_device_id i2c_imx_dt_ids[] = {
  209. { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
  210. { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
  211. { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
  212. { /* sentinel */ }
  213. };
  214. MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
  215. static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
  216. {
  217. return i2c_imx->hwdata->devtype == IMX1_I2C;
  218. }
  219. static inline void imx_i2c_write_reg(unsigned int val,
  220. struct imx_i2c_struct *i2c_imx, unsigned int reg)
  221. {
  222. writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
  223. }
  224. static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
  225. unsigned int reg)
  226. {
  227. return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
  228. }
  229. /** Functions for IMX I2C adapter driver ***************************************
  230. *******************************************************************************/
  231. static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
  232. {
  233. unsigned long orig_jiffies = jiffies;
  234. unsigned int temp;
  235. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  236. while (1) {
  237. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
  238. if (for_busy && (temp & I2SR_IBB))
  239. break;
  240. if (!for_busy && !(temp & I2SR_IBB))
  241. break;
  242. if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
  243. dev_dbg(&i2c_imx->adapter.dev,
  244. "<%s> I2C bus is busy\n", __func__);
  245. return -ETIMEDOUT;
  246. }
  247. schedule();
  248. }
  249. return 0;
  250. }
  251. static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
  252. {
  253. wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
  254. if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
  255. dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
  256. return -ETIMEDOUT;
  257. }
  258. dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
  259. i2c_imx->i2csr = 0;
  260. return 0;
  261. }
  262. static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
  263. {
  264. if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
  265. dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
  266. return -EIO; /* No ACK */
  267. }
  268. dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
  269. return 0;
  270. }
  271. static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
  272. {
  273. unsigned int temp = 0;
  274. int result;
  275. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  276. clk_prepare_enable(i2c_imx->clk);
  277. imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
  278. /* Enable I2C controller */
  279. imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
  280. imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
  281. /* Wait controller to be stable */
  282. udelay(50);
  283. /* Start I2C transaction */
  284. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  285. temp |= I2CR_MSTA;
  286. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  287. result = i2c_imx_bus_busy(i2c_imx, 1);
  288. if (result)
  289. return result;
  290. i2c_imx->stopped = 0;
  291. temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
  292. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  293. return result;
  294. }
  295. static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
  296. {
  297. unsigned int temp = 0;
  298. if (!i2c_imx->stopped) {
  299. /* Stop I2C transaction */
  300. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  301. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  302. temp &= ~(I2CR_MSTA | I2CR_MTX);
  303. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  304. }
  305. if (is_imx1_i2c(i2c_imx)) {
  306. /*
  307. * This delay caused by an i.MXL hardware bug.
  308. * If no (or too short) delay, no "STOP" bit will be generated.
  309. */
  310. udelay(i2c_imx->disable_delay);
  311. }
  312. if (!i2c_imx->stopped) {
  313. i2c_imx_bus_busy(i2c_imx, 0);
  314. i2c_imx->stopped = 1;
  315. }
  316. /* Disable I2C controller */
  317. temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
  318. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  319. clk_disable_unprepare(i2c_imx->clk);
  320. }
  321. static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
  322. unsigned int rate)
  323. {
  324. struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
  325. unsigned int i2c_clk_rate;
  326. unsigned int div;
  327. int i;
  328. /* Divider value calculation */
  329. i2c_clk_rate = clk_get_rate(i2c_imx->clk);
  330. div = (i2c_clk_rate + rate - 1) / rate;
  331. if (div < i2c_clk_div[0].div)
  332. i = 0;
  333. else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
  334. i = i2c_imx->hwdata->ndivs - 1;
  335. else
  336. for (i = 0; i2c_clk_div[i].div < div; i++);
  337. /* Store divider value */
  338. i2c_imx->ifdr = i2c_clk_div[i].val;
  339. /*
  340. * There dummy delay is calculated.
  341. * It should be about one I2C clock period long.
  342. * This delay is used in I2C bus disable function
  343. * to fix chip hardware bug.
  344. */
  345. i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
  346. + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
  347. /* dev_dbg() can't be used, because adapter is not yet registered */
  348. #ifdef CONFIG_I2C_DEBUG_BUS
  349. dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
  350. __func__, i2c_clk_rate, div);
  351. dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
  352. __func__, i2c_clk_div[i].val, i2c_clk_div[i].div);
  353. #endif
  354. }
  355. static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
  356. {
  357. struct imx_i2c_struct *i2c_imx = dev_id;
  358. unsigned int temp;
  359. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
  360. if (temp & I2SR_IIF) {
  361. /* save status register */
  362. i2c_imx->i2csr = temp;
  363. temp &= ~I2SR_IIF;
  364. temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
  365. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
  366. wake_up(&i2c_imx->queue);
  367. return IRQ_HANDLED;
  368. }
  369. return IRQ_NONE;
  370. }
  371. static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
  372. {
  373. int i, result;
  374. dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
  375. __func__, msgs->addr << 1);
  376. /* write slave address */
  377. imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
  378. result = i2c_imx_trx_complete(i2c_imx);
  379. if (result)
  380. return result;
  381. result = i2c_imx_acked(i2c_imx);
  382. if (result)
  383. return result;
  384. dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
  385. /* write data */
  386. for (i = 0; i < msgs->len; i++) {
  387. dev_dbg(&i2c_imx->adapter.dev,
  388. "<%s> write byte: B%d=0x%X\n",
  389. __func__, i, msgs->buf[i]);
  390. imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
  391. result = i2c_imx_trx_complete(i2c_imx);
  392. if (result)
  393. return result;
  394. result = i2c_imx_acked(i2c_imx);
  395. if (result)
  396. return result;
  397. }
  398. return 0;
  399. }
  400. static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
  401. {
  402. int i, result;
  403. unsigned int temp;
  404. dev_dbg(&i2c_imx->adapter.dev,
  405. "<%s> write slave address: addr=0x%x\n",
  406. __func__, (msgs->addr << 1) | 0x01);
  407. /* write slave address */
  408. imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
  409. result = i2c_imx_trx_complete(i2c_imx);
  410. if (result)
  411. return result;
  412. result = i2c_imx_acked(i2c_imx);
  413. if (result)
  414. return result;
  415. dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
  416. /* setup bus to read data */
  417. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  418. temp &= ~I2CR_MTX;
  419. if (msgs->len - 1)
  420. temp &= ~I2CR_TXAK;
  421. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  422. imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
  423. dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
  424. /* read data */
  425. for (i = 0; i < msgs->len; i++) {
  426. result = i2c_imx_trx_complete(i2c_imx);
  427. if (result)
  428. return result;
  429. if (i == (msgs->len - 1)) {
  430. /* It must generate STOP before read I2DR to prevent
  431. controller from generating another clock cycle */
  432. dev_dbg(&i2c_imx->adapter.dev,
  433. "<%s> clear MSTA\n", __func__);
  434. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  435. temp &= ~(I2CR_MSTA | I2CR_MTX);
  436. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  437. i2c_imx_bus_busy(i2c_imx, 0);
  438. i2c_imx->stopped = 1;
  439. } else if (i == (msgs->len - 2)) {
  440. dev_dbg(&i2c_imx->adapter.dev,
  441. "<%s> set TXAK\n", __func__);
  442. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  443. temp |= I2CR_TXAK;
  444. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  445. }
  446. msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
  447. dev_dbg(&i2c_imx->adapter.dev,
  448. "<%s> read byte: B%d=0x%X\n",
  449. __func__, i, msgs->buf[i]);
  450. }
  451. return 0;
  452. }
  453. static int i2c_imx_xfer(struct i2c_adapter *adapter,
  454. struct i2c_msg *msgs, int num)
  455. {
  456. unsigned int i, temp;
  457. int result;
  458. struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
  459. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  460. /* Start I2C transfer */
  461. result = i2c_imx_start(i2c_imx);
  462. if (result)
  463. goto fail0;
  464. /* read/write data */
  465. for (i = 0; i < num; i++) {
  466. if (i) {
  467. dev_dbg(&i2c_imx->adapter.dev,
  468. "<%s> repeated start\n", __func__);
  469. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  470. temp |= I2CR_RSTA;
  471. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  472. result = i2c_imx_bus_busy(i2c_imx, 1);
  473. if (result)
  474. goto fail0;
  475. }
  476. dev_dbg(&i2c_imx->adapter.dev,
  477. "<%s> transfer message: %d\n", __func__, i);
  478. /* write/read data */
  479. #ifdef CONFIG_I2C_DEBUG_BUS
  480. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  481. dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
  482. "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
  483. (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
  484. (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
  485. (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
  486. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
  487. dev_dbg(&i2c_imx->adapter.dev,
  488. "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
  489. "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
  490. (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
  491. (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
  492. (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
  493. (temp & I2SR_RXAK ? 1 : 0));
  494. #endif
  495. if (msgs[i].flags & I2C_M_RD)
  496. result = i2c_imx_read(i2c_imx, &msgs[i]);
  497. else
  498. result = i2c_imx_write(i2c_imx, &msgs[i]);
  499. if (result)
  500. goto fail0;
  501. }
  502. fail0:
  503. /* Stop I2C transfer */
  504. i2c_imx_stop(i2c_imx);
  505. dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
  506. (result < 0) ? "error" : "success msg",
  507. (result < 0) ? result : num);
  508. return (result < 0) ? result : num;
  509. }
  510. static u32 i2c_imx_func(struct i2c_adapter *adapter)
  511. {
  512. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  513. }
  514. static struct i2c_algorithm i2c_imx_algo = {
  515. .master_xfer = i2c_imx_xfer,
  516. .functionality = i2c_imx_func,
  517. };
  518. static int __init i2c_imx_probe(struct platform_device *pdev)
  519. {
  520. const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
  521. &pdev->dev);
  522. struct imx_i2c_struct *i2c_imx;
  523. struct resource *res;
  524. struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
  525. void __iomem *base;
  526. int irq, ret;
  527. u32 bitrate;
  528. dev_dbg(&pdev->dev, "<%s>\n", __func__);
  529. irq = platform_get_irq(pdev, 0);
  530. if (irq < 0) {
  531. dev_err(&pdev->dev, "can't get irq number\n");
  532. return -ENOENT;
  533. }
  534. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  535. base = devm_ioremap_resource(&pdev->dev, res);
  536. if (IS_ERR(base))
  537. return PTR_ERR(base);
  538. i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct),
  539. GFP_KERNEL);
  540. if (!i2c_imx) {
  541. dev_err(&pdev->dev, "can't allocate interface\n");
  542. return -ENOMEM;
  543. }
  544. if (of_id)
  545. i2c_imx->hwdata = of_id->data;
  546. else
  547. i2c_imx->hwdata = (struct imx_i2c_hwdata *)
  548. platform_get_device_id(pdev)->driver_data;
  549. /* Setup i2c_imx driver structure */
  550. strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
  551. i2c_imx->adapter.owner = THIS_MODULE;
  552. i2c_imx->adapter.algo = &i2c_imx_algo;
  553. i2c_imx->adapter.dev.parent = &pdev->dev;
  554. i2c_imx->adapter.nr = pdev->id;
  555. i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
  556. i2c_imx->base = base;
  557. /* Get I2C clock */
  558. i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
  559. if (IS_ERR(i2c_imx->clk)) {
  560. dev_err(&pdev->dev, "can't get I2C clock\n");
  561. return PTR_ERR(i2c_imx->clk);
  562. }
  563. ret = clk_prepare_enable(i2c_imx->clk);
  564. if (ret) {
  565. dev_err(&pdev->dev, "can't enable I2C clock\n");
  566. return ret;
  567. }
  568. /* Request IRQ */
  569. ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
  570. pdev->name, i2c_imx);
  571. if (ret) {
  572. dev_err(&pdev->dev, "can't claim irq %d\n", irq);
  573. return ret;
  574. }
  575. /* Init queue */
  576. init_waitqueue_head(&i2c_imx->queue);
  577. /* Set up adapter data */
  578. i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
  579. /* Set up clock divider */
  580. bitrate = IMX_I2C_BIT_RATE;
  581. ret = of_property_read_u32(pdev->dev.of_node,
  582. "clock-frequency", &bitrate);
  583. if (ret < 0 && pdata && pdata->bitrate)
  584. bitrate = pdata->bitrate;
  585. i2c_imx_set_clk(i2c_imx, bitrate);
  586. /* Set up chip registers to defaults */
  587. imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
  588. i2c_imx, IMX_I2C_I2CR);
  589. imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
  590. /* Add I2C adapter */
  591. ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
  592. if (ret < 0) {
  593. dev_err(&pdev->dev, "registration failed\n");
  594. return ret;
  595. }
  596. /* Set up platform driver data */
  597. platform_set_drvdata(pdev, i2c_imx);
  598. clk_disable_unprepare(i2c_imx->clk);
  599. dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
  600. dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
  601. res->start, res->end);
  602. dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n",
  603. resource_size(res), res->start);
  604. dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
  605. i2c_imx->adapter.name);
  606. dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
  607. return 0; /* Return OK */
  608. }
  609. static int __exit i2c_imx_remove(struct platform_device *pdev)
  610. {
  611. struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
  612. /* remove adapter */
  613. dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
  614. i2c_del_adapter(&i2c_imx->adapter);
  615. /* setup chip registers to defaults */
  616. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
  617. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
  618. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
  619. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
  620. return 0;
  621. }
  622. static struct platform_driver i2c_imx_driver = {
  623. .remove = __exit_p(i2c_imx_remove),
  624. .driver = {
  625. .name = DRIVER_NAME,
  626. .owner = THIS_MODULE,
  627. .of_match_table = i2c_imx_dt_ids,
  628. },
  629. .id_table = imx_i2c_devtype,
  630. };
  631. static int __init i2c_adap_imx_init(void)
  632. {
  633. return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
  634. }
  635. subsys_initcall(i2c_adap_imx_init);
  636. static void __exit i2c_adap_imx_exit(void)
  637. {
  638. platform_driver_unregister(&i2c_imx_driver);
  639. }
  640. module_exit(i2c_adap_imx_exit);
  641. MODULE_LICENSE("GPL");
  642. MODULE_AUTHOR("Darius Augulis");
  643. MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
  644. MODULE_ALIAS("platform:" DRIVER_NAME);