rcar_du_lvdsenc.c 4.7 KB

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  1. /*
  2. * rcar_du_lvdsenc.c -- R-Car Display Unit LVDS Encoder
  3. *
  4. * Copyright (C) 2013 Renesas Corporation
  5. *
  6. * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/io.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include "rcar_du_drv.h"
  19. #include "rcar_du_encoder.h"
  20. #include "rcar_du_lvdsenc.h"
  21. #include "rcar_lvds_regs.h"
  22. struct rcar_du_lvdsenc {
  23. struct rcar_du_device *dev;
  24. unsigned int index;
  25. void __iomem *mmio;
  26. struct clk *clock;
  27. int dpms;
  28. enum rcar_lvds_input input;
  29. };
  30. static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data)
  31. {
  32. iowrite32(data, lvds->mmio + reg);
  33. }
  34. static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
  35. struct rcar_du_crtc *rcrtc)
  36. {
  37. const struct drm_display_mode *mode = &rcrtc->crtc.mode;
  38. unsigned int freq = mode->clock;
  39. u32 lvdcr0;
  40. u32 pllcr;
  41. int ret;
  42. if (lvds->dpms == DRM_MODE_DPMS_ON)
  43. return 0;
  44. ret = clk_prepare_enable(lvds->clock);
  45. if (ret < 0)
  46. return ret;
  47. /* PLL clock configuration */
  48. if (freq <= 38000)
  49. pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
  50. else if (freq <= 60000)
  51. pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
  52. else if (freq <= 121000)
  53. pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
  54. else
  55. pllcr = LVDPLLCR_PLLDLYCNT_150M;
  56. rcar_lvds_write(lvds, LVDPLLCR, pllcr);
  57. /* Hardcode the channels and control signals routing for now.
  58. *
  59. * HSYNC -> CTRL0
  60. * VSYNC -> CTRL1
  61. * DISP -> CTRL2
  62. * 0 -> CTRL3
  63. *
  64. * Channels 1 and 3 are switched on ES1.
  65. */
  66. rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
  67. LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
  68. LVDCTRCR_CTR0SEL_HSYNC);
  69. rcar_lvds_write(lvds, LVDCHCR,
  70. LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3) |
  71. LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1));
  72. /* Select the input, hardcode mode 0, enable LVDS operation and turn
  73. * bias circuitry on.
  74. */
  75. lvdcr0 = LVDCR0_BEN | LVDCR0_LVEN;
  76. if (rcrtc->index == 2)
  77. lvdcr0 |= LVDCR0_DUSEL;
  78. rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  79. /* Turn all the channels on. */
  80. rcar_lvds_write(lvds, LVDCR1, LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
  81. LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
  82. /* Turn the PLL on, wait for the startup delay, and turn the output
  83. * on.
  84. */
  85. lvdcr0 |= LVDCR0_PLLEN;
  86. rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  87. usleep_range(100, 150);
  88. lvdcr0 |= LVDCR0_LVRES;
  89. rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  90. lvds->dpms = DRM_MODE_DPMS_ON;
  91. return 0;
  92. }
  93. static void rcar_du_lvdsenc_stop(struct rcar_du_lvdsenc *lvds)
  94. {
  95. if (lvds->dpms == DRM_MODE_DPMS_OFF)
  96. return;
  97. rcar_lvds_write(lvds, LVDCR0, 0);
  98. rcar_lvds_write(lvds, LVDCR1, 0);
  99. clk_disable_unprepare(lvds->clock);
  100. lvds->dpms = DRM_MODE_DPMS_OFF;
  101. }
  102. int rcar_du_lvdsenc_dpms(struct rcar_du_lvdsenc *lvds,
  103. struct drm_crtc *crtc, int mode)
  104. {
  105. if (mode == DRM_MODE_DPMS_OFF) {
  106. rcar_du_lvdsenc_stop(lvds);
  107. return 0;
  108. } else if (crtc) {
  109. struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
  110. return rcar_du_lvdsenc_start(lvds, rcrtc);
  111. } else
  112. return -EINVAL;
  113. }
  114. static int rcar_du_lvdsenc_get_resources(struct rcar_du_lvdsenc *lvds,
  115. struct platform_device *pdev)
  116. {
  117. struct resource *mem;
  118. char name[7];
  119. sprintf(name, "lvds.%u", lvds->index);
  120. mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
  121. if (mem == NULL) {
  122. dev_err(&pdev->dev, "failed to get memory resource for %s\n",
  123. name);
  124. return -EINVAL;
  125. }
  126. lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
  127. if (lvds->mmio == NULL) {
  128. dev_err(&pdev->dev, "failed to remap memory resource for %s\n",
  129. name);
  130. return -ENOMEM;
  131. }
  132. lvds->clock = devm_clk_get(&pdev->dev, name);
  133. if (IS_ERR(lvds->clock)) {
  134. dev_err(&pdev->dev, "failed to get clock for %s\n", name);
  135. return PTR_ERR(lvds->clock);
  136. }
  137. return 0;
  138. }
  139. int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu)
  140. {
  141. struct platform_device *pdev = to_platform_device(rcdu->dev);
  142. struct rcar_du_lvdsenc *lvds;
  143. unsigned int i;
  144. int ret;
  145. for (i = 0; i < rcdu->info->num_lvds; ++i) {
  146. lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
  147. if (lvds == NULL) {
  148. dev_err(&pdev->dev, "failed to allocate private data\n");
  149. return -ENOMEM;
  150. }
  151. lvds->dev = rcdu;
  152. lvds->index = i;
  153. lvds->input = i ? RCAR_LVDS_INPUT_DU1 : RCAR_LVDS_INPUT_DU0;
  154. lvds->dpms = DRM_MODE_DPMS_OFF;
  155. ret = rcar_du_lvdsenc_get_resources(lvds, pdev);
  156. if (ret < 0)
  157. return ret;
  158. rcdu->lvds[i] = lvds;
  159. }
  160. return 0;
  161. }