disp.h 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186
  1. #ifndef __NV04_DISPLAY_H__
  2. #define __NV04_DISPLAY_H__
  3. #include <subdev/bios/pll.h>
  4. #include "nouveau_display.h"
  5. enum nv04_fp_display_regs {
  6. FP_DISPLAY_END,
  7. FP_TOTAL,
  8. FP_CRTC,
  9. FP_SYNC_START,
  10. FP_SYNC_END,
  11. FP_VALID_START,
  12. FP_VALID_END
  13. };
  14. struct nv04_crtc_reg {
  15. unsigned char MiscOutReg;
  16. uint8_t CRTC[0xa0];
  17. uint8_t CR58[0x10];
  18. uint8_t Sequencer[5];
  19. uint8_t Graphics[9];
  20. uint8_t Attribute[21];
  21. unsigned char DAC[768];
  22. /* PCRTC regs */
  23. uint32_t fb_start;
  24. uint32_t crtc_cfg;
  25. uint32_t cursor_cfg;
  26. uint32_t gpio_ext;
  27. uint32_t crtc_830;
  28. uint32_t crtc_834;
  29. uint32_t crtc_850;
  30. uint32_t crtc_eng_ctrl;
  31. /* PRAMDAC regs */
  32. uint32_t nv10_cursync;
  33. struct nouveau_pll_vals pllvals;
  34. uint32_t ramdac_gen_ctrl;
  35. uint32_t ramdac_630;
  36. uint32_t ramdac_634;
  37. uint32_t tv_setup;
  38. uint32_t tv_vtotal;
  39. uint32_t tv_vskew;
  40. uint32_t tv_vsync_delay;
  41. uint32_t tv_htotal;
  42. uint32_t tv_hskew;
  43. uint32_t tv_hsync_delay;
  44. uint32_t tv_hsync_delay2;
  45. uint32_t fp_horiz_regs[7];
  46. uint32_t fp_vert_regs[7];
  47. uint32_t dither;
  48. uint32_t fp_control;
  49. uint32_t dither_regs[6];
  50. uint32_t fp_debug_0;
  51. uint32_t fp_debug_1;
  52. uint32_t fp_debug_2;
  53. uint32_t fp_margin_color;
  54. uint32_t ramdac_8c0;
  55. uint32_t ramdac_a20;
  56. uint32_t ramdac_a24;
  57. uint32_t ramdac_a34;
  58. uint32_t ctv_regs[38];
  59. };
  60. struct nv04_output_reg {
  61. uint32_t output;
  62. int head;
  63. };
  64. struct nv04_mode_state {
  65. struct nv04_crtc_reg crtc_reg[2];
  66. uint32_t pllsel;
  67. uint32_t sel_clk;
  68. };
  69. struct nv04_display {
  70. struct nv04_mode_state mode_reg;
  71. struct nv04_mode_state saved_reg;
  72. uint32_t saved_vga_font[4][16384];
  73. uint32_t dac_users[4];
  74. struct nouveau_object *core;
  75. struct nouveau_bo *image[2];
  76. };
  77. static inline struct nv04_display *
  78. nv04_display(struct drm_device *dev)
  79. {
  80. return nouveau_display(dev)->priv;
  81. }
  82. /* nv04_display.c */
  83. int nv04_display_early_init(struct drm_device *);
  84. void nv04_display_late_takedown(struct drm_device *);
  85. int nv04_display_create(struct drm_device *);
  86. void nv04_display_destroy(struct drm_device *);
  87. int nv04_display_init(struct drm_device *);
  88. void nv04_display_fini(struct drm_device *);
  89. /* nv04_crtc.c */
  90. int nv04_crtc_create(struct drm_device *, int index);
  91. /* nv04_dac.c */
  92. int nv04_dac_create(struct drm_connector *, struct dcb_output *);
  93. uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
  94. int nv04_dac_output_offset(struct drm_encoder *encoder);
  95. void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
  96. bool nv04_dac_in_use(struct drm_encoder *encoder);
  97. /* nv04_dfp.c */
  98. int nv04_dfp_create(struct drm_connector *, struct dcb_output *);
  99. int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent);
  100. void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
  101. int head, bool dl);
  102. void nv04_dfp_disable(struct drm_device *dev, int head);
  103. void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
  104. /* nv04_tv.c */
  105. int nv04_tv_identify(struct drm_device *dev, int i2c_index);
  106. int nv04_tv_create(struct drm_connector *, struct dcb_output *);
  107. /* nv17_tv.c */
  108. int nv17_tv_create(struct drm_connector *, struct dcb_output *);
  109. static inline bool
  110. nv_two_heads(struct drm_device *dev)
  111. {
  112. struct nouveau_drm *drm = nouveau_drm(dev);
  113. const int impl = dev->pci_device & 0x0ff0;
  114. if (nv_device(drm->device)->card_type >= NV_10 && impl != 0x0100 &&
  115. impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
  116. return true;
  117. return false;
  118. }
  119. static inline bool
  120. nv_gf4_disp_arch(struct drm_device *dev)
  121. {
  122. return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
  123. }
  124. static inline bool
  125. nv_two_reg_pll(struct drm_device *dev)
  126. {
  127. struct nouveau_drm *drm = nouveau_drm(dev);
  128. const int impl = dev->pci_device & 0x0ff0;
  129. if (impl == 0x0310 || impl == 0x0340 || nv_device(drm->device)->card_type >= NV_40)
  130. return true;
  131. return false;
  132. }
  133. static inline bool
  134. nv_match_device(struct drm_device *dev, unsigned device,
  135. unsigned sub_vendor, unsigned sub_device)
  136. {
  137. return dev->pdev->device == device &&
  138. dev->pdev->subsystem_vendor == sub_vendor &&
  139. dev->pdev->subsystem_device == sub_device;
  140. }
  141. #include <subdev/bios.h>
  142. #include <subdev/bios/init.h>
  143. static inline void
  144. nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
  145. struct dcb_output *outp, int crtc)
  146. {
  147. struct nouveau_device *device = nouveau_dev(dev);
  148. struct nouveau_bios *bios = nouveau_bios(device);
  149. struct nvbios_init init = {
  150. .subdev = nv_subdev(bios),
  151. .bios = bios,
  152. .offset = table,
  153. .outp = outp,
  154. .crtc = crtc,
  155. .execute = 1,
  156. };
  157. nvbios_exec(&init);
  158. }
  159. #endif