intel_panel.c 20 KB

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  1. /*
  2. * Copyright © 2006-2010 Intel Corporation
  3. * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Dave Airlie <airlied@linux.ie>
  27. * Jesse Barnes <jesse.barnes@intel.com>
  28. * Chris Wilson <chris@chris-wilson.co.uk>
  29. */
  30. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31. #include <linux/moduleparam.h>
  32. #include "intel_drv.h"
  33. #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
  34. void
  35. intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
  36. struct drm_display_mode *adjusted_mode)
  37. {
  38. drm_mode_copy(adjusted_mode, fixed_mode);
  39. drm_mode_set_crtcinfo(adjusted_mode, 0);
  40. }
  41. /* adjusted_mode has been preset to be the panel's fixed mode */
  42. void
  43. intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
  44. struct intel_crtc_config *pipe_config,
  45. int fitting_mode)
  46. {
  47. struct drm_display_mode *mode, *adjusted_mode;
  48. int x, y, width, height;
  49. mode = &pipe_config->requested_mode;
  50. adjusted_mode = &pipe_config->adjusted_mode;
  51. x = y = width = height = 0;
  52. /* Native modes don't need fitting */
  53. if (adjusted_mode->hdisplay == mode->hdisplay &&
  54. adjusted_mode->vdisplay == mode->vdisplay)
  55. goto done;
  56. switch (fitting_mode) {
  57. case DRM_MODE_SCALE_CENTER:
  58. width = mode->hdisplay;
  59. height = mode->vdisplay;
  60. x = (adjusted_mode->hdisplay - width + 1)/2;
  61. y = (adjusted_mode->vdisplay - height + 1)/2;
  62. break;
  63. case DRM_MODE_SCALE_ASPECT:
  64. /* Scale but preserve the aspect ratio */
  65. {
  66. u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
  67. u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
  68. if (scaled_width > scaled_height) { /* pillar */
  69. width = scaled_height / mode->vdisplay;
  70. if (width & 1)
  71. width++;
  72. x = (adjusted_mode->hdisplay - width + 1) / 2;
  73. y = 0;
  74. height = adjusted_mode->vdisplay;
  75. } else if (scaled_width < scaled_height) { /* letter */
  76. height = scaled_width / mode->hdisplay;
  77. if (height & 1)
  78. height++;
  79. y = (adjusted_mode->vdisplay - height + 1) / 2;
  80. x = 0;
  81. width = adjusted_mode->hdisplay;
  82. } else {
  83. x = y = 0;
  84. width = adjusted_mode->hdisplay;
  85. height = adjusted_mode->vdisplay;
  86. }
  87. }
  88. break;
  89. case DRM_MODE_SCALE_FULLSCREEN:
  90. x = y = 0;
  91. width = adjusted_mode->hdisplay;
  92. height = adjusted_mode->vdisplay;
  93. break;
  94. default:
  95. WARN(1, "bad panel fit mode: %d\n", fitting_mode);
  96. return;
  97. }
  98. done:
  99. pipe_config->pch_pfit.pos = (x << 16) | y;
  100. pipe_config->pch_pfit.size = (width << 16) | height;
  101. pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
  102. }
  103. static void
  104. centre_horizontally(struct drm_display_mode *mode,
  105. int width)
  106. {
  107. u32 border, sync_pos, blank_width, sync_width;
  108. /* keep the hsync and hblank widths constant */
  109. sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
  110. blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
  111. sync_pos = (blank_width - sync_width + 1) / 2;
  112. border = (mode->hdisplay - width + 1) / 2;
  113. border += border & 1; /* make the border even */
  114. mode->crtc_hdisplay = width;
  115. mode->crtc_hblank_start = width + border;
  116. mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
  117. mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
  118. mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
  119. }
  120. static void
  121. centre_vertically(struct drm_display_mode *mode,
  122. int height)
  123. {
  124. u32 border, sync_pos, blank_width, sync_width;
  125. /* keep the vsync and vblank widths constant */
  126. sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
  127. blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
  128. sync_pos = (blank_width - sync_width + 1) / 2;
  129. border = (mode->vdisplay - height + 1) / 2;
  130. mode->crtc_vdisplay = height;
  131. mode->crtc_vblank_start = height + border;
  132. mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
  133. mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
  134. mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
  135. }
  136. static inline u32 panel_fitter_scaling(u32 source, u32 target)
  137. {
  138. /*
  139. * Floating point operation is not supported. So the FACTOR
  140. * is defined, which can avoid the floating point computation
  141. * when calculating the panel ratio.
  142. */
  143. #define ACCURACY 12
  144. #define FACTOR (1 << ACCURACY)
  145. u32 ratio = source * FACTOR / target;
  146. return (FACTOR * ratio + FACTOR/2) / FACTOR;
  147. }
  148. void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
  149. struct intel_crtc_config *pipe_config,
  150. int fitting_mode)
  151. {
  152. struct drm_device *dev = intel_crtc->base.dev;
  153. u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
  154. struct drm_display_mode *mode, *adjusted_mode;
  155. mode = &pipe_config->requested_mode;
  156. adjusted_mode = &pipe_config->adjusted_mode;
  157. /* Native modes don't need fitting */
  158. if (adjusted_mode->hdisplay == mode->hdisplay &&
  159. adjusted_mode->vdisplay == mode->vdisplay)
  160. goto out;
  161. switch (fitting_mode) {
  162. case DRM_MODE_SCALE_CENTER:
  163. /*
  164. * For centered modes, we have to calculate border widths &
  165. * heights and modify the values programmed into the CRTC.
  166. */
  167. centre_horizontally(adjusted_mode, mode->hdisplay);
  168. centre_vertically(adjusted_mode, mode->vdisplay);
  169. border = LVDS_BORDER_ENABLE;
  170. break;
  171. case DRM_MODE_SCALE_ASPECT:
  172. /* Scale but preserve the aspect ratio */
  173. if (INTEL_INFO(dev)->gen >= 4) {
  174. u32 scaled_width = adjusted_mode->hdisplay *
  175. mode->vdisplay;
  176. u32 scaled_height = mode->hdisplay *
  177. adjusted_mode->vdisplay;
  178. /* 965+ is easy, it does everything in hw */
  179. if (scaled_width > scaled_height)
  180. pfit_control |= PFIT_ENABLE |
  181. PFIT_SCALING_PILLAR;
  182. else if (scaled_width < scaled_height)
  183. pfit_control |= PFIT_ENABLE |
  184. PFIT_SCALING_LETTER;
  185. else if (adjusted_mode->hdisplay != mode->hdisplay)
  186. pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
  187. } else {
  188. u32 scaled_width = adjusted_mode->hdisplay *
  189. mode->vdisplay;
  190. u32 scaled_height = mode->hdisplay *
  191. adjusted_mode->vdisplay;
  192. /*
  193. * For earlier chips we have to calculate the scaling
  194. * ratio by hand and program it into the
  195. * PFIT_PGM_RATIO register
  196. */
  197. if (scaled_width > scaled_height) { /* pillar */
  198. centre_horizontally(adjusted_mode,
  199. scaled_height /
  200. mode->vdisplay);
  201. border = LVDS_BORDER_ENABLE;
  202. if (mode->vdisplay != adjusted_mode->vdisplay) {
  203. u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
  204. pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  205. bits << PFIT_VERT_SCALE_SHIFT);
  206. pfit_control |= (PFIT_ENABLE |
  207. VERT_INTERP_BILINEAR |
  208. HORIZ_INTERP_BILINEAR);
  209. }
  210. } else if (scaled_width < scaled_height) { /* letter */
  211. centre_vertically(adjusted_mode,
  212. scaled_width /
  213. mode->hdisplay);
  214. border = LVDS_BORDER_ENABLE;
  215. if (mode->hdisplay != adjusted_mode->hdisplay) {
  216. u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
  217. pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  218. bits << PFIT_VERT_SCALE_SHIFT);
  219. pfit_control |= (PFIT_ENABLE |
  220. VERT_INTERP_BILINEAR |
  221. HORIZ_INTERP_BILINEAR);
  222. }
  223. } else {
  224. /* Aspects match, Let hw scale both directions */
  225. pfit_control |= (PFIT_ENABLE |
  226. VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
  227. VERT_INTERP_BILINEAR |
  228. HORIZ_INTERP_BILINEAR);
  229. }
  230. }
  231. break;
  232. case DRM_MODE_SCALE_FULLSCREEN:
  233. /*
  234. * Full scaling, even if it changes the aspect ratio.
  235. * Fortunately this is all done for us in hw.
  236. */
  237. if (mode->vdisplay != adjusted_mode->vdisplay ||
  238. mode->hdisplay != adjusted_mode->hdisplay) {
  239. pfit_control |= PFIT_ENABLE;
  240. if (INTEL_INFO(dev)->gen >= 4)
  241. pfit_control |= PFIT_SCALING_AUTO;
  242. else
  243. pfit_control |= (VERT_AUTO_SCALE |
  244. VERT_INTERP_BILINEAR |
  245. HORIZ_AUTO_SCALE |
  246. HORIZ_INTERP_BILINEAR);
  247. }
  248. break;
  249. default:
  250. WARN(1, "bad panel fit mode: %d\n", fitting_mode);
  251. return;
  252. }
  253. /* 965+ wants fuzzy fitting */
  254. /* FIXME: handle multiple panels by failing gracefully */
  255. if (INTEL_INFO(dev)->gen >= 4)
  256. pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
  257. PFIT_FILTER_FUZZY);
  258. out:
  259. if ((pfit_control & PFIT_ENABLE) == 0) {
  260. pfit_control = 0;
  261. pfit_pgm_ratios = 0;
  262. }
  263. /* Make sure pre-965 set dither correctly for 18bpp panels. */
  264. if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
  265. pfit_control |= PANEL_8TO6_DITHER_ENABLE;
  266. pipe_config->gmch_pfit.control = pfit_control;
  267. pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
  268. pipe_config->gmch_pfit.lvds_border_bits = border;
  269. }
  270. static int is_backlight_combination_mode(struct drm_device *dev)
  271. {
  272. struct drm_i915_private *dev_priv = dev->dev_private;
  273. if (INTEL_INFO(dev)->gen >= 4)
  274. return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
  275. if (IS_GEN2(dev))
  276. return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
  277. return 0;
  278. }
  279. /* XXX: query mode clock or hardware clock and program max PWM appropriately
  280. * when it's 0.
  281. */
  282. static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
  283. {
  284. struct drm_i915_private *dev_priv = dev->dev_private;
  285. u32 val;
  286. WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));
  287. /* Restore the CTL value if it lost, e.g. GPU reset */
  288. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  289. val = I915_READ(BLC_PWM_PCH_CTL2);
  290. if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
  291. dev_priv->regfile.saveBLC_PWM_CTL2 = val;
  292. } else if (val == 0) {
  293. val = dev_priv->regfile.saveBLC_PWM_CTL2;
  294. I915_WRITE(BLC_PWM_PCH_CTL2, val);
  295. }
  296. } else {
  297. val = I915_READ(BLC_PWM_CTL);
  298. if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
  299. dev_priv->regfile.saveBLC_PWM_CTL = val;
  300. if (INTEL_INFO(dev)->gen >= 4)
  301. dev_priv->regfile.saveBLC_PWM_CTL2 =
  302. I915_READ(BLC_PWM_CTL2);
  303. } else if (val == 0) {
  304. val = dev_priv->regfile.saveBLC_PWM_CTL;
  305. I915_WRITE(BLC_PWM_CTL, val);
  306. if (INTEL_INFO(dev)->gen >= 4)
  307. I915_WRITE(BLC_PWM_CTL2,
  308. dev_priv->regfile.saveBLC_PWM_CTL2);
  309. }
  310. }
  311. return val;
  312. }
  313. static u32 intel_panel_get_max_backlight(struct drm_device *dev)
  314. {
  315. u32 max;
  316. max = i915_read_blc_pwm_ctl(dev);
  317. if (HAS_PCH_SPLIT(dev)) {
  318. max >>= 16;
  319. } else {
  320. if (INTEL_INFO(dev)->gen < 4)
  321. max >>= 17;
  322. else
  323. max >>= 16;
  324. if (is_backlight_combination_mode(dev))
  325. max *= 0xff;
  326. }
  327. DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
  328. return max;
  329. }
  330. static int i915_panel_invert_brightness;
  331. MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
  332. "(-1 force normal, 0 machine defaults, 1 force inversion), please "
  333. "report PCI device ID, subsystem vendor and subsystem device ID "
  334. "to dri-devel@lists.freedesktop.org, if your machine needs it. "
  335. "It will then be included in an upcoming module version.");
  336. module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
  337. static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
  338. {
  339. struct drm_i915_private *dev_priv = dev->dev_private;
  340. if (i915_panel_invert_brightness < 0)
  341. return val;
  342. if (i915_panel_invert_brightness > 0 ||
  343. dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
  344. u32 max = intel_panel_get_max_backlight(dev);
  345. if (max)
  346. return max - val;
  347. }
  348. return val;
  349. }
  350. static u32 intel_panel_get_backlight(struct drm_device *dev)
  351. {
  352. struct drm_i915_private *dev_priv = dev->dev_private;
  353. u32 val;
  354. unsigned long flags;
  355. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  356. if (HAS_PCH_SPLIT(dev)) {
  357. val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  358. } else {
  359. val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  360. if (INTEL_INFO(dev)->gen < 4)
  361. val >>= 1;
  362. if (is_backlight_combination_mode(dev)) {
  363. u8 lbpc;
  364. pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
  365. val *= lbpc;
  366. }
  367. }
  368. val = intel_panel_compute_brightness(dev, val);
  369. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  370. DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
  371. return val;
  372. }
  373. static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
  374. {
  375. struct drm_i915_private *dev_priv = dev->dev_private;
  376. u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
  377. I915_WRITE(BLC_PWM_CPU_CTL, val | level);
  378. }
  379. static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level)
  380. {
  381. struct drm_i915_private *dev_priv = dev->dev_private;
  382. u32 tmp;
  383. DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
  384. level = intel_panel_compute_brightness(dev, level);
  385. if (HAS_PCH_SPLIT(dev))
  386. return intel_pch_panel_set_backlight(dev, level);
  387. if (is_backlight_combination_mode(dev)) {
  388. u32 max = intel_panel_get_max_backlight(dev);
  389. u8 lbpc;
  390. /* we're screwed, but keep behaviour backwards compatible */
  391. if (!max)
  392. max = 1;
  393. lbpc = level * 0xfe / max + 1;
  394. level /= lbpc;
  395. pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
  396. }
  397. tmp = I915_READ(BLC_PWM_CTL);
  398. if (INTEL_INFO(dev)->gen < 4)
  399. level <<= 1;
  400. tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
  401. I915_WRITE(BLC_PWM_CTL, tmp | level);
  402. }
  403. /* set backlight brightness to level in range [0..max] */
  404. void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max)
  405. {
  406. struct drm_i915_private *dev_priv = dev->dev_private;
  407. u32 freq;
  408. unsigned long flags;
  409. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  410. freq = intel_panel_get_max_backlight(dev);
  411. if (!freq) {
  412. /* we are screwed, bail out */
  413. goto out;
  414. }
  415. /* scale to hardware, but be careful to not overflow */
  416. if (freq < max)
  417. level = level * freq / max;
  418. else
  419. level = freq / max * level;
  420. dev_priv->backlight.level = level;
  421. if (dev_priv->backlight.device)
  422. dev_priv->backlight.device->props.brightness = level;
  423. if (dev_priv->backlight.enabled)
  424. intel_panel_actually_set_backlight(dev, level);
  425. out:
  426. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  427. }
  428. void intel_panel_disable_backlight(struct drm_device *dev)
  429. {
  430. struct drm_i915_private *dev_priv = dev->dev_private;
  431. unsigned long flags;
  432. /*
  433. * Do not disable backlight on the vgaswitcheroo path. When switching
  434. * away from i915, the other client may depend on i915 to handle the
  435. * backlight. This will leave the backlight on unnecessarily when
  436. * another client is not activated.
  437. */
  438. if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
  439. DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
  440. return;
  441. }
  442. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  443. dev_priv->backlight.enabled = false;
  444. intel_panel_actually_set_backlight(dev, 0);
  445. if (INTEL_INFO(dev)->gen >= 4) {
  446. uint32_t reg, tmp;
  447. reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
  448. I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
  449. if (HAS_PCH_SPLIT(dev)) {
  450. tmp = I915_READ(BLC_PWM_PCH_CTL1);
  451. tmp &= ~BLM_PCH_PWM_ENABLE;
  452. I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
  453. }
  454. }
  455. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  456. }
  457. void intel_panel_enable_backlight(struct drm_device *dev,
  458. enum pipe pipe)
  459. {
  460. struct drm_i915_private *dev_priv = dev->dev_private;
  461. enum transcoder cpu_transcoder =
  462. intel_pipe_to_cpu_transcoder(dev_priv, pipe);
  463. unsigned long flags;
  464. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  465. if (dev_priv->backlight.level == 0) {
  466. dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
  467. if (dev_priv->backlight.device)
  468. dev_priv->backlight.device->props.brightness =
  469. dev_priv->backlight.level;
  470. }
  471. if (INTEL_INFO(dev)->gen >= 4) {
  472. uint32_t reg, tmp;
  473. reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
  474. tmp = I915_READ(reg);
  475. /* Note that this can also get called through dpms changes. And
  476. * we don't track the backlight dpms state, hence check whether
  477. * we have to do anything first. */
  478. if (tmp & BLM_PWM_ENABLE)
  479. goto set_level;
  480. if (INTEL_INFO(dev)->num_pipes == 3)
  481. tmp &= ~BLM_PIPE_SELECT_IVB;
  482. else
  483. tmp &= ~BLM_PIPE_SELECT;
  484. if (cpu_transcoder == TRANSCODER_EDP)
  485. tmp |= BLM_TRANSCODER_EDP;
  486. else
  487. tmp |= BLM_PIPE(cpu_transcoder);
  488. tmp &= ~BLM_PWM_ENABLE;
  489. I915_WRITE(reg, tmp);
  490. POSTING_READ(reg);
  491. I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
  492. if (HAS_PCH_SPLIT(dev) &&
  493. !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
  494. tmp = I915_READ(BLC_PWM_PCH_CTL1);
  495. tmp |= BLM_PCH_PWM_ENABLE;
  496. tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
  497. I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
  498. }
  499. }
  500. set_level:
  501. /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
  502. * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
  503. * registers are set.
  504. */
  505. dev_priv->backlight.enabled = true;
  506. intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
  507. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  508. }
  509. static void intel_panel_init_backlight(struct drm_device *dev)
  510. {
  511. struct drm_i915_private *dev_priv = dev->dev_private;
  512. dev_priv->backlight.level = intel_panel_get_backlight(dev);
  513. dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
  514. }
  515. enum drm_connector_status
  516. intel_panel_detect(struct drm_device *dev)
  517. {
  518. struct drm_i915_private *dev_priv = dev->dev_private;
  519. /* Assume that the BIOS does not lie through the OpRegion... */
  520. if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
  521. return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
  522. connector_status_connected :
  523. connector_status_disconnected;
  524. }
  525. switch (i915_panel_ignore_lid) {
  526. case -2:
  527. return connector_status_connected;
  528. case -1:
  529. return connector_status_disconnected;
  530. default:
  531. return connector_status_unknown;
  532. }
  533. }
  534. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  535. static int intel_panel_update_status(struct backlight_device *bd)
  536. {
  537. struct drm_device *dev = bl_get_data(bd);
  538. intel_panel_set_backlight(dev, bd->props.brightness,
  539. bd->props.max_brightness);
  540. return 0;
  541. }
  542. static int intel_panel_get_brightness(struct backlight_device *bd)
  543. {
  544. struct drm_device *dev = bl_get_data(bd);
  545. return intel_panel_get_backlight(dev);
  546. }
  547. static const struct backlight_ops intel_panel_bl_ops = {
  548. .update_status = intel_panel_update_status,
  549. .get_brightness = intel_panel_get_brightness,
  550. };
  551. int intel_panel_setup_backlight(struct drm_connector *connector)
  552. {
  553. struct drm_device *dev = connector->dev;
  554. struct drm_i915_private *dev_priv = dev->dev_private;
  555. struct backlight_properties props;
  556. unsigned long flags;
  557. intel_panel_init_backlight(dev);
  558. if (WARN_ON(dev_priv->backlight.device))
  559. return -ENODEV;
  560. memset(&props, 0, sizeof(props));
  561. props.type = BACKLIGHT_RAW;
  562. props.brightness = dev_priv->backlight.level;
  563. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  564. props.max_brightness = intel_panel_get_max_backlight(dev);
  565. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  566. if (props.max_brightness == 0) {
  567. DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
  568. return -ENODEV;
  569. }
  570. dev_priv->backlight.device =
  571. backlight_device_register("intel_backlight",
  572. &connector->kdev, dev,
  573. &intel_panel_bl_ops, &props);
  574. if (IS_ERR(dev_priv->backlight.device)) {
  575. DRM_ERROR("Failed to register backlight: %ld\n",
  576. PTR_ERR(dev_priv->backlight.device));
  577. dev_priv->backlight.device = NULL;
  578. return -ENODEV;
  579. }
  580. return 0;
  581. }
  582. void intel_panel_destroy_backlight(struct drm_device *dev)
  583. {
  584. struct drm_i915_private *dev_priv = dev->dev_private;
  585. if (dev_priv->backlight.device) {
  586. backlight_device_unregister(dev_priv->backlight.device);
  587. dev_priv->backlight.device = NULL;
  588. }
  589. }
  590. #else
  591. int intel_panel_setup_backlight(struct drm_connector *connector)
  592. {
  593. intel_panel_init_backlight(connector->dev);
  594. return 0;
  595. }
  596. void intel_panel_destroy_backlight(struct drm_device *dev)
  597. {
  598. return;
  599. }
  600. #endif
  601. int intel_panel_init(struct intel_panel *panel,
  602. struct drm_display_mode *fixed_mode)
  603. {
  604. panel->fixed_mode = fixed_mode;
  605. return 0;
  606. }
  607. void intel_panel_fini(struct intel_panel *panel)
  608. {
  609. struct intel_connector *intel_connector =
  610. container_of(panel, struct intel_connector, panel);
  611. if (panel->fixed_mode)
  612. drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
  613. }