i810_dma.c 33 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include <drm/drmP.h>
  33. #include <drm/i810_drm.h>
  34. #include "i810_drv.h"
  35. #include <linux/interrupt.h> /* For task queue support */
  36. #include <linux/delay.h>
  37. #include <linux/slab.h>
  38. #include <linux/pagemap.h>
  39. #define I810_BUF_FREE 2
  40. #define I810_BUF_CLIENT 1
  41. #define I810_BUF_HARDWARE 0
  42. #define I810_BUF_UNMAPPED 0
  43. #define I810_BUF_MAPPED 1
  44. static struct drm_buf *i810_freelist_get(struct drm_device * dev)
  45. {
  46. struct drm_device_dma *dma = dev->dma;
  47. int i;
  48. int used;
  49. /* Linear search might not be the best solution */
  50. for (i = 0; i < dma->buf_count; i++) {
  51. struct drm_buf *buf = dma->buflist[i];
  52. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  53. /* In use is already a pointer */
  54. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  55. I810_BUF_CLIENT);
  56. if (used == I810_BUF_FREE)
  57. return buf;
  58. }
  59. return NULL;
  60. }
  61. /* This should only be called if the buffer is not sent to the hardware
  62. * yet, the hardware updates in use for us once its on the ring buffer.
  63. */
  64. static int i810_freelist_put(struct drm_device *dev, struct drm_buf *buf)
  65. {
  66. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  67. int used;
  68. /* In use is already a pointer */
  69. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  70. if (used != I810_BUF_CLIENT) {
  71. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  72. return -EINVAL;
  73. }
  74. return 0;
  75. }
  76. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  77. {
  78. struct drm_file *priv = filp->private_data;
  79. struct drm_device *dev;
  80. drm_i810_private_t *dev_priv;
  81. struct drm_buf *buf;
  82. drm_i810_buf_priv_t *buf_priv;
  83. dev = priv->minor->dev;
  84. dev_priv = dev->dev_private;
  85. buf = dev_priv->mmap_buffer;
  86. buf_priv = buf->dev_private;
  87. vma->vm_flags |= VM_DONTCOPY;
  88. buf_priv->currently_mapped = I810_BUF_MAPPED;
  89. if (io_remap_pfn_range(vma, vma->vm_start,
  90. vma->vm_pgoff,
  91. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  92. return -EAGAIN;
  93. return 0;
  94. }
  95. static const struct file_operations i810_buffer_fops = {
  96. .open = drm_open,
  97. .release = drm_release,
  98. .unlocked_ioctl = drm_ioctl,
  99. .mmap = i810_mmap_buffers,
  100. #ifdef CONFIG_COMPAT
  101. .compat_ioctl = drm_compat_ioctl,
  102. #endif
  103. .llseek = noop_llseek,
  104. };
  105. static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv)
  106. {
  107. struct drm_device *dev = file_priv->minor->dev;
  108. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  109. drm_i810_private_t *dev_priv = dev->dev_private;
  110. const struct file_operations *old_fops;
  111. int retcode = 0;
  112. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  113. return -EINVAL;
  114. /* This is all entirely broken */
  115. old_fops = file_priv->filp->f_op;
  116. file_priv->filp->f_op = &i810_buffer_fops;
  117. dev_priv->mmap_buffer = buf;
  118. buf_priv->virtual = (void *)vm_mmap(file_priv->filp, 0, buf->total,
  119. PROT_READ | PROT_WRITE,
  120. MAP_SHARED, buf->bus_address);
  121. dev_priv->mmap_buffer = NULL;
  122. file_priv->filp->f_op = old_fops;
  123. if (IS_ERR(buf_priv->virtual)) {
  124. /* Real error */
  125. DRM_ERROR("mmap error\n");
  126. retcode = PTR_ERR(buf_priv->virtual);
  127. buf_priv->virtual = NULL;
  128. }
  129. return retcode;
  130. }
  131. static int i810_unmap_buffer(struct drm_buf *buf)
  132. {
  133. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  134. int retcode = 0;
  135. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  136. return -EINVAL;
  137. retcode = vm_munmap((unsigned long)buf_priv->virtual,
  138. (size_t) buf->total);
  139. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  140. buf_priv->virtual = NULL;
  141. return retcode;
  142. }
  143. static int i810_dma_get_buffer(struct drm_device *dev, drm_i810_dma_t *d,
  144. struct drm_file *file_priv)
  145. {
  146. struct drm_buf *buf;
  147. drm_i810_buf_priv_t *buf_priv;
  148. int retcode = 0;
  149. buf = i810_freelist_get(dev);
  150. if (!buf) {
  151. retcode = -ENOMEM;
  152. DRM_DEBUG("retcode=%d\n", retcode);
  153. return retcode;
  154. }
  155. retcode = i810_map_buffer(buf, file_priv);
  156. if (retcode) {
  157. i810_freelist_put(dev, buf);
  158. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  159. return retcode;
  160. }
  161. buf->file_priv = file_priv;
  162. buf_priv = buf->dev_private;
  163. d->granted = 1;
  164. d->request_idx = buf->idx;
  165. d->request_size = buf->total;
  166. d->virtual = buf_priv->virtual;
  167. return retcode;
  168. }
  169. static int i810_dma_cleanup(struct drm_device *dev)
  170. {
  171. struct drm_device_dma *dma = dev->dma;
  172. /* Make sure interrupts are disabled here because the uninstall ioctl
  173. * may not have been called from userspace and after dev_private
  174. * is freed, it's too late.
  175. */
  176. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  177. drm_irq_uninstall(dev);
  178. if (dev->dev_private) {
  179. int i;
  180. drm_i810_private_t *dev_priv =
  181. (drm_i810_private_t *) dev->dev_private;
  182. if (dev_priv->ring.virtual_start)
  183. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  184. if (dev_priv->hw_status_page) {
  185. pci_free_consistent(dev->pdev, PAGE_SIZE,
  186. dev_priv->hw_status_page,
  187. dev_priv->dma_status_page);
  188. }
  189. kfree(dev->dev_private);
  190. dev->dev_private = NULL;
  191. for (i = 0; i < dma->buf_count; i++) {
  192. struct drm_buf *buf = dma->buflist[i];
  193. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  194. if (buf_priv->kernel_virtual && buf->total)
  195. drm_core_ioremapfree(&buf_priv->map, dev);
  196. }
  197. }
  198. return 0;
  199. }
  200. static int i810_wait_ring(struct drm_device *dev, int n)
  201. {
  202. drm_i810_private_t *dev_priv = dev->dev_private;
  203. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  204. int iters = 0;
  205. unsigned long end;
  206. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  207. end = jiffies + (HZ * 3);
  208. while (ring->space < n) {
  209. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  210. ring->space = ring->head - (ring->tail + 8);
  211. if (ring->space < 0)
  212. ring->space += ring->Size;
  213. if (ring->head != last_head) {
  214. end = jiffies + (HZ * 3);
  215. last_head = ring->head;
  216. }
  217. iters++;
  218. if (time_before(end, jiffies)) {
  219. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  220. DRM_ERROR("lockup\n");
  221. goto out_wait_ring;
  222. }
  223. udelay(1);
  224. }
  225. out_wait_ring:
  226. return iters;
  227. }
  228. static void i810_kernel_lost_context(struct drm_device *dev)
  229. {
  230. drm_i810_private_t *dev_priv = dev->dev_private;
  231. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  232. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  233. ring->tail = I810_READ(LP_RING + RING_TAIL);
  234. ring->space = ring->head - (ring->tail + 8);
  235. if (ring->space < 0)
  236. ring->space += ring->Size;
  237. }
  238. static int i810_freelist_init(struct drm_device *dev, drm_i810_private_t *dev_priv)
  239. {
  240. struct drm_device_dma *dma = dev->dma;
  241. int my_idx = 24;
  242. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  243. int i;
  244. if (dma->buf_count > 1019) {
  245. /* Not enough space in the status page for the freelist */
  246. return -EINVAL;
  247. }
  248. for (i = 0; i < dma->buf_count; i++) {
  249. struct drm_buf *buf = dma->buflist[i];
  250. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  251. buf_priv->in_use = hw_status++;
  252. buf_priv->my_use_idx = my_idx;
  253. my_idx += 4;
  254. *buf_priv->in_use = I810_BUF_FREE;
  255. buf_priv->map.offset = buf->bus_address;
  256. buf_priv->map.size = buf->total;
  257. buf_priv->map.type = _DRM_AGP;
  258. buf_priv->map.flags = 0;
  259. buf_priv->map.mtrr = 0;
  260. drm_core_ioremap(&buf_priv->map, dev);
  261. buf_priv->kernel_virtual = buf_priv->map.handle;
  262. }
  263. return 0;
  264. }
  265. static int i810_dma_initialize(struct drm_device *dev,
  266. drm_i810_private_t *dev_priv,
  267. drm_i810_init_t *init)
  268. {
  269. struct drm_map_list *r_list;
  270. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  271. list_for_each_entry(r_list, &dev->maplist, head) {
  272. if (r_list->map &&
  273. r_list->map->type == _DRM_SHM &&
  274. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  275. dev_priv->sarea_map = r_list->map;
  276. break;
  277. }
  278. }
  279. if (!dev_priv->sarea_map) {
  280. dev->dev_private = (void *)dev_priv;
  281. i810_dma_cleanup(dev);
  282. DRM_ERROR("can not find sarea!\n");
  283. return -EINVAL;
  284. }
  285. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  286. if (!dev_priv->mmio_map) {
  287. dev->dev_private = (void *)dev_priv;
  288. i810_dma_cleanup(dev);
  289. DRM_ERROR("can not find mmio map!\n");
  290. return -EINVAL;
  291. }
  292. dev->agp_buffer_token = init->buffers_offset;
  293. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  294. if (!dev->agp_buffer_map) {
  295. dev->dev_private = (void *)dev_priv;
  296. i810_dma_cleanup(dev);
  297. DRM_ERROR("can not find dma buffer map!\n");
  298. return -EINVAL;
  299. }
  300. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  301. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  302. dev_priv->ring.Start = init->ring_start;
  303. dev_priv->ring.End = init->ring_end;
  304. dev_priv->ring.Size = init->ring_size;
  305. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  306. dev_priv->ring.map.size = init->ring_size;
  307. dev_priv->ring.map.type = _DRM_AGP;
  308. dev_priv->ring.map.flags = 0;
  309. dev_priv->ring.map.mtrr = 0;
  310. drm_core_ioremap(&dev_priv->ring.map, dev);
  311. if (dev_priv->ring.map.handle == NULL) {
  312. dev->dev_private = (void *)dev_priv;
  313. i810_dma_cleanup(dev);
  314. DRM_ERROR("can not ioremap virtual address for"
  315. " ring buffer\n");
  316. return -ENOMEM;
  317. }
  318. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  319. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  320. dev_priv->w = init->w;
  321. dev_priv->h = init->h;
  322. dev_priv->pitch = init->pitch;
  323. dev_priv->back_offset = init->back_offset;
  324. dev_priv->depth_offset = init->depth_offset;
  325. dev_priv->front_offset = init->front_offset;
  326. dev_priv->overlay_offset = init->overlay_offset;
  327. dev_priv->overlay_physical = init->overlay_physical;
  328. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  329. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  330. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  331. /* Program Hardware Status Page */
  332. dev_priv->hw_status_page =
  333. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  334. &dev_priv->dma_status_page);
  335. if (!dev_priv->hw_status_page) {
  336. dev->dev_private = (void *)dev_priv;
  337. i810_dma_cleanup(dev);
  338. DRM_ERROR("Can not allocate hardware status page\n");
  339. return -ENOMEM;
  340. }
  341. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  342. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  343. I810_WRITE(0x02080, dev_priv->dma_status_page);
  344. DRM_DEBUG("Enabled hardware status page\n");
  345. /* Now we need to init our freelist */
  346. if (i810_freelist_init(dev, dev_priv) != 0) {
  347. dev->dev_private = (void *)dev_priv;
  348. i810_dma_cleanup(dev);
  349. DRM_ERROR("Not enough space in the status page for"
  350. " the freelist\n");
  351. return -ENOMEM;
  352. }
  353. dev->dev_private = (void *)dev_priv;
  354. return 0;
  355. }
  356. static int i810_dma_init(struct drm_device *dev, void *data,
  357. struct drm_file *file_priv)
  358. {
  359. drm_i810_private_t *dev_priv;
  360. drm_i810_init_t *init = data;
  361. int retcode = 0;
  362. switch (init->func) {
  363. case I810_INIT_DMA_1_4:
  364. DRM_INFO("Using v1.4 init.\n");
  365. dev_priv = kmalloc(sizeof(drm_i810_private_t), GFP_KERNEL);
  366. if (dev_priv == NULL)
  367. return -ENOMEM;
  368. retcode = i810_dma_initialize(dev, dev_priv, init);
  369. break;
  370. case I810_CLEANUP_DMA:
  371. DRM_INFO("DMA Cleanup\n");
  372. retcode = i810_dma_cleanup(dev);
  373. break;
  374. default:
  375. return -EINVAL;
  376. }
  377. return retcode;
  378. }
  379. /* Most efficient way to verify state for the i810 is as it is
  380. * emitted. Non-conformant state is silently dropped.
  381. *
  382. * Use 'volatile' & local var tmp to force the emitted values to be
  383. * identical to the verified ones.
  384. */
  385. static void i810EmitContextVerified(struct drm_device *dev,
  386. volatile unsigned int *code)
  387. {
  388. drm_i810_private_t *dev_priv = dev->dev_private;
  389. int i, j = 0;
  390. unsigned int tmp;
  391. RING_LOCALS;
  392. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  393. OUT_RING(GFX_OP_COLOR_FACTOR);
  394. OUT_RING(code[I810_CTXREG_CF1]);
  395. OUT_RING(GFX_OP_STIPPLE);
  396. OUT_RING(code[I810_CTXREG_ST1]);
  397. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  398. tmp = code[i];
  399. if ((tmp & (7 << 29)) == (3 << 29) &&
  400. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  401. OUT_RING(tmp);
  402. j++;
  403. } else
  404. printk("constext state dropped!!!\n");
  405. }
  406. if (j & 1)
  407. OUT_RING(0);
  408. ADVANCE_LP_RING();
  409. }
  410. static void i810EmitTexVerified(struct drm_device *dev, volatile unsigned int *code)
  411. {
  412. drm_i810_private_t *dev_priv = dev->dev_private;
  413. int i, j = 0;
  414. unsigned int tmp;
  415. RING_LOCALS;
  416. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  417. OUT_RING(GFX_OP_MAP_INFO);
  418. OUT_RING(code[I810_TEXREG_MI1]);
  419. OUT_RING(code[I810_TEXREG_MI2]);
  420. OUT_RING(code[I810_TEXREG_MI3]);
  421. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  422. tmp = code[i];
  423. if ((tmp & (7 << 29)) == (3 << 29) &&
  424. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  425. OUT_RING(tmp);
  426. j++;
  427. } else
  428. printk("texture state dropped!!!\n");
  429. }
  430. if (j & 1)
  431. OUT_RING(0);
  432. ADVANCE_LP_RING();
  433. }
  434. /* Need to do some additional checking when setting the dest buffer.
  435. */
  436. static void i810EmitDestVerified(struct drm_device *dev,
  437. volatile unsigned int *code)
  438. {
  439. drm_i810_private_t *dev_priv = dev->dev_private;
  440. unsigned int tmp;
  441. RING_LOCALS;
  442. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  443. tmp = code[I810_DESTREG_DI1];
  444. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  445. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  446. OUT_RING(tmp);
  447. } else
  448. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  449. tmp, dev_priv->front_di1, dev_priv->back_di1);
  450. /* invarient:
  451. */
  452. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  453. OUT_RING(dev_priv->zi1);
  454. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  455. OUT_RING(code[I810_DESTREG_DV1]);
  456. OUT_RING(GFX_OP_DRAWRECT_INFO);
  457. OUT_RING(code[I810_DESTREG_DR1]);
  458. OUT_RING(code[I810_DESTREG_DR2]);
  459. OUT_RING(code[I810_DESTREG_DR3]);
  460. OUT_RING(code[I810_DESTREG_DR4]);
  461. OUT_RING(0);
  462. ADVANCE_LP_RING();
  463. }
  464. static void i810EmitState(struct drm_device *dev)
  465. {
  466. drm_i810_private_t *dev_priv = dev->dev_private;
  467. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  468. unsigned int dirty = sarea_priv->dirty;
  469. DRM_DEBUG("%x\n", dirty);
  470. if (dirty & I810_UPLOAD_BUFFERS) {
  471. i810EmitDestVerified(dev, sarea_priv->BufferState);
  472. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  473. }
  474. if (dirty & I810_UPLOAD_CTX) {
  475. i810EmitContextVerified(dev, sarea_priv->ContextState);
  476. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  477. }
  478. if (dirty & I810_UPLOAD_TEX0) {
  479. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  480. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  481. }
  482. if (dirty & I810_UPLOAD_TEX1) {
  483. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  484. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  485. }
  486. }
  487. /* need to verify
  488. */
  489. static void i810_dma_dispatch_clear(struct drm_device *dev, int flags,
  490. unsigned int clear_color,
  491. unsigned int clear_zval)
  492. {
  493. drm_i810_private_t *dev_priv = dev->dev_private;
  494. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  495. int nbox = sarea_priv->nbox;
  496. struct drm_clip_rect *pbox = sarea_priv->boxes;
  497. int pitch = dev_priv->pitch;
  498. int cpp = 2;
  499. int i;
  500. RING_LOCALS;
  501. if (dev_priv->current_page == 1) {
  502. unsigned int tmp = flags;
  503. flags &= ~(I810_FRONT | I810_BACK);
  504. if (tmp & I810_FRONT)
  505. flags |= I810_BACK;
  506. if (tmp & I810_BACK)
  507. flags |= I810_FRONT;
  508. }
  509. i810_kernel_lost_context(dev);
  510. if (nbox > I810_NR_SAREA_CLIPRECTS)
  511. nbox = I810_NR_SAREA_CLIPRECTS;
  512. for (i = 0; i < nbox; i++, pbox++) {
  513. unsigned int x = pbox->x1;
  514. unsigned int y = pbox->y1;
  515. unsigned int width = (pbox->x2 - x) * cpp;
  516. unsigned int height = pbox->y2 - y;
  517. unsigned int start = y * pitch + x * cpp;
  518. if (pbox->x1 > pbox->x2 ||
  519. pbox->y1 > pbox->y2 ||
  520. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  521. continue;
  522. if (flags & I810_FRONT) {
  523. BEGIN_LP_RING(6);
  524. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  525. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  526. OUT_RING((height << 16) | width);
  527. OUT_RING(start);
  528. OUT_RING(clear_color);
  529. OUT_RING(0);
  530. ADVANCE_LP_RING();
  531. }
  532. if (flags & I810_BACK) {
  533. BEGIN_LP_RING(6);
  534. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  535. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  536. OUT_RING((height << 16) | width);
  537. OUT_RING(dev_priv->back_offset + start);
  538. OUT_RING(clear_color);
  539. OUT_RING(0);
  540. ADVANCE_LP_RING();
  541. }
  542. if (flags & I810_DEPTH) {
  543. BEGIN_LP_RING(6);
  544. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  545. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  546. OUT_RING((height << 16) | width);
  547. OUT_RING(dev_priv->depth_offset + start);
  548. OUT_RING(clear_zval);
  549. OUT_RING(0);
  550. ADVANCE_LP_RING();
  551. }
  552. }
  553. }
  554. static void i810_dma_dispatch_swap(struct drm_device *dev)
  555. {
  556. drm_i810_private_t *dev_priv = dev->dev_private;
  557. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  558. int nbox = sarea_priv->nbox;
  559. struct drm_clip_rect *pbox = sarea_priv->boxes;
  560. int pitch = dev_priv->pitch;
  561. int cpp = 2;
  562. int i;
  563. RING_LOCALS;
  564. DRM_DEBUG("swapbuffers\n");
  565. i810_kernel_lost_context(dev);
  566. if (nbox > I810_NR_SAREA_CLIPRECTS)
  567. nbox = I810_NR_SAREA_CLIPRECTS;
  568. for (i = 0; i < nbox; i++, pbox++) {
  569. unsigned int w = pbox->x2 - pbox->x1;
  570. unsigned int h = pbox->y2 - pbox->y1;
  571. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  572. unsigned int start = dst;
  573. if (pbox->x1 > pbox->x2 ||
  574. pbox->y1 > pbox->y2 ||
  575. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  576. continue;
  577. BEGIN_LP_RING(6);
  578. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  579. OUT_RING(pitch | (0xCC << 16));
  580. OUT_RING((h << 16) | (w * cpp));
  581. if (dev_priv->current_page == 0)
  582. OUT_RING(dev_priv->front_offset + start);
  583. else
  584. OUT_RING(dev_priv->back_offset + start);
  585. OUT_RING(pitch);
  586. if (dev_priv->current_page == 0)
  587. OUT_RING(dev_priv->back_offset + start);
  588. else
  589. OUT_RING(dev_priv->front_offset + start);
  590. ADVANCE_LP_RING();
  591. }
  592. }
  593. static void i810_dma_dispatch_vertex(struct drm_device *dev,
  594. struct drm_buf *buf, int discard, int used)
  595. {
  596. drm_i810_private_t *dev_priv = dev->dev_private;
  597. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  598. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  599. struct drm_clip_rect *box = sarea_priv->boxes;
  600. int nbox = sarea_priv->nbox;
  601. unsigned long address = (unsigned long)buf->bus_address;
  602. unsigned long start = address - dev->agp->base;
  603. int i = 0;
  604. RING_LOCALS;
  605. i810_kernel_lost_context(dev);
  606. if (nbox > I810_NR_SAREA_CLIPRECTS)
  607. nbox = I810_NR_SAREA_CLIPRECTS;
  608. if (used > 4 * 1024)
  609. used = 0;
  610. if (sarea_priv->dirty)
  611. i810EmitState(dev);
  612. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  613. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  614. *(u32 *) buf_priv->kernel_virtual =
  615. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  616. if (used & 4) {
  617. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  618. used += 4;
  619. }
  620. i810_unmap_buffer(buf);
  621. }
  622. if (used) {
  623. do {
  624. if (i < nbox) {
  625. BEGIN_LP_RING(4);
  626. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  627. SC_ENABLE);
  628. OUT_RING(GFX_OP_SCISSOR_INFO);
  629. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  630. OUT_RING((box[i].x2 -
  631. 1) | ((box[i].y2 - 1) << 16));
  632. ADVANCE_LP_RING();
  633. }
  634. BEGIN_LP_RING(4);
  635. OUT_RING(CMD_OP_BATCH_BUFFER);
  636. OUT_RING(start | BB1_PROTECTED);
  637. OUT_RING(start + used - 4);
  638. OUT_RING(0);
  639. ADVANCE_LP_RING();
  640. } while (++i < nbox);
  641. }
  642. if (discard) {
  643. dev_priv->counter++;
  644. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  645. I810_BUF_HARDWARE);
  646. BEGIN_LP_RING(8);
  647. OUT_RING(CMD_STORE_DWORD_IDX);
  648. OUT_RING(20);
  649. OUT_RING(dev_priv->counter);
  650. OUT_RING(CMD_STORE_DWORD_IDX);
  651. OUT_RING(buf_priv->my_use_idx);
  652. OUT_RING(I810_BUF_FREE);
  653. OUT_RING(CMD_REPORT_HEAD);
  654. OUT_RING(0);
  655. ADVANCE_LP_RING();
  656. }
  657. }
  658. static void i810_dma_dispatch_flip(struct drm_device *dev)
  659. {
  660. drm_i810_private_t *dev_priv = dev->dev_private;
  661. int pitch = dev_priv->pitch;
  662. RING_LOCALS;
  663. DRM_DEBUG("page=%d pfCurrentPage=%d\n",
  664. dev_priv->current_page,
  665. dev_priv->sarea_priv->pf_current_page);
  666. i810_kernel_lost_context(dev);
  667. BEGIN_LP_RING(2);
  668. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  669. OUT_RING(0);
  670. ADVANCE_LP_RING();
  671. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  672. /* On i815 at least ASYNC is buggy */
  673. /* pitch<<5 is from 11.2.8 p158,
  674. its the pitch / 8 then left shifted 8,
  675. so (pitch >> 3) << 8 */
  676. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  677. if (dev_priv->current_page == 0) {
  678. OUT_RING(dev_priv->back_offset);
  679. dev_priv->current_page = 1;
  680. } else {
  681. OUT_RING(dev_priv->front_offset);
  682. dev_priv->current_page = 0;
  683. }
  684. OUT_RING(0);
  685. ADVANCE_LP_RING();
  686. BEGIN_LP_RING(2);
  687. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  688. OUT_RING(0);
  689. ADVANCE_LP_RING();
  690. /* Increment the frame counter. The client-side 3D driver must
  691. * throttle the framerate by waiting for this value before
  692. * performing the swapbuffer ioctl.
  693. */
  694. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  695. }
  696. static void i810_dma_quiescent(struct drm_device *dev)
  697. {
  698. drm_i810_private_t *dev_priv = dev->dev_private;
  699. RING_LOCALS;
  700. i810_kernel_lost_context(dev);
  701. BEGIN_LP_RING(4);
  702. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  703. OUT_RING(CMD_REPORT_HEAD);
  704. OUT_RING(0);
  705. OUT_RING(0);
  706. ADVANCE_LP_RING();
  707. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  708. }
  709. static int i810_flush_queue(struct drm_device *dev)
  710. {
  711. drm_i810_private_t *dev_priv = dev->dev_private;
  712. struct drm_device_dma *dma = dev->dma;
  713. int i, ret = 0;
  714. RING_LOCALS;
  715. i810_kernel_lost_context(dev);
  716. BEGIN_LP_RING(2);
  717. OUT_RING(CMD_REPORT_HEAD);
  718. OUT_RING(0);
  719. ADVANCE_LP_RING();
  720. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  721. for (i = 0; i < dma->buf_count; i++) {
  722. struct drm_buf *buf = dma->buflist[i];
  723. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  724. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  725. I810_BUF_FREE);
  726. if (used == I810_BUF_HARDWARE)
  727. DRM_DEBUG("reclaimed from HARDWARE\n");
  728. if (used == I810_BUF_CLIENT)
  729. DRM_DEBUG("still on client\n");
  730. }
  731. return ret;
  732. }
  733. /* Must be called with the lock held */
  734. void i810_driver_reclaim_buffers(struct drm_device *dev,
  735. struct drm_file *file_priv)
  736. {
  737. struct drm_device_dma *dma = dev->dma;
  738. int i;
  739. if (!dma)
  740. return;
  741. if (!dev->dev_private)
  742. return;
  743. if (!dma->buflist)
  744. return;
  745. i810_flush_queue(dev);
  746. for (i = 0; i < dma->buf_count; i++) {
  747. struct drm_buf *buf = dma->buflist[i];
  748. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  749. if (buf->file_priv == file_priv && buf_priv) {
  750. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  751. I810_BUF_FREE);
  752. if (used == I810_BUF_CLIENT)
  753. DRM_DEBUG("reclaimed from client\n");
  754. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  755. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  756. }
  757. }
  758. }
  759. static int i810_flush_ioctl(struct drm_device *dev, void *data,
  760. struct drm_file *file_priv)
  761. {
  762. LOCK_TEST_WITH_RETURN(dev, file_priv);
  763. i810_flush_queue(dev);
  764. return 0;
  765. }
  766. static int i810_dma_vertex(struct drm_device *dev, void *data,
  767. struct drm_file *file_priv)
  768. {
  769. struct drm_device_dma *dma = dev->dma;
  770. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  771. u32 *hw_status = dev_priv->hw_status_page;
  772. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  773. dev_priv->sarea_priv;
  774. drm_i810_vertex_t *vertex = data;
  775. LOCK_TEST_WITH_RETURN(dev, file_priv);
  776. DRM_DEBUG("idx %d used %d discard %d\n",
  777. vertex->idx, vertex->used, vertex->discard);
  778. if (vertex->idx < 0 || vertex->idx > dma->buf_count)
  779. return -EINVAL;
  780. i810_dma_dispatch_vertex(dev,
  781. dma->buflist[vertex->idx],
  782. vertex->discard, vertex->used);
  783. atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
  784. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  785. sarea_priv->last_enqueue = dev_priv->counter - 1;
  786. sarea_priv->last_dispatch = (int)hw_status[5];
  787. return 0;
  788. }
  789. static int i810_clear_bufs(struct drm_device *dev, void *data,
  790. struct drm_file *file_priv)
  791. {
  792. drm_i810_clear_t *clear = data;
  793. LOCK_TEST_WITH_RETURN(dev, file_priv);
  794. /* GH: Someone's doing nasty things... */
  795. if (!dev->dev_private)
  796. return -EINVAL;
  797. i810_dma_dispatch_clear(dev, clear->flags,
  798. clear->clear_color, clear->clear_depth);
  799. return 0;
  800. }
  801. static int i810_swap_bufs(struct drm_device *dev, void *data,
  802. struct drm_file *file_priv)
  803. {
  804. DRM_DEBUG("\n");
  805. LOCK_TEST_WITH_RETURN(dev, file_priv);
  806. i810_dma_dispatch_swap(dev);
  807. return 0;
  808. }
  809. static int i810_getage(struct drm_device *dev, void *data,
  810. struct drm_file *file_priv)
  811. {
  812. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  813. u32 *hw_status = dev_priv->hw_status_page;
  814. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  815. dev_priv->sarea_priv;
  816. sarea_priv->last_dispatch = (int)hw_status[5];
  817. return 0;
  818. }
  819. static int i810_getbuf(struct drm_device *dev, void *data,
  820. struct drm_file *file_priv)
  821. {
  822. int retcode = 0;
  823. drm_i810_dma_t *d = data;
  824. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  825. u32 *hw_status = dev_priv->hw_status_page;
  826. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  827. dev_priv->sarea_priv;
  828. LOCK_TEST_WITH_RETURN(dev, file_priv);
  829. d->granted = 0;
  830. retcode = i810_dma_get_buffer(dev, d, file_priv);
  831. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  832. task_pid_nr(current), retcode, d->granted);
  833. sarea_priv->last_dispatch = (int)hw_status[5];
  834. return retcode;
  835. }
  836. static int i810_copybuf(struct drm_device *dev, void *data,
  837. struct drm_file *file_priv)
  838. {
  839. /* Never copy - 2.4.x doesn't need it */
  840. return 0;
  841. }
  842. static int i810_docopy(struct drm_device *dev, void *data,
  843. struct drm_file *file_priv)
  844. {
  845. /* Never copy - 2.4.x doesn't need it */
  846. return 0;
  847. }
  848. static void i810_dma_dispatch_mc(struct drm_device *dev, struct drm_buf *buf, int used,
  849. unsigned int last_render)
  850. {
  851. drm_i810_private_t *dev_priv = dev->dev_private;
  852. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  853. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  854. unsigned long address = (unsigned long)buf->bus_address;
  855. unsigned long start = address - dev->agp->base;
  856. int u;
  857. RING_LOCALS;
  858. i810_kernel_lost_context(dev);
  859. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  860. if (u != I810_BUF_CLIENT)
  861. DRM_DEBUG("MC found buffer that isn't mine!\n");
  862. if (used > 4 * 1024)
  863. used = 0;
  864. sarea_priv->dirty = 0x7f;
  865. DRM_DEBUG("addr 0x%lx, used 0x%x\n", address, used);
  866. dev_priv->counter++;
  867. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  868. DRM_DEBUG("start : %lx\n", start);
  869. DRM_DEBUG("used : %d\n", used);
  870. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  871. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  872. if (used & 4) {
  873. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  874. used += 4;
  875. }
  876. i810_unmap_buffer(buf);
  877. }
  878. BEGIN_LP_RING(4);
  879. OUT_RING(CMD_OP_BATCH_BUFFER);
  880. OUT_RING(start | BB1_PROTECTED);
  881. OUT_RING(start + used - 4);
  882. OUT_RING(0);
  883. ADVANCE_LP_RING();
  884. BEGIN_LP_RING(8);
  885. OUT_RING(CMD_STORE_DWORD_IDX);
  886. OUT_RING(buf_priv->my_use_idx);
  887. OUT_RING(I810_BUF_FREE);
  888. OUT_RING(0);
  889. OUT_RING(CMD_STORE_DWORD_IDX);
  890. OUT_RING(16);
  891. OUT_RING(last_render);
  892. OUT_RING(0);
  893. ADVANCE_LP_RING();
  894. }
  895. static int i810_dma_mc(struct drm_device *dev, void *data,
  896. struct drm_file *file_priv)
  897. {
  898. struct drm_device_dma *dma = dev->dma;
  899. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  900. u32 *hw_status = dev_priv->hw_status_page;
  901. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  902. dev_priv->sarea_priv;
  903. drm_i810_mc_t *mc = data;
  904. LOCK_TEST_WITH_RETURN(dev, file_priv);
  905. if (mc->idx >= dma->buf_count || mc->idx < 0)
  906. return -EINVAL;
  907. i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
  908. mc->last_render);
  909. atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
  910. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  911. sarea_priv->last_enqueue = dev_priv->counter - 1;
  912. sarea_priv->last_dispatch = (int)hw_status[5];
  913. return 0;
  914. }
  915. static int i810_rstatus(struct drm_device *dev, void *data,
  916. struct drm_file *file_priv)
  917. {
  918. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  919. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  920. }
  921. static int i810_ov0_info(struct drm_device *dev, void *data,
  922. struct drm_file *file_priv)
  923. {
  924. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  925. drm_i810_overlay_t *ov = data;
  926. ov->offset = dev_priv->overlay_offset;
  927. ov->physical = dev_priv->overlay_physical;
  928. return 0;
  929. }
  930. static int i810_fstatus(struct drm_device *dev, void *data,
  931. struct drm_file *file_priv)
  932. {
  933. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  934. LOCK_TEST_WITH_RETURN(dev, file_priv);
  935. return I810_READ(0x30008);
  936. }
  937. static int i810_ov0_flip(struct drm_device *dev, void *data,
  938. struct drm_file *file_priv)
  939. {
  940. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  941. LOCK_TEST_WITH_RETURN(dev, file_priv);
  942. /* Tell the overlay to update */
  943. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  944. return 0;
  945. }
  946. /* Not sure why this isn't set all the time:
  947. */
  948. static void i810_do_init_pageflip(struct drm_device *dev)
  949. {
  950. drm_i810_private_t *dev_priv = dev->dev_private;
  951. DRM_DEBUG("\n");
  952. dev_priv->page_flipping = 1;
  953. dev_priv->current_page = 0;
  954. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  955. }
  956. static int i810_do_cleanup_pageflip(struct drm_device *dev)
  957. {
  958. drm_i810_private_t *dev_priv = dev->dev_private;
  959. DRM_DEBUG("\n");
  960. if (dev_priv->current_page != 0)
  961. i810_dma_dispatch_flip(dev);
  962. dev_priv->page_flipping = 0;
  963. return 0;
  964. }
  965. static int i810_flip_bufs(struct drm_device *dev, void *data,
  966. struct drm_file *file_priv)
  967. {
  968. drm_i810_private_t *dev_priv = dev->dev_private;
  969. DRM_DEBUG("\n");
  970. LOCK_TEST_WITH_RETURN(dev, file_priv);
  971. if (!dev_priv->page_flipping)
  972. i810_do_init_pageflip(dev);
  973. i810_dma_dispatch_flip(dev);
  974. return 0;
  975. }
  976. int i810_driver_load(struct drm_device *dev, unsigned long flags)
  977. {
  978. /* i810 has 4 more counters */
  979. dev->counters += 4;
  980. dev->types[6] = _DRM_STAT_IRQ;
  981. dev->types[7] = _DRM_STAT_PRIMARY;
  982. dev->types[8] = _DRM_STAT_SECONDARY;
  983. dev->types[9] = _DRM_STAT_DMA;
  984. pci_set_master(dev->pdev);
  985. return 0;
  986. }
  987. void i810_driver_lastclose(struct drm_device *dev)
  988. {
  989. i810_dma_cleanup(dev);
  990. }
  991. void i810_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
  992. {
  993. if (dev->dev_private) {
  994. drm_i810_private_t *dev_priv = dev->dev_private;
  995. if (dev_priv->page_flipping)
  996. i810_do_cleanup_pageflip(dev);
  997. }
  998. if (file_priv->master && file_priv->master->lock.hw_lock) {
  999. drm_idlelock_take(&file_priv->master->lock);
  1000. i810_driver_reclaim_buffers(dev, file_priv);
  1001. drm_idlelock_release(&file_priv->master->lock);
  1002. } else {
  1003. /* master disappeared, clean up stuff anyway and hope nothing
  1004. * goes wrong */
  1005. i810_driver_reclaim_buffers(dev, file_priv);
  1006. }
  1007. }
  1008. int i810_driver_dma_quiescent(struct drm_device *dev)
  1009. {
  1010. i810_dma_quiescent(dev);
  1011. return 0;
  1012. }
  1013. const struct drm_ioctl_desc i810_ioctls[] = {
  1014. DRM_IOCTL_DEF_DRV(I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1015. DRM_IOCTL_DEF_DRV(I810_VERTEX, i810_dma_vertex, DRM_AUTH|DRM_UNLOCKED),
  1016. DRM_IOCTL_DEF_DRV(I810_CLEAR, i810_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
  1017. DRM_IOCTL_DEF_DRV(I810_FLUSH, i810_flush_ioctl, DRM_AUTH|DRM_UNLOCKED),
  1018. DRM_IOCTL_DEF_DRV(I810_GETAGE, i810_getage, DRM_AUTH|DRM_UNLOCKED),
  1019. DRM_IOCTL_DEF_DRV(I810_GETBUF, i810_getbuf, DRM_AUTH|DRM_UNLOCKED),
  1020. DRM_IOCTL_DEF_DRV(I810_SWAP, i810_swap_bufs, DRM_AUTH|DRM_UNLOCKED),
  1021. DRM_IOCTL_DEF_DRV(I810_COPY, i810_copybuf, DRM_AUTH|DRM_UNLOCKED),
  1022. DRM_IOCTL_DEF_DRV(I810_DOCOPY, i810_docopy, DRM_AUTH|DRM_UNLOCKED),
  1023. DRM_IOCTL_DEF_DRV(I810_OV0INFO, i810_ov0_info, DRM_AUTH|DRM_UNLOCKED),
  1024. DRM_IOCTL_DEF_DRV(I810_FSTATUS, i810_fstatus, DRM_AUTH|DRM_UNLOCKED),
  1025. DRM_IOCTL_DEF_DRV(I810_OV0FLIP, i810_ov0_flip, DRM_AUTH|DRM_UNLOCKED),
  1026. DRM_IOCTL_DEF_DRV(I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1027. DRM_IOCTL_DEF_DRV(I810_RSTATUS, i810_rstatus, DRM_AUTH|DRM_UNLOCKED),
  1028. DRM_IOCTL_DEF_DRV(I810_FLIP, i810_flip_bufs, DRM_AUTH|DRM_UNLOCKED),
  1029. };
  1030. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1031. /**
  1032. * Determine if the device really is AGP or not.
  1033. *
  1034. * All Intel graphics chipsets are treated as AGP, even if they are really
  1035. * PCI-e.
  1036. *
  1037. * \param dev The device to be tested.
  1038. *
  1039. * \returns
  1040. * A value of 1 is always retured to indictate every i810 is AGP.
  1041. */
  1042. int i810_driver_device_is_agp(struct drm_device *dev)
  1043. {
  1044. return 1;
  1045. }