gpio-tegra.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570
  1. /*
  2. * arch/arm/mach-tegra/gpio.c
  3. *
  4. * Copyright (c) 2010 Google, Inc
  5. *
  6. * Author:
  7. * Erik Gilling <konkers@google.com>
  8. *
  9. * This software is licensed under the terms of the GNU General Public
  10. * License version 2, as published by the Free Software Foundation, and
  11. * may be copied, distributed, and modified under those terms.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. */
  19. #include <linux/err.h>
  20. #include <linux/init.h>
  21. #include <linux/irq.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/io.h>
  24. #include <linux/gpio.h>
  25. #include <linux/of_device.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/module.h>
  28. #include <linux/irqdomain.h>
  29. #include <linux/irqchip/chained_irq.h>
  30. #include <linux/pinctrl/consumer.h>
  31. #include <linux/pm.h>
  32. #define GPIO_BANK(x) ((x) >> 5)
  33. #define GPIO_PORT(x) (((x) >> 3) & 0x3)
  34. #define GPIO_BIT(x) ((x) & 0x7)
  35. #define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
  36. GPIO_PORT(x) * 4)
  37. #define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
  38. #define GPIO_OE(x) (GPIO_REG(x) + 0x10)
  39. #define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
  40. #define GPIO_IN(x) (GPIO_REG(x) + 0x30)
  41. #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
  42. #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
  43. #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
  44. #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
  45. #define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
  46. #define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
  47. #define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
  48. #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
  49. #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
  50. #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
  51. #define GPIO_INT_LVL_MASK 0x010101
  52. #define GPIO_INT_LVL_EDGE_RISING 0x000101
  53. #define GPIO_INT_LVL_EDGE_FALLING 0x000100
  54. #define GPIO_INT_LVL_EDGE_BOTH 0x010100
  55. #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
  56. #define GPIO_INT_LVL_LEVEL_LOW 0x000000
  57. struct tegra_gpio_bank {
  58. int bank;
  59. int irq;
  60. spinlock_t lvl_lock[4];
  61. #ifdef CONFIG_PM_SLEEP
  62. u32 cnf[4];
  63. u32 out[4];
  64. u32 oe[4];
  65. u32 int_enb[4];
  66. u32 int_lvl[4];
  67. u32 wake_enb[4];
  68. #endif
  69. };
  70. static struct irq_domain *irq_domain;
  71. static void __iomem *regs;
  72. static u32 tegra_gpio_bank_count;
  73. static u32 tegra_gpio_bank_stride;
  74. static u32 tegra_gpio_upper_offset;
  75. static struct tegra_gpio_bank *tegra_gpio_banks;
  76. static inline void tegra_gpio_writel(u32 val, u32 reg)
  77. {
  78. __raw_writel(val, regs + reg);
  79. }
  80. static inline u32 tegra_gpio_readl(u32 reg)
  81. {
  82. return __raw_readl(regs + reg);
  83. }
  84. static int tegra_gpio_compose(int bank, int port, int bit)
  85. {
  86. return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
  87. }
  88. static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
  89. {
  90. u32 val;
  91. val = 0x100 << GPIO_BIT(gpio);
  92. if (value)
  93. val |= 1 << GPIO_BIT(gpio);
  94. tegra_gpio_writel(val, reg);
  95. }
  96. static void tegra_gpio_enable(int gpio)
  97. {
  98. tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
  99. }
  100. static void tegra_gpio_disable(int gpio)
  101. {
  102. tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
  103. }
  104. static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
  105. {
  106. return pinctrl_request_gpio(offset);
  107. }
  108. static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
  109. {
  110. pinctrl_free_gpio(offset);
  111. tegra_gpio_disable(offset);
  112. }
  113. static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  114. {
  115. tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
  116. }
  117. static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
  118. {
  119. /* If gpio is in output mode then read from the out value */
  120. if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
  121. return (tegra_gpio_readl(GPIO_OUT(offset)) >>
  122. GPIO_BIT(offset)) & 0x1;
  123. return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
  124. }
  125. static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  126. {
  127. tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
  128. tegra_gpio_enable(offset);
  129. return 0;
  130. }
  131. static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
  132. int value)
  133. {
  134. tegra_gpio_set(chip, offset, value);
  135. tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
  136. tegra_gpio_enable(offset);
  137. return 0;
  138. }
  139. static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  140. {
  141. return irq_find_mapping(irq_domain, offset);
  142. }
  143. static struct gpio_chip tegra_gpio_chip = {
  144. .label = "tegra-gpio",
  145. .request = tegra_gpio_request,
  146. .free = tegra_gpio_free,
  147. .direction_input = tegra_gpio_direction_input,
  148. .get = tegra_gpio_get,
  149. .direction_output = tegra_gpio_direction_output,
  150. .set = tegra_gpio_set,
  151. .to_irq = tegra_gpio_to_irq,
  152. .base = 0,
  153. };
  154. static void tegra_gpio_irq_ack(struct irq_data *d)
  155. {
  156. int gpio = d->hwirq;
  157. tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
  158. }
  159. static void tegra_gpio_irq_mask(struct irq_data *d)
  160. {
  161. int gpio = d->hwirq;
  162. tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
  163. }
  164. static void tegra_gpio_irq_unmask(struct irq_data *d)
  165. {
  166. int gpio = d->hwirq;
  167. tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
  168. }
  169. static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  170. {
  171. int gpio = d->hwirq;
  172. struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
  173. int port = GPIO_PORT(gpio);
  174. int lvl_type;
  175. int val;
  176. unsigned long flags;
  177. switch (type & IRQ_TYPE_SENSE_MASK) {
  178. case IRQ_TYPE_EDGE_RISING:
  179. lvl_type = GPIO_INT_LVL_EDGE_RISING;
  180. break;
  181. case IRQ_TYPE_EDGE_FALLING:
  182. lvl_type = GPIO_INT_LVL_EDGE_FALLING;
  183. break;
  184. case IRQ_TYPE_EDGE_BOTH:
  185. lvl_type = GPIO_INT_LVL_EDGE_BOTH;
  186. break;
  187. case IRQ_TYPE_LEVEL_HIGH:
  188. lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
  189. break;
  190. case IRQ_TYPE_LEVEL_LOW:
  191. lvl_type = GPIO_INT_LVL_LEVEL_LOW;
  192. break;
  193. default:
  194. return -EINVAL;
  195. }
  196. spin_lock_irqsave(&bank->lvl_lock[port], flags);
  197. val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
  198. val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
  199. val |= lvl_type << GPIO_BIT(gpio);
  200. tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
  201. spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
  202. tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
  203. tegra_gpio_enable(gpio);
  204. if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
  205. __irq_set_handler_locked(d->irq, handle_level_irq);
  206. else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
  207. __irq_set_handler_locked(d->irq, handle_edge_irq);
  208. return 0;
  209. }
  210. static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
  211. {
  212. struct tegra_gpio_bank *bank;
  213. int port;
  214. int pin;
  215. int unmasked = 0;
  216. struct irq_chip *chip = irq_desc_get_chip(desc);
  217. chained_irq_enter(chip, desc);
  218. bank = irq_get_handler_data(irq);
  219. for (port = 0; port < 4; port++) {
  220. int gpio = tegra_gpio_compose(bank->bank, port, 0);
  221. unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
  222. tegra_gpio_readl(GPIO_INT_ENB(gpio));
  223. u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
  224. for_each_set_bit(pin, &sta, 8) {
  225. tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
  226. /* if gpio is edge triggered, clear condition
  227. * before executing the hander so that we don't
  228. * miss edges
  229. */
  230. if (lvl & (0x100 << pin)) {
  231. unmasked = 1;
  232. chained_irq_exit(chip, desc);
  233. }
  234. generic_handle_irq(gpio_to_irq(gpio + pin));
  235. }
  236. }
  237. if (!unmasked)
  238. chained_irq_exit(chip, desc);
  239. }
  240. #ifdef CONFIG_PM_SLEEP
  241. static int tegra_gpio_resume(struct device *dev)
  242. {
  243. unsigned long flags;
  244. int b;
  245. int p;
  246. local_irq_save(flags);
  247. for (b = 0; b < tegra_gpio_bank_count; b++) {
  248. struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
  249. for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
  250. unsigned int gpio = (b<<5) | (p<<3);
  251. tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
  252. tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
  253. tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
  254. tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
  255. tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
  256. }
  257. }
  258. local_irq_restore(flags);
  259. return 0;
  260. }
  261. static int tegra_gpio_suspend(struct device *dev)
  262. {
  263. unsigned long flags;
  264. int b;
  265. int p;
  266. local_irq_save(flags);
  267. for (b = 0; b < tegra_gpio_bank_count; b++) {
  268. struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
  269. for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
  270. unsigned int gpio = (b<<5) | (p<<3);
  271. bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
  272. bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
  273. bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
  274. bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
  275. bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
  276. /* Enable gpio irq for wake up source */
  277. tegra_gpio_writel(bank->wake_enb[p],
  278. GPIO_INT_ENB(gpio));
  279. }
  280. }
  281. local_irq_restore(flags);
  282. return 0;
  283. }
  284. static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
  285. {
  286. struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
  287. int gpio = d->hwirq;
  288. u32 port, bit, mask;
  289. port = GPIO_PORT(gpio);
  290. bit = GPIO_BIT(gpio);
  291. mask = BIT(bit);
  292. if (enable)
  293. bank->wake_enb[port] |= mask;
  294. else
  295. bank->wake_enb[port] &= ~mask;
  296. return irq_set_irq_wake(bank->irq, enable);
  297. }
  298. #endif
  299. static struct irq_chip tegra_gpio_irq_chip = {
  300. .name = "GPIO",
  301. .irq_ack = tegra_gpio_irq_ack,
  302. .irq_mask = tegra_gpio_irq_mask,
  303. .irq_unmask = tegra_gpio_irq_unmask,
  304. .irq_set_type = tegra_gpio_irq_set_type,
  305. #ifdef CONFIG_PM_SLEEP
  306. .irq_set_wake = tegra_gpio_irq_set_wake,
  307. #endif
  308. };
  309. static const struct dev_pm_ops tegra_gpio_pm_ops = {
  310. SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
  311. };
  312. struct tegra_gpio_soc_config {
  313. u32 bank_stride;
  314. u32 upper_offset;
  315. };
  316. static struct tegra_gpio_soc_config tegra20_gpio_config = {
  317. .bank_stride = 0x80,
  318. .upper_offset = 0x800,
  319. };
  320. static struct tegra_gpio_soc_config tegra30_gpio_config = {
  321. .bank_stride = 0x100,
  322. .upper_offset = 0x80,
  323. };
  324. static struct of_device_id tegra_gpio_of_match[] = {
  325. { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
  326. { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
  327. { },
  328. };
  329. /* This lock class tells lockdep that GPIO irqs are in a different
  330. * category than their parents, so it won't report false recursion.
  331. */
  332. static struct lock_class_key gpio_lock_class;
  333. static int tegra_gpio_probe(struct platform_device *pdev)
  334. {
  335. const struct of_device_id *match;
  336. struct tegra_gpio_soc_config *config;
  337. struct resource *res;
  338. struct tegra_gpio_bank *bank;
  339. int gpio;
  340. int i;
  341. int j;
  342. match = of_match_device(tegra_gpio_of_match, &pdev->dev);
  343. if (!match) {
  344. dev_err(&pdev->dev, "Error: No device match found\n");
  345. return -ENODEV;
  346. }
  347. config = (struct tegra_gpio_soc_config *)match->data;
  348. tegra_gpio_bank_stride = config->bank_stride;
  349. tegra_gpio_upper_offset = config->upper_offset;
  350. for (;;) {
  351. res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
  352. if (!res)
  353. break;
  354. tegra_gpio_bank_count++;
  355. }
  356. if (!tegra_gpio_bank_count) {
  357. dev_err(&pdev->dev, "Missing IRQ resource\n");
  358. return -ENODEV;
  359. }
  360. tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
  361. tegra_gpio_banks = devm_kzalloc(&pdev->dev,
  362. tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
  363. GFP_KERNEL);
  364. if (!tegra_gpio_banks) {
  365. dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
  366. return -ENODEV;
  367. }
  368. irq_domain = irq_domain_add_linear(pdev->dev.of_node,
  369. tegra_gpio_chip.ngpio,
  370. &irq_domain_simple_ops, NULL);
  371. if (!irq_domain)
  372. return -ENODEV;
  373. for (i = 0; i < tegra_gpio_bank_count; i++) {
  374. res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
  375. if (!res) {
  376. dev_err(&pdev->dev, "Missing IRQ resource\n");
  377. return -ENODEV;
  378. }
  379. bank = &tegra_gpio_banks[i];
  380. bank->bank = i;
  381. bank->irq = res->start;
  382. }
  383. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  384. regs = devm_ioremap_resource(&pdev->dev, res);
  385. if (IS_ERR(regs))
  386. return PTR_ERR(regs);
  387. for (i = 0; i < tegra_gpio_bank_count; i++) {
  388. for (j = 0; j < 4; j++) {
  389. int gpio = tegra_gpio_compose(i, j, 0);
  390. tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
  391. }
  392. }
  393. tegra_gpio_chip.of_node = pdev->dev.of_node;
  394. gpiochip_add(&tegra_gpio_chip);
  395. for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
  396. int irq = irq_create_mapping(irq_domain, gpio);
  397. /* No validity check; all Tegra GPIOs are valid IRQs */
  398. bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
  399. irq_set_lockdep_class(irq, &gpio_lock_class);
  400. irq_set_chip_data(irq, bank);
  401. irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
  402. handle_simple_irq);
  403. set_irq_flags(irq, IRQF_VALID);
  404. }
  405. for (i = 0; i < tegra_gpio_bank_count; i++) {
  406. bank = &tegra_gpio_banks[i];
  407. irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
  408. irq_set_handler_data(bank->irq, bank);
  409. for (j = 0; j < 4; j++)
  410. spin_lock_init(&bank->lvl_lock[j]);
  411. }
  412. return 0;
  413. }
  414. static struct platform_driver tegra_gpio_driver = {
  415. .driver = {
  416. .name = "tegra-gpio",
  417. .owner = THIS_MODULE,
  418. .pm = &tegra_gpio_pm_ops,
  419. .of_match_table = tegra_gpio_of_match,
  420. },
  421. .probe = tegra_gpio_probe,
  422. };
  423. static int __init tegra_gpio_init(void)
  424. {
  425. return platform_driver_register(&tegra_gpio_driver);
  426. }
  427. postcore_initcall(tegra_gpio_init);
  428. #ifdef CONFIG_DEBUG_FS
  429. #include <linux/debugfs.h>
  430. #include <linux/seq_file.h>
  431. static int dbg_gpio_show(struct seq_file *s, void *unused)
  432. {
  433. int i;
  434. int j;
  435. for (i = 0; i < tegra_gpio_bank_count; i++) {
  436. for (j = 0; j < 4; j++) {
  437. int gpio = tegra_gpio_compose(i, j, 0);
  438. seq_printf(s,
  439. "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
  440. i, j,
  441. tegra_gpio_readl(GPIO_CNF(gpio)),
  442. tegra_gpio_readl(GPIO_OE(gpio)),
  443. tegra_gpio_readl(GPIO_OUT(gpio)),
  444. tegra_gpio_readl(GPIO_IN(gpio)),
  445. tegra_gpio_readl(GPIO_INT_STA(gpio)),
  446. tegra_gpio_readl(GPIO_INT_ENB(gpio)),
  447. tegra_gpio_readl(GPIO_INT_LVL(gpio)));
  448. }
  449. }
  450. return 0;
  451. }
  452. static int dbg_gpio_open(struct inode *inode, struct file *file)
  453. {
  454. return single_open(file, dbg_gpio_show, &inode->i_private);
  455. }
  456. static const struct file_operations debug_fops = {
  457. .open = dbg_gpio_open,
  458. .read = seq_read,
  459. .llseek = seq_lseek,
  460. .release = single_release,
  461. };
  462. static int __init tegra_gpio_debuginit(void)
  463. {
  464. (void) debugfs_create_file("tegra_gpio", S_IRUGO,
  465. NULL, NULL, &debug_fops);
  466. return 0;
  467. }
  468. late_initcall(tegra_gpio_debuginit);
  469. #endif