gpio-rcar.c 12 KB

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  1. /*
  2. * Renesas R-Car GPIO Support
  3. *
  4. * Copyright (C) 2013 Magnus Damm
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/err.h>
  16. #include <linux/gpio.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/io.h>
  20. #include <linux/ioport.h>
  21. #include <linux/irq.h>
  22. #include <linux/irqdomain.h>
  23. #include <linux/module.h>
  24. #include <linux/pinctrl/consumer.h>
  25. #include <linux/platform_data/gpio-rcar.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/spinlock.h>
  28. #include <linux/slab.h>
  29. struct gpio_rcar_priv {
  30. void __iomem *base;
  31. spinlock_t lock;
  32. struct gpio_rcar_config config;
  33. struct platform_device *pdev;
  34. struct gpio_chip gpio_chip;
  35. struct irq_chip irq_chip;
  36. struct irq_domain *irq_domain;
  37. };
  38. #define IOINTSEL 0x00
  39. #define INOUTSEL 0x04
  40. #define OUTDT 0x08
  41. #define INDT 0x0c
  42. #define INTDT 0x10
  43. #define INTCLR 0x14
  44. #define INTMSK 0x18
  45. #define MSKCLR 0x1c
  46. #define POSNEG 0x20
  47. #define EDGLEVEL 0x24
  48. #define FILONOFF 0x28
  49. #define BOTHEDGE 0x4c
  50. #define RCAR_MAX_GPIO_PER_BANK 32
  51. static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
  52. {
  53. return ioread32(p->base + offs);
  54. }
  55. static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
  56. u32 value)
  57. {
  58. iowrite32(value, p->base + offs);
  59. }
  60. static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
  61. int bit, bool value)
  62. {
  63. u32 tmp = gpio_rcar_read(p, offs);
  64. if (value)
  65. tmp |= BIT(bit);
  66. else
  67. tmp &= ~BIT(bit);
  68. gpio_rcar_write(p, offs, tmp);
  69. }
  70. static void gpio_rcar_irq_disable(struct irq_data *d)
  71. {
  72. struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
  73. gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
  74. }
  75. static void gpio_rcar_irq_enable(struct irq_data *d)
  76. {
  77. struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
  78. gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
  79. }
  80. static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
  81. unsigned int hwirq,
  82. bool active_high_rising_edge,
  83. bool level_trigger,
  84. bool both)
  85. {
  86. unsigned long flags;
  87. /* follow steps in the GPIO documentation for
  88. * "Setting Edge-Sensitive Interrupt Input Mode" and
  89. * "Setting Level-Sensitive Interrupt Input Mode"
  90. */
  91. spin_lock_irqsave(&p->lock, flags);
  92. /* Configure postive or negative logic in POSNEG */
  93. gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
  94. /* Configure edge or level trigger in EDGLEVEL */
  95. gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
  96. /* Select one edge or both edges in BOTHEDGE */
  97. if (p->config.has_both_edge_trigger)
  98. gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
  99. /* Select "Interrupt Input Mode" in IOINTSEL */
  100. gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
  101. /* Write INTCLR in case of edge trigger */
  102. if (!level_trigger)
  103. gpio_rcar_write(p, INTCLR, BIT(hwirq));
  104. spin_unlock_irqrestore(&p->lock, flags);
  105. }
  106. static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
  107. {
  108. struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
  109. unsigned int hwirq = irqd_to_hwirq(d);
  110. dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
  111. switch (type & IRQ_TYPE_SENSE_MASK) {
  112. case IRQ_TYPE_LEVEL_HIGH:
  113. gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
  114. false);
  115. break;
  116. case IRQ_TYPE_LEVEL_LOW:
  117. gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
  118. false);
  119. break;
  120. case IRQ_TYPE_EDGE_RISING:
  121. gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
  122. false);
  123. break;
  124. case IRQ_TYPE_EDGE_FALLING:
  125. gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
  126. false);
  127. break;
  128. case IRQ_TYPE_EDGE_BOTH:
  129. if (!p->config.has_both_edge_trigger)
  130. return -EINVAL;
  131. gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
  132. true);
  133. break;
  134. default:
  135. return -EINVAL;
  136. }
  137. return 0;
  138. }
  139. static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
  140. {
  141. struct gpio_rcar_priv *p = dev_id;
  142. u32 pending;
  143. unsigned int offset, irqs_handled = 0;
  144. while ((pending = gpio_rcar_read(p, INTDT))) {
  145. offset = __ffs(pending);
  146. gpio_rcar_write(p, INTCLR, BIT(offset));
  147. generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
  148. irqs_handled++;
  149. }
  150. return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
  151. }
  152. static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
  153. {
  154. return container_of(chip, struct gpio_rcar_priv, gpio_chip);
  155. }
  156. static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
  157. unsigned int gpio,
  158. bool output)
  159. {
  160. struct gpio_rcar_priv *p = gpio_to_priv(chip);
  161. unsigned long flags;
  162. /* follow steps in the GPIO documentation for
  163. * "Setting General Output Mode" and
  164. * "Setting General Input Mode"
  165. */
  166. spin_lock_irqsave(&p->lock, flags);
  167. /* Configure postive logic in POSNEG */
  168. gpio_rcar_modify_bit(p, POSNEG, gpio, false);
  169. /* Select "General Input/Output Mode" in IOINTSEL */
  170. gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
  171. /* Select Input Mode or Output Mode in INOUTSEL */
  172. gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
  173. spin_unlock_irqrestore(&p->lock, flags);
  174. }
  175. static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
  176. {
  177. return pinctrl_request_gpio(chip->base + offset);
  178. }
  179. static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
  180. {
  181. pinctrl_free_gpio(chip->base + offset);
  182. /* Set the GPIO as an input to ensure that the next GPIO request won't
  183. * drive the GPIO pin as an output.
  184. */
  185. gpio_rcar_config_general_input_output_mode(chip, offset, false);
  186. }
  187. static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
  188. {
  189. gpio_rcar_config_general_input_output_mode(chip, offset, false);
  190. return 0;
  191. }
  192. static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
  193. {
  194. u32 bit = BIT(offset);
  195. /* testing on r8a7790 shows that INDT does not show correct pin state
  196. * when configured as output, so use OUTDT in case of output pins */
  197. if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
  198. return (int)(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
  199. else
  200. return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
  201. }
  202. static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
  203. {
  204. struct gpio_rcar_priv *p = gpio_to_priv(chip);
  205. unsigned long flags;
  206. spin_lock_irqsave(&p->lock, flags);
  207. gpio_rcar_modify_bit(p, OUTDT, offset, value);
  208. spin_unlock_irqrestore(&p->lock, flags);
  209. }
  210. static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
  211. int value)
  212. {
  213. /* write GPIO value to output before selecting output mode of pin */
  214. gpio_rcar_set(chip, offset, value);
  215. gpio_rcar_config_general_input_output_mode(chip, offset, true);
  216. return 0;
  217. }
  218. static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
  219. {
  220. return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
  221. }
  222. static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
  223. irq_hw_number_t hw)
  224. {
  225. struct gpio_rcar_priv *p = h->host_data;
  226. dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);
  227. irq_set_chip_data(virq, h->host_data);
  228. irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
  229. set_irq_flags(virq, IRQF_VALID); /* kill me now */
  230. return 0;
  231. }
  232. static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
  233. .map = gpio_rcar_irq_domain_map,
  234. };
  235. static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
  236. {
  237. struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
  238. struct device_node *np = p->pdev->dev.of_node;
  239. struct of_phandle_args args;
  240. int ret;
  241. if (pdata) {
  242. p->config = *pdata;
  243. } else if (IS_ENABLED(CONFIG_OF) && np) {
  244. ret = of_parse_phandle_with_args(np, "gpio-ranges",
  245. "#gpio-range-cells", 0, &args);
  246. p->config.number_of_pins = ret == 0 && args.args_count == 3
  247. ? args.args[2]
  248. : RCAR_MAX_GPIO_PER_BANK;
  249. p->config.gpio_base = -1;
  250. }
  251. if (p->config.number_of_pins == 0 ||
  252. p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
  253. dev_warn(&p->pdev->dev,
  254. "Invalid number of gpio lines %u, using %u\n",
  255. p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
  256. p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
  257. }
  258. }
  259. static int gpio_rcar_probe(struct platform_device *pdev)
  260. {
  261. struct gpio_rcar_priv *p;
  262. struct resource *io, *irq;
  263. struct gpio_chip *gpio_chip;
  264. struct irq_chip *irq_chip;
  265. const char *name = dev_name(&pdev->dev);
  266. int ret;
  267. p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
  268. if (!p) {
  269. dev_err(&pdev->dev, "failed to allocate driver data\n");
  270. ret = -ENOMEM;
  271. goto err0;
  272. }
  273. p->pdev = pdev;
  274. spin_lock_init(&p->lock);
  275. /* Get device configuration from DT node or platform data. */
  276. gpio_rcar_parse_pdata(p);
  277. platform_set_drvdata(pdev, p);
  278. io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  279. irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  280. if (!io || !irq) {
  281. dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
  282. ret = -EINVAL;
  283. goto err0;
  284. }
  285. p->base = devm_ioremap_nocache(&pdev->dev, io->start,
  286. resource_size(io));
  287. if (!p->base) {
  288. dev_err(&pdev->dev, "failed to remap I/O memory\n");
  289. ret = -ENXIO;
  290. goto err0;
  291. }
  292. gpio_chip = &p->gpio_chip;
  293. gpio_chip->request = gpio_rcar_request;
  294. gpio_chip->free = gpio_rcar_free;
  295. gpio_chip->direction_input = gpio_rcar_direction_input;
  296. gpio_chip->get = gpio_rcar_get;
  297. gpio_chip->direction_output = gpio_rcar_direction_output;
  298. gpio_chip->set = gpio_rcar_set;
  299. gpio_chip->to_irq = gpio_rcar_to_irq;
  300. gpio_chip->label = name;
  301. gpio_chip->dev = &pdev->dev;
  302. gpio_chip->owner = THIS_MODULE;
  303. gpio_chip->base = p->config.gpio_base;
  304. gpio_chip->ngpio = p->config.number_of_pins;
  305. irq_chip = &p->irq_chip;
  306. irq_chip->name = name;
  307. irq_chip->irq_mask = gpio_rcar_irq_disable;
  308. irq_chip->irq_unmask = gpio_rcar_irq_enable;
  309. irq_chip->irq_enable = gpio_rcar_irq_enable;
  310. irq_chip->irq_disable = gpio_rcar_irq_disable;
  311. irq_chip->irq_set_type = gpio_rcar_irq_set_type;
  312. irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;
  313. p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
  314. p->config.number_of_pins,
  315. p->config.irq_base,
  316. &gpio_rcar_irq_domain_ops, p);
  317. if (!p->irq_domain) {
  318. ret = -ENXIO;
  319. dev_err(&pdev->dev, "cannot initialize irq domain\n");
  320. goto err1;
  321. }
  322. if (devm_request_irq(&pdev->dev, irq->start,
  323. gpio_rcar_irq_handler, IRQF_SHARED, name, p)) {
  324. dev_err(&pdev->dev, "failed to request IRQ\n");
  325. ret = -ENOENT;
  326. goto err1;
  327. }
  328. ret = gpiochip_add(gpio_chip);
  329. if (ret) {
  330. dev_err(&pdev->dev, "failed to add GPIO controller\n");
  331. goto err1;
  332. }
  333. dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
  334. /* warn in case of mismatch if irq base is specified */
  335. if (p->config.irq_base) {
  336. ret = irq_find_mapping(p->irq_domain, 0);
  337. if (p->config.irq_base != ret)
  338. dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
  339. p->config.irq_base, ret);
  340. }
  341. if (p->config.pctl_name) {
  342. ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
  343. gpio_chip->base, gpio_chip->ngpio);
  344. if (ret < 0)
  345. dev_warn(&pdev->dev, "failed to add pin range\n");
  346. }
  347. return 0;
  348. err1:
  349. irq_domain_remove(p->irq_domain);
  350. err0:
  351. return ret;
  352. }
  353. static int gpio_rcar_remove(struct platform_device *pdev)
  354. {
  355. struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
  356. int ret;
  357. ret = gpiochip_remove(&p->gpio_chip);
  358. if (ret)
  359. return ret;
  360. irq_domain_remove(p->irq_domain);
  361. return 0;
  362. }
  363. #ifdef CONFIG_OF
  364. static const struct of_device_id gpio_rcar_of_table[] = {
  365. {
  366. .compatible = "renesas,gpio-rcar",
  367. },
  368. { },
  369. };
  370. MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
  371. #endif
  372. static struct platform_driver gpio_rcar_device_driver = {
  373. .probe = gpio_rcar_probe,
  374. .remove = gpio_rcar_remove,
  375. .driver = {
  376. .name = "gpio_rcar",
  377. .of_match_table = of_match_ptr(gpio_rcar_of_table),
  378. }
  379. };
  380. module_platform_driver(gpio_rcar_device_driver);
  381. MODULE_AUTHOR("Magnus Damm");
  382. MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
  383. MODULE_LICENSE("GPL v2");