tegra-cpufreq.c 6.6 KB

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  1. /*
  2. * Copyright (C) 2010 Google, Inc.
  3. *
  4. * Author:
  5. * Colin Cross <ccross@google.com>
  6. * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
  7. *
  8. * This software is licensed under the terms of the GNU General Public
  9. * License version 2, as published by the Free Software Foundation, and
  10. * may be copied, distributed, and modified under those terms.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/types.h>
  21. #include <linux/sched.h>
  22. #include <linux/cpufreq.h>
  23. #include <linux/delay.h>
  24. #include <linux/init.h>
  25. #include <linux/err.h>
  26. #include <linux/clk.h>
  27. #include <linux/io.h>
  28. #include <linux/suspend.h>
  29. static struct cpufreq_frequency_table freq_table[] = {
  30. { .frequency = 216000 },
  31. { .frequency = 312000 },
  32. { .frequency = 456000 },
  33. { .frequency = 608000 },
  34. { .frequency = 760000 },
  35. { .frequency = 816000 },
  36. { .frequency = 912000 },
  37. { .frequency = 1000000 },
  38. { .frequency = CPUFREQ_TABLE_END },
  39. };
  40. #define NUM_CPUS 2
  41. static struct clk *cpu_clk;
  42. static struct clk *pll_x_clk;
  43. static struct clk *pll_p_clk;
  44. static struct clk *emc_clk;
  45. static unsigned long target_cpu_speed[NUM_CPUS];
  46. static DEFINE_MUTEX(tegra_cpu_lock);
  47. static bool is_suspended;
  48. static int tegra_verify_speed(struct cpufreq_policy *policy)
  49. {
  50. return cpufreq_frequency_table_verify(policy, freq_table);
  51. }
  52. static unsigned int tegra_getspeed(unsigned int cpu)
  53. {
  54. unsigned long rate;
  55. if (cpu >= NUM_CPUS)
  56. return 0;
  57. rate = clk_get_rate(cpu_clk) / 1000;
  58. return rate;
  59. }
  60. static int tegra_cpu_clk_set_rate(unsigned long rate)
  61. {
  62. int ret;
  63. /*
  64. * Take an extra reference to the main pll so it doesn't turn
  65. * off when we move the cpu off of it
  66. */
  67. clk_prepare_enable(pll_x_clk);
  68. ret = clk_set_parent(cpu_clk, pll_p_clk);
  69. if (ret) {
  70. pr_err("Failed to switch cpu to clock pll_p\n");
  71. goto out;
  72. }
  73. if (rate == clk_get_rate(pll_p_clk))
  74. goto out;
  75. ret = clk_set_rate(pll_x_clk, rate);
  76. if (ret) {
  77. pr_err("Failed to change pll_x to %lu\n", rate);
  78. goto out;
  79. }
  80. ret = clk_set_parent(cpu_clk, pll_x_clk);
  81. if (ret) {
  82. pr_err("Failed to switch cpu to clock pll_x\n");
  83. goto out;
  84. }
  85. out:
  86. clk_disable_unprepare(pll_x_clk);
  87. return ret;
  88. }
  89. static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
  90. unsigned long rate)
  91. {
  92. int ret = 0;
  93. struct cpufreq_freqs freqs;
  94. freqs.old = tegra_getspeed(0);
  95. freqs.new = rate;
  96. if (freqs.old == freqs.new)
  97. return ret;
  98. /*
  99. * Vote on memory bus frequency based on cpu frequency
  100. * This sets the minimum frequency, display or avp may request higher
  101. */
  102. if (rate >= 816000)
  103. clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
  104. else if (rate >= 456000)
  105. clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
  106. else
  107. clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
  108. cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  109. #ifdef CONFIG_CPU_FREQ_DEBUG
  110. printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
  111. freqs.old, freqs.new);
  112. #endif
  113. ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
  114. if (ret) {
  115. pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
  116. freqs.new);
  117. freqs.new = freqs.old;
  118. }
  119. cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
  120. return ret;
  121. }
  122. static unsigned long tegra_cpu_highest_speed(void)
  123. {
  124. unsigned long rate = 0;
  125. int i;
  126. for_each_online_cpu(i)
  127. rate = max(rate, target_cpu_speed[i]);
  128. return rate;
  129. }
  130. static int tegra_target(struct cpufreq_policy *policy,
  131. unsigned int target_freq,
  132. unsigned int relation)
  133. {
  134. unsigned int idx;
  135. unsigned int freq;
  136. int ret = 0;
  137. mutex_lock(&tegra_cpu_lock);
  138. if (is_suspended) {
  139. ret = -EBUSY;
  140. goto out;
  141. }
  142. cpufreq_frequency_table_target(policy, freq_table, target_freq,
  143. relation, &idx);
  144. freq = freq_table[idx].frequency;
  145. target_cpu_speed[policy->cpu] = freq;
  146. ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());
  147. out:
  148. mutex_unlock(&tegra_cpu_lock);
  149. return ret;
  150. }
  151. static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
  152. void *dummy)
  153. {
  154. mutex_lock(&tegra_cpu_lock);
  155. if (event == PM_SUSPEND_PREPARE) {
  156. struct cpufreq_policy *policy = cpufreq_cpu_get(0);
  157. is_suspended = true;
  158. pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
  159. freq_table[0].frequency);
  160. tegra_update_cpu_speed(policy, freq_table[0].frequency);
  161. cpufreq_cpu_put(policy);
  162. } else if (event == PM_POST_SUSPEND) {
  163. is_suspended = false;
  164. }
  165. mutex_unlock(&tegra_cpu_lock);
  166. return NOTIFY_OK;
  167. }
  168. static struct notifier_block tegra_cpu_pm_notifier = {
  169. .notifier_call = tegra_pm_notify,
  170. };
  171. static int tegra_cpu_init(struct cpufreq_policy *policy)
  172. {
  173. if (policy->cpu >= NUM_CPUS)
  174. return -EINVAL;
  175. clk_prepare_enable(emc_clk);
  176. clk_prepare_enable(cpu_clk);
  177. cpufreq_frequency_table_cpuinfo(policy, freq_table);
  178. cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
  179. policy->cur = tegra_getspeed(policy->cpu);
  180. target_cpu_speed[policy->cpu] = policy->cur;
  181. /* FIXME: what's the actual transition time? */
  182. policy->cpuinfo.transition_latency = 300 * 1000;
  183. cpumask_copy(policy->cpus, cpu_possible_mask);
  184. if (policy->cpu == 0)
  185. register_pm_notifier(&tegra_cpu_pm_notifier);
  186. return 0;
  187. }
  188. static int tegra_cpu_exit(struct cpufreq_policy *policy)
  189. {
  190. cpufreq_frequency_table_cpuinfo(policy, freq_table);
  191. clk_disable_unprepare(emc_clk);
  192. return 0;
  193. }
  194. static struct freq_attr *tegra_cpufreq_attr[] = {
  195. &cpufreq_freq_attr_scaling_available_freqs,
  196. NULL,
  197. };
  198. static struct cpufreq_driver tegra_cpufreq_driver = {
  199. .verify = tegra_verify_speed,
  200. .target = tegra_target,
  201. .get = tegra_getspeed,
  202. .init = tegra_cpu_init,
  203. .exit = tegra_cpu_exit,
  204. .name = "tegra",
  205. .attr = tegra_cpufreq_attr,
  206. };
  207. static int __init tegra_cpufreq_init(void)
  208. {
  209. cpu_clk = clk_get_sys(NULL, "cclk");
  210. if (IS_ERR(cpu_clk))
  211. return PTR_ERR(cpu_clk);
  212. pll_x_clk = clk_get_sys(NULL, "pll_x");
  213. if (IS_ERR(pll_x_clk))
  214. return PTR_ERR(pll_x_clk);
  215. pll_p_clk = clk_get_sys(NULL, "pll_p");
  216. if (IS_ERR(pll_p_clk))
  217. return PTR_ERR(pll_p_clk);
  218. emc_clk = clk_get_sys("cpu", "emc");
  219. if (IS_ERR(emc_clk)) {
  220. clk_put(cpu_clk);
  221. return PTR_ERR(emc_clk);
  222. }
  223. return cpufreq_register_driver(&tegra_cpufreq_driver);
  224. }
  225. static void __exit tegra_cpufreq_exit(void)
  226. {
  227. cpufreq_unregister_driver(&tegra_cpufreq_driver);
  228. clk_put(emc_clk);
  229. clk_put(cpu_clk);
  230. }
  231. MODULE_AUTHOR("Colin Cross <ccross@android.com>");
  232. MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
  233. MODULE_LICENSE("GPL");
  234. module_init(tegra_cpufreq_init);
  235. module_exit(tegra_cpufreq_exit);