spc.c 4.5 KB

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  1. /*
  2. * Versatile Express Serial Power Controller (SPC) support
  3. *
  4. * Copyright (C) 2013 ARM Ltd.
  5. *
  6. * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
  7. * Achin Gupta <achin.gupta@arm.com>
  8. * Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  15. * kind, whether express or implied; without even the implied warranty
  16. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. */
  19. #include <linux/err.h>
  20. #include <linux/io.h>
  21. #include <linux/slab.h>
  22. #include <asm/cacheflush.h>
  23. #define SPCLOG "vexpress-spc: "
  24. /* SPC wake-up IRQs status and mask */
  25. #define WAKE_INT_MASK 0x24
  26. #define WAKE_INT_RAW 0x28
  27. #define WAKE_INT_STAT 0x2c
  28. /* SPC power down registers */
  29. #define A15_PWRDN_EN 0x30
  30. #define A7_PWRDN_EN 0x34
  31. /* SPC per-CPU mailboxes */
  32. #define A15_BX_ADDR0 0x68
  33. #define A7_BX_ADDR0 0x78
  34. /* wake-up interrupt masks */
  35. #define GBL_WAKEUP_INT_MSK (0x3 << 10)
  36. /* TC2 static dual-cluster configuration */
  37. #define MAX_CLUSTERS 2
  38. struct ve_spc_drvdata {
  39. void __iomem *baseaddr;
  40. /*
  41. * A15s cluster identifier
  42. * It corresponds to A15 processors MPIDR[15:8] bitfield
  43. */
  44. u32 a15_clusid;
  45. };
  46. static struct ve_spc_drvdata *info;
  47. static inline bool cluster_is_a15(u32 cluster)
  48. {
  49. return cluster == info->a15_clusid;
  50. }
  51. /**
  52. * ve_spc_global_wakeup_irq()
  53. *
  54. * Function to set/clear global wakeup IRQs. Not protected by locking since
  55. * it might be used in code paths where normal cacheable locks are not
  56. * working. Locking must be provided by the caller to ensure atomicity.
  57. *
  58. * @set: if true, global wake-up IRQs are set, if false they are cleared
  59. */
  60. void ve_spc_global_wakeup_irq(bool set)
  61. {
  62. u32 reg;
  63. reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
  64. if (set)
  65. reg |= GBL_WAKEUP_INT_MSK;
  66. else
  67. reg &= ~GBL_WAKEUP_INT_MSK;
  68. writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
  69. }
  70. /**
  71. * ve_spc_cpu_wakeup_irq()
  72. *
  73. * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
  74. * it might be used in code paths where normal cacheable locks are not
  75. * working. Locking must be provided by the caller to ensure atomicity.
  76. *
  77. * @cluster: mpidr[15:8] bitfield describing cluster affinity level
  78. * @cpu: mpidr[7:0] bitfield describing cpu affinity level
  79. * @set: if true, wake-up IRQs are set, if false they are cleared
  80. */
  81. void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
  82. {
  83. u32 mask, reg;
  84. if (cluster >= MAX_CLUSTERS)
  85. return;
  86. mask = 1 << cpu;
  87. if (!cluster_is_a15(cluster))
  88. mask <<= 4;
  89. reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
  90. if (set)
  91. reg |= mask;
  92. else
  93. reg &= ~mask;
  94. writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
  95. }
  96. /**
  97. * ve_spc_set_resume_addr() - set the jump address used for warm boot
  98. *
  99. * @cluster: mpidr[15:8] bitfield describing cluster affinity level
  100. * @cpu: mpidr[7:0] bitfield describing cpu affinity level
  101. * @addr: physical resume address
  102. */
  103. void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
  104. {
  105. void __iomem *baseaddr;
  106. if (cluster >= MAX_CLUSTERS)
  107. return;
  108. if (cluster_is_a15(cluster))
  109. baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
  110. else
  111. baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
  112. writel_relaxed(addr, baseaddr);
  113. }
  114. /**
  115. * ve_spc_powerdown()
  116. *
  117. * Function to enable/disable cluster powerdown. Not protected by locking
  118. * since it might be used in code paths where normal cacheable locks are not
  119. * working. Locking must be provided by the caller to ensure atomicity.
  120. *
  121. * @cluster: mpidr[15:8] bitfield describing cluster affinity level
  122. * @enable: if true enables powerdown, if false disables it
  123. */
  124. void ve_spc_powerdown(u32 cluster, bool enable)
  125. {
  126. u32 pwdrn_reg;
  127. if (cluster >= MAX_CLUSTERS)
  128. return;
  129. pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
  130. writel_relaxed(enable, info->baseaddr + pwdrn_reg);
  131. }
  132. int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid)
  133. {
  134. info = kzalloc(sizeof(*info), GFP_KERNEL);
  135. if (!info) {
  136. pr_err(SPCLOG "unable to allocate mem\n");
  137. return -ENOMEM;
  138. }
  139. info->baseaddr = baseaddr;
  140. info->a15_clusid = a15_clusid;
  141. /*
  142. * Multi-cluster systems may need this data when non-coherent, during
  143. * cluster power-up/power-down. Make sure driver info reaches main
  144. * memory.
  145. */
  146. sync_cache_w(info);
  147. sync_cache_w(&info);
  148. return 0;
  149. }