lpc32xx.dtsi 6.3 KB

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  1. /*
  2. * NXP LPC32xx SoC
  3. *
  4. * Copyright 2012 Roland Stigge <stigge@antcom.de>
  5. *
  6. * The code contained herein is licensed under the GNU General Public
  7. * License. You may obtain a copy of the GNU General Public License
  8. * Version 2 or later at the following locations:
  9. *
  10. * http://www.opensource.org/licenses/gpl-license.html
  11. * http://www.gnu.org/copyleft/gpl.html
  12. */
  13. /include/ "skeleton.dtsi"
  14. / {
  15. compatible = "nxp,lpc3220";
  16. interrupt-parent = <&mic>;
  17. cpus {
  18. #address-cells = <0>;
  19. #size-cells = <0>;
  20. cpu {
  21. compatible = "arm,arm926ej-s";
  22. device_type = "cpu";
  23. };
  24. };
  25. ahb {
  26. #address-cells = <1>;
  27. #size-cells = <1>;
  28. compatible = "simple-bus";
  29. ranges = <0x20000000 0x20000000 0x30000000>;
  30. /*
  31. * Enable either SLC or MLC
  32. */
  33. slc: flash@20020000 {
  34. compatible = "nxp,lpc3220-slc";
  35. reg = <0x20020000 0x1000>;
  36. status = "disabled";
  37. };
  38. mlc: flash@200a8000 {
  39. compatible = "nxp,lpc3220-mlc";
  40. reg = <0x200a8000 0x11000>;
  41. interrupts = <11 0>;
  42. status = "disabled";
  43. };
  44. dma@31000000 {
  45. compatible = "arm,pl080", "arm,primecell";
  46. reg = <0x31000000 0x1000>;
  47. interrupts = <0x1c 0>;
  48. };
  49. /*
  50. * Enable either ohci or usbd (gadget)!
  51. */
  52. ohci@31020000 {
  53. compatible = "nxp,ohci-nxp", "usb-ohci";
  54. reg = <0x31020000 0x300>;
  55. interrupts = <0x3b 0>;
  56. status = "disabled";
  57. };
  58. usbd@31020000 {
  59. compatible = "nxp,lpc3220-udc";
  60. reg = <0x31020000 0x300>;
  61. interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
  62. status = "disabled";
  63. };
  64. clcd@31040000 {
  65. compatible = "arm,pl110", "arm,primecell";
  66. reg = <0x31040000 0x1000>;
  67. interrupts = <0x0e 0>;
  68. status = "disabled";
  69. };
  70. mac: ethernet@31060000 {
  71. compatible = "nxp,lpc-eth";
  72. reg = <0x31060000 0x1000>;
  73. interrupts = <0x1d 0>;
  74. };
  75. apb {
  76. #address-cells = <1>;
  77. #size-cells = <1>;
  78. compatible = "simple-bus";
  79. ranges = <0x20000000 0x20000000 0x30000000>;
  80. ssp0: ssp@20084000 {
  81. compatible = "arm,pl022", "arm,primecell";
  82. reg = <0x20084000 0x1000>;
  83. interrupts = <0x14 0>;
  84. };
  85. spi1: spi@20088000 {
  86. compatible = "nxp,lpc3220-spi";
  87. reg = <0x20088000 0x1000>;
  88. };
  89. ssp1: ssp@2008c000 {
  90. compatible = "arm,pl022", "arm,primecell";
  91. reg = <0x2008c000 0x1000>;
  92. interrupts = <0x15 0>;
  93. };
  94. spi2: spi@20090000 {
  95. compatible = "nxp,lpc3220-spi";
  96. reg = <0x20090000 0x1000>;
  97. };
  98. i2s0: i2s@20094000 {
  99. compatible = "nxp,lpc3220-i2s";
  100. reg = <0x20094000 0x1000>;
  101. };
  102. sd@20098000 {
  103. compatible = "arm,pl18x", "arm,primecell";
  104. reg = <0x20098000 0x1000>;
  105. interrupts = <0x0f 0>, <0x0d 0>;
  106. status = "disabled";
  107. };
  108. i2s1: i2s@2009C000 {
  109. compatible = "nxp,lpc3220-i2s";
  110. reg = <0x2009C000 0x1000>;
  111. };
  112. /* UART5 first since it is the default console, ttyS0 */
  113. uart5: serial@40090000 {
  114. /* actually, ns16550a w/ 64 byte fifos! */
  115. compatible = "nxp,lpc3220-uart";
  116. reg = <0x40090000 0x1000>;
  117. interrupts = <9 0>;
  118. clock-frequency = <13000000>;
  119. reg-shift = <2>;
  120. status = "disabled";
  121. };
  122. uart3: serial@40080000 {
  123. compatible = "nxp,lpc3220-uart";
  124. reg = <0x40080000 0x1000>;
  125. interrupts = <7 0>;
  126. clock-frequency = <13000000>;
  127. reg-shift = <2>;
  128. status = "disabled";
  129. };
  130. uart4: serial@40088000 {
  131. compatible = "nxp,lpc3220-uart";
  132. reg = <0x40088000 0x1000>;
  133. interrupts = <8 0>;
  134. clock-frequency = <13000000>;
  135. reg-shift = <2>;
  136. status = "disabled";
  137. };
  138. uart6: serial@40098000 {
  139. compatible = "nxp,lpc3220-uart";
  140. reg = <0x40098000 0x1000>;
  141. interrupts = <10 0>;
  142. clock-frequency = <13000000>;
  143. reg-shift = <2>;
  144. status = "disabled";
  145. };
  146. i2c1: i2c@400A0000 {
  147. compatible = "nxp,pnx-i2c";
  148. reg = <0x400A0000 0x100>;
  149. interrupts = <0x33 0>;
  150. #address-cells = <1>;
  151. #size-cells = <0>;
  152. pnx,timeout = <0x64>;
  153. };
  154. i2c2: i2c@400A8000 {
  155. compatible = "nxp,pnx-i2c";
  156. reg = <0x400A8000 0x100>;
  157. interrupts = <0x32 0>;
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. pnx,timeout = <0x64>;
  161. };
  162. mpwm: mpwm@400E8000 {
  163. compatible = "nxp,lpc3220-motor-pwm";
  164. reg = <0x400E8000 0x78>;
  165. status = "disabled";
  166. #pwm-cells = <2>;
  167. };
  168. i2cusb: i2c@31020300 {
  169. compatible = "nxp,pnx-i2c";
  170. reg = <0x31020300 0x100>;
  171. interrupts = <0x3f 0>;
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. pnx,timeout = <0x64>;
  175. };
  176. };
  177. fab {
  178. #address-cells = <1>;
  179. #size-cells = <1>;
  180. compatible = "simple-bus";
  181. ranges = <0x20000000 0x20000000 0x30000000>;
  182. /*
  183. * MIC Interrupt controller includes:
  184. * MIC @40008000
  185. * SIC1 @4000C000
  186. * SIC2 @40010000
  187. */
  188. mic: interrupt-controller@40008000 {
  189. compatible = "nxp,lpc3220-mic";
  190. interrupt-controller;
  191. reg = <0x40008000 0xC000>;
  192. #interrupt-cells = <2>;
  193. };
  194. uart1: serial@40014000 {
  195. compatible = "nxp,lpc3220-hsuart";
  196. reg = <0x40014000 0x1000>;
  197. interrupts = <26 0>;
  198. status = "disabled";
  199. };
  200. uart2: serial@40018000 {
  201. compatible = "nxp,lpc3220-hsuart";
  202. reg = <0x40018000 0x1000>;
  203. interrupts = <25 0>;
  204. status = "disabled";
  205. };
  206. uart7: serial@4001c000 {
  207. compatible = "nxp,lpc3220-hsuart";
  208. reg = <0x4001c000 0x1000>;
  209. interrupts = <24 0>;
  210. status = "disabled";
  211. };
  212. rtc@40024000 {
  213. compatible = "nxp,lpc3220-rtc";
  214. reg = <0x40024000 0x1000>;
  215. interrupts = <0x34 0>;
  216. };
  217. gpio: gpio@40028000 {
  218. compatible = "nxp,lpc3220-gpio";
  219. reg = <0x40028000 0x1000>;
  220. gpio-controller;
  221. #gpio-cells = <3>; /* bank, pin, flags */
  222. };
  223. watchdog@4003C000 {
  224. compatible = "nxp,pnx4008-wdt";
  225. reg = <0x4003C000 0x1000>;
  226. };
  227. /*
  228. * TSC vs. ADC: Since those two share the same
  229. * hardware, you need to choose from one of the
  230. * following two and do 'status = "okay";' for one of
  231. * them
  232. */
  233. adc@40048000 {
  234. compatible = "nxp,lpc3220-adc";
  235. reg = <0x40048000 0x1000>;
  236. interrupts = <0x27 0>;
  237. status = "disabled";
  238. };
  239. tsc@40048000 {
  240. compatible = "nxp,lpc3220-tsc";
  241. reg = <0x40048000 0x1000>;
  242. interrupts = <0x27 0>;
  243. status = "disabled";
  244. };
  245. key@40050000 {
  246. compatible = "nxp,lpc3220-key";
  247. reg = <0x40050000 0x1000>;
  248. interrupts = <54 0>;
  249. status = "disabled";
  250. };
  251. pwm: pwm@4005C000 {
  252. compatible = "nxp,lpc3220-pwm";
  253. reg = <0x4005C000 0x8>;
  254. status = "disabled";
  255. };
  256. };
  257. };
  258. };