keystone.dts 2.6 KB

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  1. /*
  2. * Copyright 2013 Texas Instruments, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. #include <dt-bindings/interrupt-controller/arm-gic.h>
  10. #include "skeleton.dtsi"
  11. / {
  12. model = "Texas Instruments Keystone 2 SoC";
  13. compatible = "ti,keystone-evm";
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. interrupt-parent = <&gic>;
  17. aliases {
  18. serial0 = &uart0;
  19. };
  20. memory {
  21. reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. interrupt-parent = <&gic>;
  27. cpu@0 {
  28. compatible = "arm,cortex-a15";
  29. device_type = "cpu";
  30. reg = <0>;
  31. };
  32. cpu@1 {
  33. compatible = "arm,cortex-a15";
  34. device_type = "cpu";
  35. reg = <1>;
  36. };
  37. cpu@2 {
  38. compatible = "arm,cortex-a15";
  39. device_type = "cpu";
  40. reg = <2>;
  41. };
  42. cpu@3 {
  43. compatible = "arm,cortex-a15";
  44. device_type = "cpu";
  45. reg = <3>;
  46. };
  47. };
  48. gic: interrupt-controller {
  49. compatible = "arm,cortex-a15-gic";
  50. #interrupt-cells = <3>;
  51. #size-cells = <0>;
  52. #address-cells = <1>;
  53. interrupt-controller;
  54. reg = <0x0 0x02561000 0x0 0x1000>,
  55. <0x0 0x02562000 0x0 0x2000>;
  56. };
  57. timer {
  58. compatible = "arm,armv7-timer";
  59. interrupts =
  60. <GIC_PPI 13
  61. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  62. <GIC_PPI 14
  63. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  64. <GIC_PPI 11
  65. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  66. <GIC_PPI 10
  67. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  68. };
  69. pmu {
  70. compatible = "arm,cortex-a15-pmu";
  71. interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
  72. <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
  73. <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
  74. <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
  75. };
  76. soc {
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. compatible = "ti,keystone","simple-bus";
  80. interrupt-parent = <&gic>;
  81. ranges = <0x0 0x0 0x0 0xc0000000>;
  82. rstctrl: reset-controller {
  83. compatible = "ti,keystone-reset";
  84. reg = <0x023100e8 4>; /* pll reset control reg */
  85. };
  86. uart0: serial@02530c00 {
  87. compatible = "ns16550a";
  88. current-speed = <115200>;
  89. reg-shift = <2>;
  90. reg-io-width = <4>;
  91. reg = <0x02530c00 0x100>;
  92. clock-frequency = <133120000>;
  93. interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
  94. };
  95. uart1: serial@02531000 {
  96. compatible = "ns16550a";
  97. current-speed = <115200>;
  98. reg-shift = <2>;
  99. reg-io-width = <4>;
  100. reg = <0x02531000 0x100>;
  101. clock-frequency = <133120000>;
  102. interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
  103. };
  104. };
  105. };