imx25.dtsi 12 KB

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  1. /*
  2. * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. #include "skeleton.dtsi"
  12. / {
  13. aliases {
  14. gpio0 = &gpio1;
  15. gpio1 = &gpio2;
  16. gpio2 = &gpio3;
  17. gpio3 = &gpio4;
  18. i2c0 = &i2c1;
  19. i2c1 = &i2c2;
  20. i2c2 = &i2c3;
  21. serial0 = &uart1;
  22. serial1 = &uart2;
  23. serial2 = &uart3;
  24. serial3 = &uart4;
  25. serial4 = &uart5;
  26. spi0 = &spi1;
  27. spi1 = &spi2;
  28. spi2 = &spi3;
  29. usb0 = &usbotg;
  30. usb1 = &usbhost1;
  31. };
  32. cpus {
  33. #address-cells = <0>;
  34. #size-cells = <0>;
  35. cpu {
  36. compatible = "arm,arm926ej-s";
  37. device_type = "cpu";
  38. };
  39. };
  40. asic: asic-interrupt-controller@68000000 {
  41. compatible = "fsl,imx25-asic", "fsl,avic";
  42. interrupt-controller;
  43. #interrupt-cells = <1>;
  44. reg = <0x68000000 0x8000000>;
  45. };
  46. clocks {
  47. #address-cells = <1>;
  48. #size-cells = <0>;
  49. osc {
  50. compatible = "fsl,imx-osc", "fixed-clock";
  51. clock-frequency = <24000000>;
  52. };
  53. };
  54. soc {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "simple-bus";
  58. interrupt-parent = <&asic>;
  59. ranges;
  60. aips@43f00000 { /* AIPS1 */
  61. compatible = "fsl,aips-bus", "simple-bus";
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. reg = <0x43f00000 0x100000>;
  65. ranges;
  66. i2c1: i2c@43f80000 {
  67. #address-cells = <1>;
  68. #size-cells = <0>;
  69. compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
  70. reg = <0x43f80000 0x4000>;
  71. clocks = <&clks 48>;
  72. clock-names = "";
  73. interrupts = <3>;
  74. status = "disabled";
  75. };
  76. i2c3: i2c@43f84000 {
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
  80. reg = <0x43f84000 0x4000>;
  81. clocks = <&clks 48>;
  82. clock-names = "";
  83. interrupts = <10>;
  84. status = "disabled";
  85. };
  86. can1: can@43f88000 {
  87. compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
  88. reg = <0x43f88000 0x4000>;
  89. interrupts = <43>;
  90. clocks = <&clks 75>, <&clks 75>;
  91. clock-names = "ipg", "per";
  92. status = "disabled";
  93. };
  94. can2: can@43f8c000 {
  95. compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
  96. reg = <0x43f8c000 0x4000>;
  97. interrupts = <44>;
  98. clocks = <&clks 76>, <&clks 76>;
  99. clock-names = "ipg", "per";
  100. status = "disabled";
  101. };
  102. uart1: serial@43f90000 {
  103. compatible = "fsl,imx25-uart", "fsl,imx21-uart";
  104. reg = <0x43f90000 0x4000>;
  105. interrupts = <45>;
  106. clocks = <&clks 120>, <&clks 57>;
  107. clock-names = "ipg", "per";
  108. status = "disabled";
  109. };
  110. uart2: serial@43f94000 {
  111. compatible = "fsl,imx25-uart", "fsl,imx21-uart";
  112. reg = <0x43f94000 0x4000>;
  113. interrupts = <32>;
  114. clocks = <&clks 121>, <&clks 57>;
  115. clock-names = "ipg", "per";
  116. status = "disabled";
  117. };
  118. i2c2: i2c@43f98000 {
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121. compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
  122. reg = <0x43f98000 0x4000>;
  123. clocks = <&clks 48>;
  124. clock-names = "";
  125. interrupts = <4>;
  126. status = "disabled";
  127. };
  128. owire@43f9c000 {
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. reg = <0x43f9c000 0x4000>;
  132. clocks = <&clks 51>;
  133. clock-names = "";
  134. interrupts = <2>;
  135. status = "disabled";
  136. };
  137. spi1: cspi@43fa4000 {
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
  141. reg = <0x43fa4000 0x4000>;
  142. clocks = <&clks 62>, <&clks 62>;
  143. clock-names = "ipg", "per";
  144. interrupts = <14>;
  145. status = "disabled";
  146. };
  147. kpp@43fa8000 {
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. reg = <0x43fa8000 0x4000>;
  151. clocks = <&clks 102>;
  152. clock-names = "";
  153. interrupts = <24>;
  154. status = "disabled";
  155. };
  156. iomuxc@43fac000{
  157. compatible = "fsl,imx25-iomuxc";
  158. reg = <0x43fac000 0x4000>;
  159. };
  160. audmux@43fb0000 {
  161. compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
  162. reg = <0x43fb0000 0x4000>;
  163. status = "disabled";
  164. };
  165. };
  166. spba@50000000 {
  167. compatible = "fsl,spba-bus", "simple-bus";
  168. #address-cells = <1>;
  169. #size-cells = <1>;
  170. reg = <0x50000000 0x40000>;
  171. ranges;
  172. spi3: cspi@50004000 {
  173. #address-cells = <1>;
  174. #size-cells = <0>;
  175. compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
  176. reg = <0x50004000 0x4000>;
  177. interrupts = <0>;
  178. clocks = <&clks 80>, <&clks 80>;
  179. clock-names = "ipg", "per";
  180. status = "disabled";
  181. };
  182. uart4: serial@50008000 {
  183. compatible = "fsl,imx25-uart", "fsl,imx21-uart";
  184. reg = <0x50008000 0x4000>;
  185. interrupts = <5>;
  186. clocks = <&clks 123>, <&clks 57>;
  187. clock-names = "ipg", "per";
  188. status = "disabled";
  189. };
  190. uart3: serial@5000c000 {
  191. compatible = "fsl,imx25-uart", "fsl,imx21-uart";
  192. reg = <0x5000c000 0x4000>;
  193. interrupts = <18>;
  194. clocks = <&clks 122>, <&clks 57>;
  195. clock-names = "ipg", "per";
  196. status = "disabled";
  197. };
  198. spi2: cspi@50010000 {
  199. #address-cells = <1>;
  200. #size-cells = <0>;
  201. compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
  202. reg = <0x50010000 0x4000>;
  203. clocks = <&clks 79>, <&clks 79>;
  204. clock-names = "ipg", "per";
  205. interrupts = <13>;
  206. status = "disabled";
  207. };
  208. ssi2: ssi@50014000 {
  209. compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
  210. reg = <0x50014000 0x4000>;
  211. interrupts = <11>;
  212. status = "disabled";
  213. };
  214. esai@50018000 {
  215. reg = <0x50018000 0x4000>;
  216. interrupts = <7>;
  217. };
  218. uart5: serial@5002c000 {
  219. compatible = "fsl,imx25-uart", "fsl,imx21-uart";
  220. reg = <0x5002c000 0x4000>;
  221. interrupts = <40>;
  222. clocks = <&clks 124>, <&clks 57>;
  223. clock-names = "ipg", "per";
  224. status = "disabled";
  225. };
  226. tsc: tsc@50030000 {
  227. compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
  228. reg = <0x50030000 0x4000>;
  229. interrupts = <46>;
  230. clocks = <&clks 119>;
  231. clock-names = "ipg";
  232. status = "disabled";
  233. };
  234. ssi1: ssi@50034000 {
  235. compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
  236. reg = <0x50034000 0x4000>;
  237. interrupts = <12>;
  238. status = "disabled";
  239. };
  240. fec: ethernet@50038000 {
  241. compatible = "fsl,imx25-fec";
  242. reg = <0x50038000 0x4000>;
  243. interrupts = <57>;
  244. clocks = <&clks 88>, <&clks 65>;
  245. clock-names = "ipg", "ahb";
  246. status = "disabled";
  247. };
  248. };
  249. aips@53f00000 { /* AIPS2 */
  250. compatible = "fsl,aips-bus", "simple-bus";
  251. #address-cells = <1>;
  252. #size-cells = <1>;
  253. reg = <0x53f00000 0x100000>;
  254. ranges;
  255. clks: ccm@53f80000 {
  256. compatible = "fsl,imx25-ccm";
  257. reg = <0x53f80000 0x4000>;
  258. interrupts = <31>;
  259. #clock-cells = <1>;
  260. };
  261. gpt4: timer@53f84000 {
  262. compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
  263. reg = <0x53f84000 0x4000>;
  264. clocks = <&clks 9>, <&clks 45>;
  265. clock-names = "ipg", "per";
  266. interrupts = <1>;
  267. };
  268. gpt3: timer@53f88000 {
  269. compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
  270. reg = <0x53f88000 0x4000>;
  271. clocks = <&clks 9>, <&clks 47>;
  272. clock-names = "ipg", "per";
  273. interrupts = <29>;
  274. };
  275. gpt2: timer@53f8c000 {
  276. compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
  277. reg = <0x53f8c000 0x4000>;
  278. clocks = <&clks 9>, <&clks 47>;
  279. clock-names = "ipg", "per";
  280. interrupts = <53>;
  281. };
  282. gpt1: timer@53f90000 {
  283. compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
  284. reg = <0x53f90000 0x4000>;
  285. clocks = <&clks 9>, <&clks 47>;
  286. clock-names = "ipg", "per";
  287. interrupts = <54>;
  288. };
  289. epit1: timer@53f94000 {
  290. compatible = "fsl,imx25-epit";
  291. reg = <0x53f94000 0x4000>;
  292. interrupts = <28>;
  293. };
  294. epit2: timer@53f98000 {
  295. compatible = "fsl,imx25-epit";
  296. reg = <0x53f98000 0x4000>;
  297. interrupts = <27>;
  298. };
  299. gpio4: gpio@53f9c000 {
  300. compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
  301. reg = <0x53f9c000 0x4000>;
  302. interrupts = <23>;
  303. gpio-controller;
  304. #gpio-cells = <2>;
  305. interrupt-controller;
  306. #interrupt-cells = <2>;
  307. };
  308. pwm2: pwm@53fa0000 {
  309. compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
  310. #pwm-cells = <2>;
  311. reg = <0x53fa0000 0x4000>;
  312. clocks = <&clks 106>, <&clks 36>;
  313. clock-names = "ipg", "per";
  314. interrupts = <36>;
  315. };
  316. gpio3: gpio@53fa4000 {
  317. compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
  318. reg = <0x53fa4000 0x4000>;
  319. interrupts = <16>;
  320. gpio-controller;
  321. #gpio-cells = <2>;
  322. interrupt-controller;
  323. #interrupt-cells = <2>;
  324. };
  325. pwm3: pwm@53fa8000 {
  326. compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
  327. #pwm-cells = <2>;
  328. reg = <0x53fa8000 0x4000>;
  329. clocks = <&clks 107>, <&clks 36>;
  330. clock-names = "ipg", "per";
  331. interrupts = <41>;
  332. };
  333. esdhc1: esdhc@53fb4000 {
  334. compatible = "fsl,imx25-esdhc";
  335. reg = <0x53fb4000 0x4000>;
  336. interrupts = <9>;
  337. clocks = <&clks 86>, <&clks 63>, <&clks 45>;
  338. clock-names = "ipg", "ahb", "per";
  339. status = "disabled";
  340. };
  341. esdhc2: esdhc@53fb8000 {
  342. compatible = "fsl,imx25-esdhc";
  343. reg = <0x53fb8000 0x4000>;
  344. interrupts = <8>;
  345. clocks = <&clks 87>, <&clks 64>, <&clks 46>;
  346. clock-names = "ipg", "ahb", "per";
  347. status = "disabled";
  348. };
  349. lcdc: lcdc@53fbc000 {
  350. compatible = "fsl,imx25-fb", "fsl,imx21-fb";
  351. reg = <0x53fbc000 0x4000>;
  352. interrupts = <39>;
  353. clocks = <&clks 103>, <&clks 66>, <&clks 49>;
  354. clock-names = "ipg", "ahb", "per";
  355. status = "disabled";
  356. };
  357. slcdc@53fc0000 {
  358. reg = <0x53fc0000 0x4000>;
  359. interrupts = <38>;
  360. status = "disabled";
  361. };
  362. pwm4: pwm@53fc8000 {
  363. compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
  364. reg = <0x53fc8000 0x4000>;
  365. clocks = <&clks 108>, <&clks 36>;
  366. clock-names = "ipg", "per";
  367. interrupts = <42>;
  368. };
  369. gpio1: gpio@53fcc000 {
  370. compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
  371. reg = <0x53fcc000 0x4000>;
  372. interrupts = <52>;
  373. gpio-controller;
  374. #gpio-cells = <2>;
  375. interrupt-controller;
  376. #interrupt-cells = <2>;
  377. };
  378. gpio2: gpio@53fd0000 {
  379. compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
  380. reg = <0x53fd0000 0x4000>;
  381. interrupts = <51>;
  382. gpio-controller;
  383. #gpio-cells = <2>;
  384. interrupt-controller;
  385. #interrupt-cells = <2>;
  386. };
  387. sdma@53fd4000 {
  388. compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
  389. reg = <0x53fd4000 0x4000>;
  390. clocks = <&clks 112>, <&clks 68>;
  391. clock-names = "ipg", "ahb";
  392. #dma-cells = <3>;
  393. interrupts = <34>;
  394. };
  395. wdog@53fdc000 {
  396. compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
  397. reg = <0x53fdc000 0x4000>;
  398. clocks = <&clks 126>;
  399. clock-names = "";
  400. interrupts = <55>;
  401. };
  402. pwm1: pwm@53fe0000 {
  403. compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
  404. #pwm-cells = <2>;
  405. reg = <0x53fe0000 0x4000>;
  406. clocks = <&clks 105>, <&clks 36>;
  407. clock-names = "ipg", "per";
  408. interrupts = <26>;
  409. };
  410. iim: iim@53ff0000 {
  411. compatible = "fsl,imx25-iim", "fsl,imx27-iim";
  412. reg = <0x53ff0000 0x4000>;
  413. interrupts = <19>;
  414. clocks = <&clks 99>;
  415. };
  416. usbphy1: usbphy@1 {
  417. compatible = "nop-usbphy";
  418. status = "disabled";
  419. };
  420. usbphy2: usbphy@2 {
  421. compatible = "nop-usbphy";
  422. status = "disabled";
  423. };
  424. usbotg: usb@53ff4000 {
  425. compatible = "fsl,imx25-usb", "fsl,imx27-usb";
  426. reg = <0x53ff4000 0x0200>;
  427. interrupts = <37>;
  428. clocks = <&clks 9>, <&clks 70>, <&clks 8>;
  429. clock-names = "ipg", "ahb", "per";
  430. fsl,usbmisc = <&usbmisc 0>;
  431. status = "disabled";
  432. };
  433. usbhost1: usb@53ff4400 {
  434. compatible = "fsl,imx25-usb", "fsl,imx27-usb";
  435. reg = <0x53ff4400 0x0200>;
  436. interrupts = <35>;
  437. clocks = <&clks 9>, <&clks 70>, <&clks 8>;
  438. clock-names = "ipg", "ahb", "per";
  439. fsl,usbmisc = <&usbmisc 1>;
  440. status = "disabled";
  441. };
  442. usbmisc: usbmisc@53ff4600 {
  443. #index-cells = <1>;
  444. compatible = "fsl,imx25-usbmisc";
  445. clocks = <&clks 9>, <&clks 70>, <&clks 8>;
  446. clock-names = "ipg", "ahb", "per";
  447. reg = <0x53ff4600 0x00f>;
  448. status = "disabled";
  449. };
  450. dryice@53ffc000 {
  451. compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
  452. reg = <0x53ffc000 0x4000>;
  453. clocks = <&clks 81>;
  454. clock-names = "ipg";
  455. interrupts = <25>;
  456. };
  457. };
  458. emi@80000000 {
  459. compatible = "fsl,emi-bus", "simple-bus";
  460. #address-cells = <1>;
  461. #size-cells = <1>;
  462. reg = <0x80000000 0x3b002000>;
  463. ranges;
  464. nfc: nand@bb000000 {
  465. #address-cells = <1>;
  466. #size-cells = <1>;
  467. compatible = "fsl,imx25-nand";
  468. reg = <0xbb000000 0x2000>;
  469. clocks = <&clks 50>;
  470. clock-names = "";
  471. interrupts = <33>;
  472. status = "disabled";
  473. };
  474. };
  475. };
  476. };