emev2.dtsi 2.7 KB

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  1. /*
  2. * Device Tree Source for the EMEV2 SoC
  3. *
  4. * Copyright (C) 2012 Renesas Solutions Corp.
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "renesas,emev2";
  13. interrupt-parent = <&gic>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. gpio3 = &gpio3;
  19. gpio4 = &gpio4;
  20. };
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. cpu@0 {
  25. device_type = "cpu";
  26. compatible = "arm,cortex-a9";
  27. reg = <0>;
  28. };
  29. cpu@1 {
  30. device_type = "cpu";
  31. compatible = "arm,cortex-a9";
  32. reg = <1>;
  33. };
  34. };
  35. gic: interrupt-controller@e0020000 {
  36. compatible = "arm,cortex-a9-gic";
  37. interrupt-controller;
  38. #interrupt-cells = <3>;
  39. reg = <0xe0028000 0x1000>,
  40. <0xe0020000 0x0100>;
  41. };
  42. pmu {
  43. compatible = "arm,cortex-a9-pmu";
  44. interrupts = <0 120 4>,
  45. <0 121 4>;
  46. };
  47. sti@e0180000 {
  48. compatible = "renesas,em-sti";
  49. reg = <0xe0180000 0x54>;
  50. interrupts = <0 125 0>;
  51. };
  52. uart@e1020000 {
  53. compatible = "renesas,em-uart";
  54. reg = <0xe1020000 0x38>;
  55. interrupts = <0 8 0>;
  56. };
  57. uart@e1030000 {
  58. compatible = "renesas,em-uart";
  59. reg = <0xe1030000 0x38>;
  60. interrupts = <0 9 0>;
  61. };
  62. uart@e1040000 {
  63. compatible = "renesas,em-uart";
  64. reg = <0xe1040000 0x38>;
  65. interrupts = <0 10 0>;
  66. };
  67. uart@e1050000 {
  68. compatible = "renesas,em-uart";
  69. reg = <0xe1050000 0x38>;
  70. interrupts = <0 11 0>;
  71. };
  72. gpio0: gpio@e0050000 {
  73. compatible = "renesas,em-gio";
  74. reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
  75. interrupts = <0 67 0>, <0 68 0>;
  76. gpio-controller;
  77. #gpio-cells = <2>;
  78. ngpios = <32>;
  79. interrupt-controller;
  80. #interrupt-cells = <2>;
  81. };
  82. gpio1: gpio@e0050080 {
  83. compatible = "renesas,em-gio";
  84. reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
  85. interrupts = <0 69 0>, <0 70 0>;
  86. gpio-controller;
  87. #gpio-cells = <2>;
  88. ngpios = <32>;
  89. interrupt-controller;
  90. #interrupt-cells = <2>;
  91. };
  92. gpio2: gpio@e0050100 {
  93. compatible = "renesas,em-gio";
  94. reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
  95. interrupts = <0 71 0>, <0 72 0>;
  96. gpio-controller;
  97. #gpio-cells = <2>;
  98. ngpios = <32>;
  99. interrupt-controller;
  100. #interrupt-cells = <2>;
  101. };
  102. gpio3: gpio@e0050180 {
  103. compatible = "renesas,em-gio";
  104. reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
  105. interrupts = <0 73 0>, <0 74 0>;
  106. gpio-controller;
  107. #gpio-cells = <2>;
  108. ngpios = <32>;
  109. interrupt-controller;
  110. #interrupt-cells = <2>;
  111. };
  112. gpio4: gpio@e0050200 {
  113. compatible = "renesas,em-gio";
  114. reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
  115. interrupts = <0 75 0>, <0 76 0>;
  116. gpio-controller;
  117. #gpio-cells = <2>;
  118. ngpios = <31>;
  119. interrupt-controller;
  120. #interrupt-cells = <2>;
  121. };
  122. };