dove.dtsi 10 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "marvell,dove";
  4. model = "Marvell Armada 88AP510 SoC";
  5. aliases {
  6. gpio0 = &gpio0;
  7. gpio1 = &gpio1;
  8. gpio2 = &gpio2;
  9. };
  10. cpus {
  11. #address-cells = <1>;
  12. #size-cells = <0>;
  13. cpu0: cpu@0 {
  14. compatible = "marvell,pj4a", "marvell,sheeva-v7";
  15. device_type = "cpu";
  16. next-level-cache = <&l2>;
  17. reg = <0>;
  18. };
  19. };
  20. l2: l2-cache {
  21. compatible = "marvell,tauros2-cache";
  22. marvell,tauros2-cache-features = <0>;
  23. };
  24. soc@f1000000 {
  25. compatible = "simple-bus";
  26. #address-cells = <1>;
  27. #size-cells = <1>;
  28. interrupt-parent = <&intc>;
  29. ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
  30. 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
  31. 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
  32. 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
  33. 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
  34. 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
  35. 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
  36. 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
  37. timer: timer@20300 {
  38. compatible = "marvell,orion-timer";
  39. reg = <0x20300 0x20>;
  40. interrupt-parent = <&bridge_intc>;
  41. interrupts = <1>, <2>;
  42. clocks = <&core_clk 0>;
  43. };
  44. intc: main-interrupt-ctrl@20200 {
  45. compatible = "marvell,orion-intc";
  46. interrupt-controller;
  47. #interrupt-cells = <1>;
  48. reg = <0x20200 0x10>, <0x20210 0x10>;
  49. };
  50. bridge_intc: bridge-interrupt-ctrl@20110 {
  51. compatible = "marvell,orion-bridge-intc";
  52. interrupt-controller;
  53. #interrupt-cells = <1>;
  54. reg = <0x20110 0x8>;
  55. interrupts = <0>;
  56. marvell,#interrupts = <5>;
  57. };
  58. core_clk: core-clocks@d0214 {
  59. compatible = "marvell,dove-core-clock";
  60. reg = <0xd0214 0x4>;
  61. #clock-cells = <1>;
  62. };
  63. gate_clk: clock-gating-ctrl@d0038 {
  64. compatible = "marvell,dove-gating-clock";
  65. reg = <0xd0038 0x4>;
  66. clocks = <&core_clk 0>;
  67. #clock-cells = <1>;
  68. };
  69. thermal: thermal-diode@d001c {
  70. compatible = "marvell,dove-thermal";
  71. reg = <0xd001c 0x0c>, <0xd005c 0x08>;
  72. };
  73. uart0: serial@12000 {
  74. compatible = "ns16550a";
  75. reg = <0x12000 0x100>;
  76. reg-shift = <2>;
  77. interrupts = <7>;
  78. clocks = <&core_clk 0>;
  79. status = "disabled";
  80. };
  81. uart1: serial@12100 {
  82. compatible = "ns16550a";
  83. reg = <0x12100 0x100>;
  84. reg-shift = <2>;
  85. interrupts = <8>;
  86. clocks = <&core_clk 0>;
  87. pinctrl-0 = <&pmx_uart1>;
  88. pinctrl-names = "default";
  89. status = "disabled";
  90. };
  91. uart2: serial@12200 {
  92. compatible = "ns16550a";
  93. reg = <0x12000 0x100>;
  94. reg-shift = <2>;
  95. interrupts = <9>;
  96. clocks = <&core_clk 0>;
  97. status = "disabled";
  98. };
  99. uart3: serial@12300 {
  100. compatible = "ns16550a";
  101. reg = <0x12100 0x100>;
  102. reg-shift = <2>;
  103. interrupts = <10>;
  104. clocks = <&core_clk 0>;
  105. status = "disabled";
  106. };
  107. gpio0: gpio-ctrl@d0400 {
  108. compatible = "marvell,orion-gpio";
  109. #gpio-cells = <2>;
  110. gpio-controller;
  111. reg = <0xd0400 0x20>;
  112. ngpios = <32>;
  113. interrupt-controller;
  114. #interrupt-cells = <2>;
  115. interrupts = <12>, <13>, <14>, <60>;
  116. };
  117. gpio1: gpio-ctrl@d0420 {
  118. compatible = "marvell,orion-gpio";
  119. #gpio-cells = <2>;
  120. gpio-controller;
  121. reg = <0xd0420 0x20>;
  122. ngpios = <32>;
  123. interrupt-controller;
  124. #interrupt-cells = <2>;
  125. interrupts = <61>;
  126. };
  127. gpio2: gpio-ctrl@e8400 {
  128. compatible = "marvell,orion-gpio";
  129. #gpio-cells = <2>;
  130. gpio-controller;
  131. reg = <0xe8400 0x0c>;
  132. ngpios = <8>;
  133. };
  134. pinctrl: pin-ctrl@d0200 {
  135. compatible = "marvell,dove-pinctrl";
  136. reg = <0xd0200 0x10>;
  137. clocks = <&gate_clk 22>;
  138. pmx_gpio_0: pmx-gpio-0 {
  139. marvell,pins = "mpp0";
  140. marvell,function = "gpio";
  141. };
  142. pmx_gpio_1: pmx-gpio-1 {
  143. marvell,pins = "mpp1";
  144. marvell,function = "gpio";
  145. };
  146. pmx_gpio_2: pmx-gpio-2 {
  147. marvell,pins = "mpp2";
  148. marvell,function = "gpio";
  149. };
  150. pmx_gpio_3: pmx-gpio-3 {
  151. marvell,pins = "mpp3";
  152. marvell,function = "gpio";
  153. };
  154. pmx_gpio_4: pmx-gpio-4 {
  155. marvell,pins = "mpp4";
  156. marvell,function = "gpio";
  157. };
  158. pmx_gpio_5: pmx-gpio-5 {
  159. marvell,pins = "mpp5";
  160. marvell,function = "gpio";
  161. };
  162. pmx_gpio_6: pmx-gpio-6 {
  163. marvell,pins = "mpp6";
  164. marvell,function = "gpio";
  165. };
  166. pmx_gpio_7: pmx-gpio-7 {
  167. marvell,pins = "mpp7";
  168. marvell,function = "gpio";
  169. };
  170. pmx_gpio_8: pmx-gpio-8 {
  171. marvell,pins = "mpp8";
  172. marvell,function = "gpio";
  173. };
  174. pmx_gpio_9: pmx-gpio-9 {
  175. marvell,pins = "mpp9";
  176. marvell,function = "gpio";
  177. };
  178. pmx_gpio_10: pmx-gpio-10 {
  179. marvell,pins = "mpp10";
  180. marvell,function = "gpio";
  181. };
  182. pmx_gpio_11: pmx-gpio-11 {
  183. marvell,pins = "mpp11";
  184. marvell,function = "gpio";
  185. };
  186. pmx_gpio_12: pmx-gpio-12 {
  187. marvell,pins = "mpp12";
  188. marvell,function = "gpio";
  189. };
  190. pmx_gpio_13: pmx-gpio-13 {
  191. marvell,pins = "mpp13";
  192. marvell,function = "gpio";
  193. };
  194. pmx_gpio_14: pmx-gpio-14 {
  195. marvell,pins = "mpp14";
  196. marvell,function = "gpio";
  197. };
  198. pmx_gpio_15: pmx-gpio-15 {
  199. marvell,pins = "mpp15";
  200. marvell,function = "gpio";
  201. };
  202. pmx_gpio_16: pmx-gpio-16 {
  203. marvell,pins = "mpp16";
  204. marvell,function = "gpio";
  205. };
  206. pmx_gpio_17: pmx-gpio-17 {
  207. marvell,pins = "mpp17";
  208. marvell,function = "gpio";
  209. };
  210. pmx_gpio_18: pmx-gpio-18 {
  211. marvell,pins = "mpp18";
  212. marvell,function = "gpio";
  213. };
  214. pmx_gpio_19: pmx-gpio-19 {
  215. marvell,pins = "mpp19";
  216. marvell,function = "gpio";
  217. };
  218. pmx_gpio_20: pmx-gpio-20 {
  219. marvell,pins = "mpp20";
  220. marvell,function = "gpio";
  221. };
  222. pmx_gpio_21: pmx-gpio-21 {
  223. marvell,pins = "mpp21";
  224. marvell,function = "gpio";
  225. };
  226. pmx_camera: pmx-camera {
  227. marvell,pins = "mpp_camera";
  228. marvell,function = "camera";
  229. };
  230. pmx_camera_gpio: pmx-camera-gpio {
  231. marvell,pins = "mpp_camera";
  232. marvell,function = "gpio";
  233. };
  234. pmx_sdio0: pmx-sdio0 {
  235. marvell,pins = "mpp_sdio0";
  236. marvell,function = "sdio0";
  237. };
  238. pmx_sdio0_gpio: pmx-sdio0-gpio {
  239. marvell,pins = "mpp_sdio0";
  240. marvell,function = "gpio";
  241. };
  242. pmx_sdio1: pmx-sdio1 {
  243. marvell,pins = "mpp_sdio1";
  244. marvell,function = "sdio1";
  245. };
  246. pmx_sdio1_gpio: pmx-sdio1-gpio {
  247. marvell,pins = "mpp_sdio1";
  248. marvell,function = "gpio";
  249. };
  250. pmx_audio1_gpio: pmx-audio1-gpio {
  251. marvell,pins = "mpp_audio1";
  252. marvell,function = "gpio";
  253. };
  254. pmx_spi0: pmx-spi0 {
  255. marvell,pins = "mpp_spi0";
  256. marvell,function = "spi0";
  257. };
  258. pmx_spi0_gpio: pmx-spi0-gpio {
  259. marvell,pins = "mpp_spi0";
  260. marvell,function = "gpio";
  261. };
  262. pmx_uart1: pmx-uart1 {
  263. marvell,pins = "mpp_uart1";
  264. marvell,function = "uart1";
  265. };
  266. pmx_uart1_gpio: pmx-uart1-gpio {
  267. marvell,pins = "mpp_uart1";
  268. marvell,function = "gpio";
  269. };
  270. pmx_nand: pmx-nand {
  271. marvell,pins = "mpp_nand";
  272. marvell,function = "nand";
  273. };
  274. pmx_nand_gpo: pmx-nand-gpo {
  275. marvell,pins = "mpp_nand";
  276. marvell,function = "gpo";
  277. };
  278. };
  279. spi0: spi-ctrl@10600 {
  280. compatible = "marvell,orion-spi";
  281. #address-cells = <1>;
  282. #size-cells = <0>;
  283. cell-index = <0>;
  284. interrupts = <6>;
  285. reg = <0x10600 0x28>;
  286. clocks = <&core_clk 0>;
  287. pinctrl-0 = <&pmx_spi0>;
  288. pinctrl-names = "default";
  289. status = "disabled";
  290. };
  291. spi1: spi-ctrl@14600 {
  292. compatible = "marvell,orion-spi";
  293. #address-cells = <1>;
  294. #size-cells = <0>;
  295. cell-index = <1>;
  296. interrupts = <5>;
  297. reg = <0x14600 0x28>;
  298. clocks = <&core_clk 0>;
  299. status = "disabled";
  300. };
  301. i2c0: i2c-ctrl@11000 {
  302. compatible = "marvell,mv64xxx-i2c";
  303. reg = <0x11000 0x20>;
  304. #address-cells = <1>;
  305. #size-cells = <0>;
  306. interrupts = <11>;
  307. clock-frequency = <400000>;
  308. timeout-ms = <1000>;
  309. clocks = <&core_clk 0>;
  310. status = "disabled";
  311. };
  312. ehci0: usb-host@50000 {
  313. compatible = "marvell,orion-ehci";
  314. reg = <0x50000 0x1000>;
  315. interrupts = <24>;
  316. clocks = <&gate_clk 0>;
  317. status = "okay";
  318. };
  319. ehci1: usb-host@51000 {
  320. compatible = "marvell,orion-ehci";
  321. reg = <0x51000 0x1000>;
  322. interrupts = <25>;
  323. clocks = <&gate_clk 1>;
  324. status = "okay";
  325. };
  326. sdio0: sdio-host@92000 {
  327. compatible = "marvell,dove-sdhci";
  328. reg = <0x92000 0x100>;
  329. interrupts = <35>, <37>;
  330. clocks = <&gate_clk 8>;
  331. pinctrl-0 = <&pmx_sdio0>;
  332. pinctrl-names = "default";
  333. status = "disabled";
  334. };
  335. sdio1: sdio-host@90000 {
  336. compatible = "marvell,dove-sdhci";
  337. reg = <0x90000 0x100>;
  338. interrupts = <36>, <38>;
  339. clocks = <&gate_clk 9>;
  340. pinctrl-0 = <&pmx_sdio1>;
  341. pinctrl-names = "default";
  342. status = "disabled";
  343. };
  344. sata0: sata-host@a0000 {
  345. compatible = "marvell,orion-sata";
  346. reg = <0xa0000 0x2400>;
  347. interrupts = <62>;
  348. clocks = <&gate_clk 3>;
  349. nr-ports = <1>;
  350. status = "disabled";
  351. };
  352. rtc: real-time-clock@d8500 {
  353. compatible = "marvell,orion-rtc";
  354. reg = <0xd8500 0x20>;
  355. };
  356. crypto: crypto-engine@30000 {
  357. compatible = "marvell,orion-crypto";
  358. reg = <0x30000 0x10000>,
  359. <0xc8000000 0x800>;
  360. reg-names = "regs", "sram";
  361. interrupts = <31>;
  362. clocks = <&gate_clk 15>;
  363. status = "okay";
  364. };
  365. xor0: dma-engine@60800 {
  366. compatible = "marvell,orion-xor";
  367. reg = <0x60800 0x100
  368. 0x60a00 0x100>;
  369. clocks = <&gate_clk 23>;
  370. status = "okay";
  371. channel0 {
  372. interrupts = <39>;
  373. dmacap,memcpy;
  374. dmacap,xor;
  375. };
  376. channel1 {
  377. interrupts = <40>;
  378. dmacap,memset;
  379. dmacap,memcpy;
  380. dmacap,xor;
  381. };
  382. };
  383. xor1: dma-engine@60900 {
  384. compatible = "marvell,orion-xor";
  385. reg = <0x60900 0x100
  386. 0x60b00 0x100>;
  387. clocks = <&gate_clk 24>;
  388. status = "okay";
  389. channel0 {
  390. interrupts = <42>;
  391. dmacap,memcpy;
  392. dmacap,xor;
  393. };
  394. channel1 {
  395. interrupts = <43>;
  396. dmacap,memset;
  397. dmacap,memcpy;
  398. dmacap,xor;
  399. };
  400. };
  401. mdio: mdio-bus@72004 {
  402. compatible = "marvell,orion-mdio";
  403. #address-cells = <1>;
  404. #size-cells = <0>;
  405. reg = <0x72004 0x84>;
  406. interrupts = <30>;
  407. clocks = <&gate_clk 2>;
  408. status = "disabled";
  409. ethphy: ethernet-phy {
  410. device-type = "ethernet-phy";
  411. /* set phy address in board file */
  412. };
  413. };
  414. eth: ethernet-controller@72000 {
  415. compatible = "marvell,orion-eth";
  416. #address-cells = <1>;
  417. #size-cells = <0>;
  418. reg = <0x72000 0x4000>;
  419. clocks = <&gate_clk 2>;
  420. marvell,tx-checksum-limit = <1600>;
  421. status = "disabled";
  422. ethernet-port@0 {
  423. device_type = "network";
  424. compatible = "marvell,orion-eth-port";
  425. reg = <0>;
  426. interrupts = <29>;
  427. /* overwrite MAC address in bootloader */
  428. local-mac-address = [00 00 00 00 00 00];
  429. phy-handle = <&ethphy>;
  430. };
  431. };
  432. };
  433. };