armada-xp-axpwifiap.dts 3.4 KB

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  1. /*
  2. * Device Tree file for Marvell RD-AXPWiFiAP.
  3. *
  4. * Note: this board is shipped with a new generation boot loader that
  5. * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
  6. * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
  7. * used.
  8. *
  9. * Copyright (C) 2013 Marvell
  10. *
  11. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  12. *
  13. * This file is licensed under the terms of the GNU General Public
  14. * License version 2. This program is licensed "as is" without any
  15. * warranty of any kind, whether express or implied.
  16. */
  17. /dts-v1/;
  18. #include "armada-xp-mv78230.dtsi"
  19. / {
  20. model = "Marvell RD-AXPWiFiAP";
  21. compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
  22. chosen {
  23. bootargs = "console=ttyS0,115200 earlyprintk";
  24. };
  25. memory {
  26. device_type = "memory";
  27. reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
  28. };
  29. soc {
  30. ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  31. MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
  32. pcie-controller {
  33. status = "okay";
  34. /* First mini-PCIe port */
  35. pcie@1,0 {
  36. /* Port 0, Lane 0 */
  37. status = "okay";
  38. };
  39. /* Second mini-PCIe port */
  40. pcie@2,0 {
  41. /* Port 0, Lane 1 */
  42. status = "okay";
  43. };
  44. /* Renesas uPD720202 USB 3.0 controller */
  45. pcie@3,0 {
  46. /* Port 0, Lane 3 */
  47. status = "okay";
  48. };
  49. };
  50. internal-regs {
  51. pinctrl {
  52. pinctrl-0 = <&pmx_phy_int>;
  53. pinctrl-names = "default";
  54. pmx_ge0: pmx-ge0 {
  55. marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
  56. "mpp4", "mpp5", "mpp6", "mpp7",
  57. "mpp8", "mpp9", "mpp10", "mpp11";
  58. marvell,function = "ge0";
  59. };
  60. pmx_ge1: pmx-ge1 {
  61. marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
  62. "mpp16", "mpp17", "mpp18", "mpp19",
  63. "mpp20", "mpp21", "mpp22", "mpp23";
  64. marvell,function = "ge1";
  65. };
  66. pmx_keys: pmx-keys {
  67. marvell,pins = "mpp33";
  68. marvell,function = "gpio";
  69. };
  70. pmx_spi: pmx-spi {
  71. marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
  72. marvell,function = "spi";
  73. };
  74. pmx_phy_int: pmx-phy-int {
  75. marvell,pins = "mpp32";
  76. marvell,function = "gpio";
  77. };
  78. };
  79. serial@12000 {
  80. clock-frequency = <250000000>;
  81. status = "okay";
  82. };
  83. serial@12100 {
  84. clock-frequency = <250000000>;
  85. status = "okay";
  86. };
  87. sata@a0000 {
  88. nr-ports = <1>;
  89. status = "okay";
  90. };
  91. mdio {
  92. phy0: ethernet-phy@0 {
  93. reg = <0>;
  94. };
  95. phy1: ethernet-phy@1 {
  96. reg = <1>;
  97. };
  98. };
  99. ethernet@70000 {
  100. pinctrl-0 = <&pmx_ge0>;
  101. pinctrl-names = "default";
  102. status = "okay";
  103. phy = <&phy0>;
  104. phy-mode = "rgmii-id";
  105. };
  106. ethernet@74000 {
  107. pinctrl-0 = <&pmx_ge1>;
  108. pinctrl-names = "default";
  109. status = "okay";
  110. phy = <&phy1>;
  111. phy-mode = "rgmii-id";
  112. };
  113. spi0: spi@10600 {
  114. status = "okay";
  115. pinctrl-0 = <&pmx_spi>;
  116. pinctrl-names = "default";
  117. spi-flash@0 {
  118. #address-cells = <1>;
  119. #size-cells = <1>;
  120. compatible = "n25q128a13";
  121. reg = <0>; /* Chip select 0 */
  122. spi-max-frequency = <108000000>;
  123. };
  124. };
  125. };
  126. };
  127. gpio_keys {
  128. compatible = "gpio-keys";
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. pinctrl-0 = <&pmx_keys>;
  132. pinctrl-names = "default";
  133. button@1 {
  134. label = "Factory Reset Button";
  135. linux,code = <141>; /* KEY_SETUP */
  136. gpios = <&gpio1 1 1>;
  137. };
  138. };
  139. };