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nvidia,tegra20-i2c.txt

nvidia,tegra20-i2c.txt 2.7 KB
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  1. NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
    2. 

  2. 

  3. Required properties:
    4. 

  4. - compatible : should be:
    5. 

  5. 	"nvidia,tegra114-i2c"
    6. 

  6. 	"nvidia,tegra30-i2c"
    7. 

  7. 	"nvidia,tegra20-i2c"
    8. 

  8. 	"nvidia,tegra20-i2c-dvc"
    9. 

  9.   Details of compatible are as follows:
    10. 

  10.   nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
    11. 

  11. 	controller. This only support master mode of I2C communication. Register
    12. 

  12. 	interface/offset and interrupts handling are different than generic I2C
    13. 

  13. 	controller. Driver of DVC I2C controller is only compatible with
    14. 

  14. 	"nvidia,tegra20-i2c-dvc".
    15. 

  15.   nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
    16. 

  16. 	master and slave mode of I2C communication. The i2c-tegra driver only
    17. 

  17. 	support master mode of I2C communication. Driver of I2C controller is
    18. 

  18. 	only compatible with "nvidia,tegra20-i2c".
    19. 

  19.   nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
    20. 

  20. 	very much similar to Tegra20 I2C controller with additional feature:
    21. 

  21. 	Continue Transfer Support. This feature helps to implement M_NO_START
    22. 

  22. 	as per I2C core API transfer flags. Driver of I2C controller is
    23. 

  23. 	compatible with "nvidia,tegra30-i2c" to enable the continue transfer
    24. 

  24. 	support. This is also compatible with "nvidia,tegra20-i2c" without
    25. 

  25. 	continue transfer support.
    26. 

  26.   nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is
    27. 

  27. 	very much similar to Tegra30 I2C controller with some hardware
    28. 

  28. 	modification:
    29. 

  29. 	 - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and
    30. 

  30. 	   fast-clk. Tegra114 has only one clock source called as div-clk and
    31. 

  31. 	   hence clock mechanism is changed in I2C controller.
    32. 

  32. 	 - Tegra30/Tegra20 I2C controller has enabled per packet transfer by
    33. 

  33. 	   default and there is no way to disable it. Tegra114 has this
    34. 

  34. 	   interrupt disable by default and SW need to enable explicitly.
    35. 

  35. 	Due to above changes, Tegra114 I2C driver makes incompatible with
    36. 

  36. 	previous hardware driver. Hence, tegra114 I2C controller is compatible
    37. 

  37. 	with "nvidia,tegra114-i2c".
    38. 

  38. - reg: Should contain I2C controller registers physical address and length.
    39. 

  39. - interrupts: Should contain I2C controller interrupts.
    40. 

  40. - address-cells: Address cells for I2C device address.
    41. 

  41. - size-cells: Size of the I2C device address.
    42. 

  42. - clocks: Clock ID as per
    43. 

  43. 		Documentation/devicetree/bindings/clock/tegra<chip-id>.txt
    44. 

  44. 	for I2C controller.
    45. 

  45. - clock-names: Name of the clock:
    46. 

  46. 	Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".
    47. 

  47. 	Tegra114 I2C controller: "div-clk".
    48. 

  48. 

  49. Example:
    50. 

  50. 

  51. 	i2c@7000c000 {
    52. 

  52. 		compatible = "nvidia,tegra20-i2c";
    53. 

  53. 		reg = <0x7000c000 0x100>;
    54. 

  54. 		interrupts = <0 38 0x04>;
    55. 

  55. 		#address-cells = <1>;
    56. 

  56. 		#size-cells = <0>;
    57. 

  57. 		clocks = <&tegra_car 12>, <&tegra_car 124>;
    58. 

  58. 		clock-names = "div-clk", "fast-clk";
    59. 

  59. 		status = "disabled";
    60. 

  60. 	};
    61.