uhci-q.c 42 KB

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  1. /*
  2. * Universal Host Controller Interface driver for USB.
  3. *
  4. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  5. *
  6. * (C) Copyright 1999 Linus Torvalds
  7. * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
  8. * (C) Copyright 1999 Randy Dunlap
  9. * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10. * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11. * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12. * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13. * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14. * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15. * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16. * (C) Copyright 2004-2006 Alan Stern, stern@rowland.harvard.edu
  17. */
  18. /*
  19. * Technically, updating td->status here is a race, but it's not really a
  20. * problem. The worst that can happen is that we set the IOC bit again
  21. * generating a spurious interrupt. We could fix this by creating another
  22. * QH and leaving the IOC bit always set, but then we would have to play
  23. * games with the FSBR code to make sure we get the correct order in all
  24. * the cases. I don't think it's worth the effort
  25. */
  26. static void uhci_set_next_interrupt(struct uhci_hcd *uhci)
  27. {
  28. if (uhci->is_stopped)
  29. mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
  30. uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
  31. }
  32. static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
  33. {
  34. uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
  35. }
  36. /*
  37. * Full-Speed Bandwidth Reclamation (FSBR).
  38. * We turn on FSBR whenever a queue that wants it is advancing,
  39. * and leave it on for a short time thereafter.
  40. */
  41. static void uhci_fsbr_on(struct uhci_hcd *uhci)
  42. {
  43. uhci->fsbr_is_on = 1;
  44. uhci->skel_term_qh->link = LINK_TO_QH(uhci->skel_fs_control_qh);
  45. }
  46. static void uhci_fsbr_off(struct uhci_hcd *uhci)
  47. {
  48. uhci->fsbr_is_on = 0;
  49. uhci->skel_term_qh->link = UHCI_PTR_TERM;
  50. }
  51. static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  52. {
  53. struct urb_priv *urbp = urb->hcpriv;
  54. if (!(urb->transfer_flags & URB_NO_FSBR))
  55. urbp->fsbr = 1;
  56. }
  57. static void uhci_urbp_wants_fsbr(struct uhci_hcd *uhci, struct urb_priv *urbp)
  58. {
  59. if (urbp->fsbr) {
  60. uhci->fsbr_is_wanted = 1;
  61. if (!uhci->fsbr_is_on)
  62. uhci_fsbr_on(uhci);
  63. else if (uhci->fsbr_expiring) {
  64. uhci->fsbr_expiring = 0;
  65. del_timer(&uhci->fsbr_timer);
  66. }
  67. }
  68. }
  69. static void uhci_fsbr_timeout(unsigned long _uhci)
  70. {
  71. struct uhci_hcd *uhci = (struct uhci_hcd *) _uhci;
  72. unsigned long flags;
  73. spin_lock_irqsave(&uhci->lock, flags);
  74. if (uhci->fsbr_expiring) {
  75. uhci->fsbr_expiring = 0;
  76. uhci_fsbr_off(uhci);
  77. }
  78. spin_unlock_irqrestore(&uhci->lock, flags);
  79. }
  80. static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci)
  81. {
  82. dma_addr_t dma_handle;
  83. struct uhci_td *td;
  84. td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
  85. if (!td)
  86. return NULL;
  87. td->dma_handle = dma_handle;
  88. td->frame = -1;
  89. INIT_LIST_HEAD(&td->list);
  90. INIT_LIST_HEAD(&td->fl_list);
  91. return td;
  92. }
  93. static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
  94. {
  95. if (!list_empty(&td->list))
  96. dev_warn(uhci_dev(uhci), "td %p still in list!\n", td);
  97. if (!list_empty(&td->fl_list))
  98. dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td);
  99. dma_pool_free(uhci->td_pool, td, td->dma_handle);
  100. }
  101. static inline void uhci_fill_td(struct uhci_td *td, u32 status,
  102. u32 token, u32 buffer)
  103. {
  104. td->status = cpu_to_le32(status);
  105. td->token = cpu_to_le32(token);
  106. td->buffer = cpu_to_le32(buffer);
  107. }
  108. static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp)
  109. {
  110. list_add_tail(&td->list, &urbp->td_list);
  111. }
  112. static void uhci_remove_td_from_urbp(struct uhci_td *td)
  113. {
  114. list_del_init(&td->list);
  115. }
  116. /*
  117. * We insert Isochronous URBs directly into the frame list at the beginning
  118. */
  119. static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci,
  120. struct uhci_td *td, unsigned framenum)
  121. {
  122. framenum &= (UHCI_NUMFRAMES - 1);
  123. td->frame = framenum;
  124. /* Is there a TD already mapped there? */
  125. if (uhci->frame_cpu[framenum]) {
  126. struct uhci_td *ftd, *ltd;
  127. ftd = uhci->frame_cpu[framenum];
  128. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  129. list_add_tail(&td->fl_list, &ftd->fl_list);
  130. td->link = ltd->link;
  131. wmb();
  132. ltd->link = LINK_TO_TD(td);
  133. } else {
  134. td->link = uhci->frame[framenum];
  135. wmb();
  136. uhci->frame[framenum] = LINK_TO_TD(td);
  137. uhci->frame_cpu[framenum] = td;
  138. }
  139. }
  140. static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci,
  141. struct uhci_td *td)
  142. {
  143. /* If it's not inserted, don't remove it */
  144. if (td->frame == -1) {
  145. WARN_ON(!list_empty(&td->fl_list));
  146. return;
  147. }
  148. if (uhci->frame_cpu[td->frame] == td) {
  149. if (list_empty(&td->fl_list)) {
  150. uhci->frame[td->frame] = td->link;
  151. uhci->frame_cpu[td->frame] = NULL;
  152. } else {
  153. struct uhci_td *ntd;
  154. ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
  155. uhci->frame[td->frame] = LINK_TO_TD(ntd);
  156. uhci->frame_cpu[td->frame] = ntd;
  157. }
  158. } else {
  159. struct uhci_td *ptd;
  160. ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
  161. ptd->link = td->link;
  162. }
  163. list_del_init(&td->fl_list);
  164. td->frame = -1;
  165. }
  166. static inline void uhci_remove_tds_from_frame(struct uhci_hcd *uhci,
  167. unsigned int framenum)
  168. {
  169. struct uhci_td *ftd, *ltd;
  170. framenum &= (UHCI_NUMFRAMES - 1);
  171. ftd = uhci->frame_cpu[framenum];
  172. if (ftd) {
  173. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  174. uhci->frame[framenum] = ltd->link;
  175. uhci->frame_cpu[framenum] = NULL;
  176. while (!list_empty(&ftd->fl_list))
  177. list_del_init(ftd->fl_list.prev);
  178. }
  179. }
  180. /*
  181. * Remove all the TDs for an Isochronous URB from the frame list
  182. */
  183. static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb)
  184. {
  185. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  186. struct uhci_td *td;
  187. list_for_each_entry(td, &urbp->td_list, list)
  188. uhci_remove_td_from_frame_list(uhci, td);
  189. }
  190. static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci,
  191. struct usb_device *udev, struct usb_host_endpoint *hep)
  192. {
  193. dma_addr_t dma_handle;
  194. struct uhci_qh *qh;
  195. qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
  196. if (!qh)
  197. return NULL;
  198. memset(qh, 0, sizeof(*qh));
  199. qh->dma_handle = dma_handle;
  200. qh->element = UHCI_PTR_TERM;
  201. qh->link = UHCI_PTR_TERM;
  202. INIT_LIST_HEAD(&qh->queue);
  203. INIT_LIST_HEAD(&qh->node);
  204. if (udev) { /* Normal QH */
  205. qh->type = hep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  206. if (qh->type != USB_ENDPOINT_XFER_ISOC) {
  207. qh->dummy_td = uhci_alloc_td(uhci);
  208. if (!qh->dummy_td) {
  209. dma_pool_free(uhci->qh_pool, qh, dma_handle);
  210. return NULL;
  211. }
  212. }
  213. qh->state = QH_STATE_IDLE;
  214. qh->hep = hep;
  215. qh->udev = udev;
  216. hep->hcpriv = qh;
  217. if (qh->type == USB_ENDPOINT_XFER_INT ||
  218. qh->type == USB_ENDPOINT_XFER_ISOC)
  219. qh->load = usb_calc_bus_time(udev->speed,
  220. usb_endpoint_dir_in(&hep->desc),
  221. qh->type == USB_ENDPOINT_XFER_ISOC,
  222. le16_to_cpu(hep->desc.wMaxPacketSize))
  223. / 1000 + 1;
  224. } else { /* Skeleton QH */
  225. qh->state = QH_STATE_ACTIVE;
  226. qh->type = -1;
  227. }
  228. return qh;
  229. }
  230. static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  231. {
  232. WARN_ON(qh->state != QH_STATE_IDLE && qh->udev);
  233. if (!list_empty(&qh->queue))
  234. dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh);
  235. list_del(&qh->node);
  236. if (qh->udev) {
  237. qh->hep->hcpriv = NULL;
  238. if (qh->dummy_td)
  239. uhci_free_td(uhci, qh->dummy_td);
  240. }
  241. dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
  242. }
  243. /*
  244. * When a queue is stopped and a dequeued URB is given back, adjust
  245. * the previous TD link (if the URB isn't first on the queue) or
  246. * save its toggle value (if it is first and is currently executing).
  247. *
  248. * Returns 0 if the URB should not yet be given back, 1 otherwise.
  249. */
  250. static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh,
  251. struct urb *urb)
  252. {
  253. struct urb_priv *urbp = urb->hcpriv;
  254. struct uhci_td *td;
  255. int ret = 1;
  256. /* Isochronous pipes don't use toggles and their TD link pointers
  257. * get adjusted during uhci_urb_dequeue(). But since their queues
  258. * cannot truly be stopped, we have to watch out for dequeues
  259. * occurring after the nominal unlink frame. */
  260. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  261. ret = (uhci->frame_number + uhci->is_stopped !=
  262. qh->unlink_frame);
  263. goto done;
  264. }
  265. /* If the URB isn't first on its queue, adjust the link pointer
  266. * of the last TD in the previous URB. The toggle doesn't need
  267. * to be saved since this URB can't be executing yet. */
  268. if (qh->queue.next != &urbp->node) {
  269. struct urb_priv *purbp;
  270. struct uhci_td *ptd;
  271. purbp = list_entry(urbp->node.prev, struct urb_priv, node);
  272. WARN_ON(list_empty(&purbp->td_list));
  273. ptd = list_entry(purbp->td_list.prev, struct uhci_td,
  274. list);
  275. td = list_entry(urbp->td_list.prev, struct uhci_td,
  276. list);
  277. ptd->link = td->link;
  278. goto done;
  279. }
  280. /* If the QH element pointer is UHCI_PTR_TERM then then currently
  281. * executing URB has already been unlinked, so this one isn't it. */
  282. if (qh_element(qh) == UHCI_PTR_TERM)
  283. goto done;
  284. qh->element = UHCI_PTR_TERM;
  285. /* Control pipes don't have to worry about toggles */
  286. if (qh->type == USB_ENDPOINT_XFER_CONTROL)
  287. goto done;
  288. /* Save the next toggle value */
  289. WARN_ON(list_empty(&urbp->td_list));
  290. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  291. qh->needs_fixup = 1;
  292. qh->initial_toggle = uhci_toggle(td_token(td));
  293. done:
  294. return ret;
  295. }
  296. /*
  297. * Fix up the data toggles for URBs in a queue, when one of them
  298. * terminates early (short transfer, error, or dequeued).
  299. */
  300. static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first)
  301. {
  302. struct urb_priv *urbp = NULL;
  303. struct uhci_td *td;
  304. unsigned int toggle = qh->initial_toggle;
  305. unsigned int pipe;
  306. /* Fixups for a short transfer start with the second URB in the
  307. * queue (the short URB is the first). */
  308. if (skip_first)
  309. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  310. /* When starting with the first URB, if the QH element pointer is
  311. * still valid then we know the URB's toggles are okay. */
  312. else if (qh_element(qh) != UHCI_PTR_TERM)
  313. toggle = 2;
  314. /* Fix up the toggle for the URBs in the queue. Normally this
  315. * loop won't run more than once: When an error or short transfer
  316. * occurs, the queue usually gets emptied. */
  317. urbp = list_prepare_entry(urbp, &qh->queue, node);
  318. list_for_each_entry_continue(urbp, &qh->queue, node) {
  319. /* If the first TD has the right toggle value, we don't
  320. * need to change any toggles in this URB */
  321. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  322. if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) {
  323. td = list_entry(urbp->td_list.prev, struct uhci_td,
  324. list);
  325. toggle = uhci_toggle(td_token(td)) ^ 1;
  326. /* Otherwise all the toggles in the URB have to be switched */
  327. } else {
  328. list_for_each_entry(td, &urbp->td_list, list) {
  329. td->token ^= __constant_cpu_to_le32(
  330. TD_TOKEN_TOGGLE);
  331. toggle ^= 1;
  332. }
  333. }
  334. }
  335. wmb();
  336. pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe;
  337. usb_settoggle(qh->udev, usb_pipeendpoint(pipe),
  338. usb_pipeout(pipe), toggle);
  339. qh->needs_fixup = 0;
  340. }
  341. /*
  342. * Put a QH on the schedule in both hardware and software
  343. */
  344. static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  345. {
  346. struct uhci_qh *pqh;
  347. WARN_ON(list_empty(&qh->queue));
  348. /* Set the element pointer if it isn't set already.
  349. * This isn't needed for Isochronous queues, but it doesn't hurt. */
  350. if (qh_element(qh) == UHCI_PTR_TERM) {
  351. struct urb_priv *urbp = list_entry(qh->queue.next,
  352. struct urb_priv, node);
  353. struct uhci_td *td = list_entry(urbp->td_list.next,
  354. struct uhci_td, list);
  355. qh->element = LINK_TO_TD(td);
  356. }
  357. /* Treat the queue as if it has just advanced */
  358. qh->wait_expired = 0;
  359. qh->advance_jiffies = jiffies;
  360. if (qh->state == QH_STATE_ACTIVE)
  361. return;
  362. qh->state = QH_STATE_ACTIVE;
  363. /* Move the QH from its old list to the end of the appropriate
  364. * skeleton's list */
  365. if (qh == uhci->next_qh)
  366. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  367. node);
  368. list_move_tail(&qh->node, &qh->skel->node);
  369. /* Link it into the schedule */
  370. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  371. qh->link = pqh->link;
  372. wmb();
  373. pqh->link = LINK_TO_QH(qh);
  374. }
  375. /*
  376. * Take a QH off the hardware schedule
  377. */
  378. static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  379. {
  380. struct uhci_qh *pqh;
  381. if (qh->state == QH_STATE_UNLINKING)
  382. return;
  383. WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev);
  384. qh->state = QH_STATE_UNLINKING;
  385. /* Unlink the QH from the schedule and record when we did it */
  386. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  387. pqh->link = qh->link;
  388. mb();
  389. uhci_get_current_frame_number(uhci);
  390. qh->unlink_frame = uhci->frame_number;
  391. /* Force an interrupt so we know when the QH is fully unlinked */
  392. if (list_empty(&uhci->skel_unlink_qh->node))
  393. uhci_set_next_interrupt(uhci);
  394. /* Move the QH from its old list to the end of the unlinking list */
  395. if (qh == uhci->next_qh)
  396. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  397. node);
  398. list_move_tail(&qh->node, &uhci->skel_unlink_qh->node);
  399. }
  400. /*
  401. * When we and the controller are through with a QH, it becomes IDLE.
  402. * This happens when a QH has been off the schedule (on the unlinking
  403. * list) for more than one frame, or when an error occurs while adding
  404. * the first URB onto a new QH.
  405. */
  406. static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh)
  407. {
  408. WARN_ON(qh->state == QH_STATE_ACTIVE);
  409. if (qh == uhci->next_qh)
  410. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  411. node);
  412. list_move(&qh->node, &uhci->idle_qh_list);
  413. qh->state = QH_STATE_IDLE;
  414. /* Now that the QH is idle, its post_td isn't being used */
  415. if (qh->post_td) {
  416. uhci_free_td(uhci, qh->post_td);
  417. qh->post_td = NULL;
  418. }
  419. /* If anyone is waiting for a QH to become idle, wake them up */
  420. if (uhci->num_waiting)
  421. wake_up_all(&uhci->waitqh);
  422. }
  423. /*
  424. * Find the highest existing bandwidth load for a given phase and period.
  425. */
  426. static int uhci_highest_load(struct uhci_hcd *uhci, int phase, int period)
  427. {
  428. int highest_load = uhci->load[phase];
  429. for (phase += period; phase < MAX_PHASE; phase += period)
  430. highest_load = max_t(int, highest_load, uhci->load[phase]);
  431. return highest_load;
  432. }
  433. /*
  434. * Set qh->phase to the optimal phase for a periodic transfer and
  435. * check whether the bandwidth requirement is acceptable.
  436. */
  437. static int uhci_check_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  438. {
  439. int minimax_load;
  440. /* Find the optimal phase (unless it is already set) and get
  441. * its load value. */
  442. if (qh->phase >= 0)
  443. minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
  444. else {
  445. int phase, load;
  446. int max_phase = min_t(int, MAX_PHASE, qh->period);
  447. qh->phase = 0;
  448. minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
  449. for (phase = 1; phase < max_phase; ++phase) {
  450. load = uhci_highest_load(uhci, phase, qh->period);
  451. if (load < minimax_load) {
  452. minimax_load = load;
  453. qh->phase = phase;
  454. }
  455. }
  456. }
  457. /* Maximum allowable periodic bandwidth is 90%, or 900 us per frame */
  458. if (minimax_load + qh->load > 900) {
  459. dev_dbg(uhci_dev(uhci), "bandwidth allocation failed: "
  460. "period %d, phase %d, %d + %d us\n",
  461. qh->period, qh->phase, minimax_load, qh->load);
  462. return -ENOSPC;
  463. }
  464. return 0;
  465. }
  466. /*
  467. * Reserve a periodic QH's bandwidth in the schedule
  468. */
  469. static void uhci_reserve_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  470. {
  471. int i;
  472. int load = qh->load;
  473. char *p = "??";
  474. for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
  475. uhci->load[i] += load;
  476. uhci->total_load += load;
  477. }
  478. uhci_to_hcd(uhci)->self.bandwidth_allocated =
  479. uhci->total_load / MAX_PHASE;
  480. switch (qh->type) {
  481. case USB_ENDPOINT_XFER_INT:
  482. ++uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
  483. p = "INT";
  484. break;
  485. case USB_ENDPOINT_XFER_ISOC:
  486. ++uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
  487. p = "ISO";
  488. break;
  489. }
  490. qh->bandwidth_reserved = 1;
  491. dev_dbg(uhci_dev(uhci),
  492. "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
  493. "reserve", qh->udev->devnum,
  494. qh->hep->desc.bEndpointAddress, p,
  495. qh->period, qh->phase, load);
  496. }
  497. /*
  498. * Release a periodic QH's bandwidth reservation
  499. */
  500. static void uhci_release_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  501. {
  502. int i;
  503. int load = qh->load;
  504. char *p = "??";
  505. for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
  506. uhci->load[i] -= load;
  507. uhci->total_load -= load;
  508. }
  509. uhci_to_hcd(uhci)->self.bandwidth_allocated =
  510. uhci->total_load / MAX_PHASE;
  511. switch (qh->type) {
  512. case USB_ENDPOINT_XFER_INT:
  513. --uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
  514. p = "INT";
  515. break;
  516. case USB_ENDPOINT_XFER_ISOC:
  517. --uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
  518. p = "ISO";
  519. break;
  520. }
  521. qh->bandwidth_reserved = 0;
  522. dev_dbg(uhci_dev(uhci),
  523. "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
  524. "release", qh->udev->devnum,
  525. qh->hep->desc.bEndpointAddress, p,
  526. qh->period, qh->phase, load);
  527. }
  528. static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci,
  529. struct urb *urb)
  530. {
  531. struct urb_priv *urbp;
  532. urbp = kmem_cache_zalloc(uhci_up_cachep, GFP_ATOMIC);
  533. if (!urbp)
  534. return NULL;
  535. urbp->urb = urb;
  536. urb->hcpriv = urbp;
  537. INIT_LIST_HEAD(&urbp->node);
  538. INIT_LIST_HEAD(&urbp->td_list);
  539. return urbp;
  540. }
  541. static void uhci_free_urb_priv(struct uhci_hcd *uhci,
  542. struct urb_priv *urbp)
  543. {
  544. struct uhci_td *td, *tmp;
  545. if (!list_empty(&urbp->node))
  546. dev_warn(uhci_dev(uhci), "urb %p still on QH's list!\n",
  547. urbp->urb);
  548. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  549. uhci_remove_td_from_urbp(td);
  550. uhci_free_td(uhci, td);
  551. }
  552. urbp->urb->hcpriv = NULL;
  553. kmem_cache_free(uhci_up_cachep, urbp);
  554. }
  555. /*
  556. * Map status to standard result codes
  557. *
  558. * <status> is (td_status(td) & 0xF60000), a.k.a.
  559. * uhci_status_bits(td_status(td)).
  560. * Note: <status> does not include the TD_CTRL_NAK bit.
  561. * <dir_out> is True for output TDs and False for input TDs.
  562. */
  563. static int uhci_map_status(int status, int dir_out)
  564. {
  565. if (!status)
  566. return 0;
  567. if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
  568. return -EPROTO;
  569. if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
  570. if (dir_out)
  571. return -EPROTO;
  572. else
  573. return -EILSEQ;
  574. }
  575. if (status & TD_CTRL_BABBLE) /* Babble */
  576. return -EOVERFLOW;
  577. if (status & TD_CTRL_DBUFERR) /* Buffer error */
  578. return -ENOSR;
  579. if (status & TD_CTRL_STALLED) /* Stalled */
  580. return -EPIPE;
  581. return 0;
  582. }
  583. /*
  584. * Control transfers
  585. */
  586. static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb,
  587. struct uhci_qh *qh)
  588. {
  589. struct uhci_td *td;
  590. unsigned long destination, status;
  591. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  592. int len = urb->transfer_buffer_length;
  593. dma_addr_t data = urb->transfer_dma;
  594. __le32 *plink;
  595. struct urb_priv *urbp = urb->hcpriv;
  596. /* The "pipe" thing contains the destination in bits 8--18 */
  597. destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
  598. /* 3 errors, dummy TD remains inactive */
  599. status = uhci_maxerr(3);
  600. if (urb->dev->speed == USB_SPEED_LOW)
  601. status |= TD_CTRL_LS;
  602. /*
  603. * Build the TD for the control request setup packet
  604. */
  605. td = qh->dummy_td;
  606. uhci_add_td_to_urbp(td, urbp);
  607. uhci_fill_td(td, status, destination | uhci_explen(8),
  608. urb->setup_dma);
  609. plink = &td->link;
  610. status |= TD_CTRL_ACTIVE;
  611. /*
  612. * If direction is "send", change the packet ID from SETUP (0x2D)
  613. * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
  614. * set Short Packet Detect (SPD) for all data packets.
  615. */
  616. if (usb_pipeout(urb->pipe))
  617. destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
  618. else {
  619. destination ^= (USB_PID_SETUP ^ USB_PID_IN);
  620. status |= TD_CTRL_SPD;
  621. }
  622. /*
  623. * Build the DATA TDs
  624. */
  625. while (len > 0) {
  626. int pktsze = min(len, maxsze);
  627. td = uhci_alloc_td(uhci);
  628. if (!td)
  629. goto nomem;
  630. *plink = LINK_TO_TD(td);
  631. /* Alternate Data0/1 (start with Data1) */
  632. destination ^= TD_TOKEN_TOGGLE;
  633. uhci_add_td_to_urbp(td, urbp);
  634. uhci_fill_td(td, status, destination | uhci_explen(pktsze),
  635. data);
  636. plink = &td->link;
  637. data += pktsze;
  638. len -= pktsze;
  639. }
  640. /*
  641. * Build the final TD for control status
  642. */
  643. td = uhci_alloc_td(uhci);
  644. if (!td)
  645. goto nomem;
  646. *plink = LINK_TO_TD(td);
  647. /*
  648. * It's IN if the pipe is an output pipe or we're not expecting
  649. * data back.
  650. */
  651. destination &= ~TD_TOKEN_PID_MASK;
  652. if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length)
  653. destination |= USB_PID_IN;
  654. else
  655. destination |= USB_PID_OUT;
  656. destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
  657. status &= ~TD_CTRL_SPD;
  658. uhci_add_td_to_urbp(td, urbp);
  659. uhci_fill_td(td, status | TD_CTRL_IOC,
  660. destination | uhci_explen(0), 0);
  661. plink = &td->link;
  662. /*
  663. * Build the new dummy TD and activate the old one
  664. */
  665. td = uhci_alloc_td(uhci);
  666. if (!td)
  667. goto nomem;
  668. *plink = LINK_TO_TD(td);
  669. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  670. wmb();
  671. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  672. qh->dummy_td = td;
  673. /* Low-speed transfers get a different queue, and won't hog the bus.
  674. * Also, some devices enumerate better without FSBR; the easiest way
  675. * to do that is to put URBs on the low-speed queue while the device
  676. * isn't in the CONFIGURED state. */
  677. if (urb->dev->speed == USB_SPEED_LOW ||
  678. urb->dev->state != USB_STATE_CONFIGURED)
  679. qh->skel = uhci->skel_ls_control_qh;
  680. else {
  681. qh->skel = uhci->skel_fs_control_qh;
  682. uhci_add_fsbr(uhci, urb);
  683. }
  684. urb->actual_length = -8; /* Account for the SETUP packet */
  685. return 0;
  686. nomem:
  687. /* Remove the dummy TD from the td_list so it doesn't get freed */
  688. uhci_remove_td_from_urbp(qh->dummy_td);
  689. return -ENOMEM;
  690. }
  691. /*
  692. * Common submit for bulk and interrupt
  693. */
  694. static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb,
  695. struct uhci_qh *qh)
  696. {
  697. struct uhci_td *td;
  698. unsigned long destination, status;
  699. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  700. int len = urb->transfer_buffer_length;
  701. dma_addr_t data = urb->transfer_dma;
  702. __le32 *plink;
  703. struct urb_priv *urbp = urb->hcpriv;
  704. unsigned int toggle;
  705. if (len < 0)
  706. return -EINVAL;
  707. /* The "pipe" thing contains the destination in bits 8--18 */
  708. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  709. toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  710. usb_pipeout(urb->pipe));
  711. /* 3 errors, dummy TD remains inactive */
  712. status = uhci_maxerr(3);
  713. if (urb->dev->speed == USB_SPEED_LOW)
  714. status |= TD_CTRL_LS;
  715. if (usb_pipein(urb->pipe))
  716. status |= TD_CTRL_SPD;
  717. /*
  718. * Build the DATA TDs
  719. */
  720. plink = NULL;
  721. td = qh->dummy_td;
  722. do { /* Allow zero length packets */
  723. int pktsze = maxsze;
  724. if (len <= pktsze) { /* The last packet */
  725. pktsze = len;
  726. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  727. status &= ~TD_CTRL_SPD;
  728. }
  729. if (plink) {
  730. td = uhci_alloc_td(uhci);
  731. if (!td)
  732. goto nomem;
  733. *plink = LINK_TO_TD(td);
  734. }
  735. uhci_add_td_to_urbp(td, urbp);
  736. uhci_fill_td(td, status,
  737. destination | uhci_explen(pktsze) |
  738. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  739. data);
  740. plink = &td->link;
  741. status |= TD_CTRL_ACTIVE;
  742. data += pktsze;
  743. len -= maxsze;
  744. toggle ^= 1;
  745. } while (len > 0);
  746. /*
  747. * URB_ZERO_PACKET means adding a 0-length packet, if direction
  748. * is OUT and the transfer_length was an exact multiple of maxsze,
  749. * hence (len = transfer_length - N * maxsze) == 0
  750. * however, if transfer_length == 0, the zero packet was already
  751. * prepared above.
  752. */
  753. if ((urb->transfer_flags & URB_ZERO_PACKET) &&
  754. usb_pipeout(urb->pipe) && len == 0 &&
  755. urb->transfer_buffer_length > 0) {
  756. td = uhci_alloc_td(uhci);
  757. if (!td)
  758. goto nomem;
  759. *plink = LINK_TO_TD(td);
  760. uhci_add_td_to_urbp(td, urbp);
  761. uhci_fill_td(td, status,
  762. destination | uhci_explen(0) |
  763. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  764. data);
  765. plink = &td->link;
  766. toggle ^= 1;
  767. }
  768. /* Set the interrupt-on-completion flag on the last packet.
  769. * A more-or-less typical 4 KB URB (= size of one memory page)
  770. * will require about 3 ms to transfer; that's a little on the
  771. * fast side but not enough to justify delaying an interrupt
  772. * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
  773. * flag setting. */
  774. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  775. /*
  776. * Build the new dummy TD and activate the old one
  777. */
  778. td = uhci_alloc_td(uhci);
  779. if (!td)
  780. goto nomem;
  781. *plink = LINK_TO_TD(td);
  782. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  783. wmb();
  784. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  785. qh->dummy_td = td;
  786. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  787. usb_pipeout(urb->pipe), toggle);
  788. return 0;
  789. nomem:
  790. /* Remove the dummy TD from the td_list so it doesn't get freed */
  791. uhci_remove_td_from_urbp(qh->dummy_td);
  792. return -ENOMEM;
  793. }
  794. static inline int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb,
  795. struct uhci_qh *qh)
  796. {
  797. int ret;
  798. /* Can't have low-speed bulk transfers */
  799. if (urb->dev->speed == USB_SPEED_LOW)
  800. return -EINVAL;
  801. qh->skel = uhci->skel_bulk_qh;
  802. ret = uhci_submit_common(uhci, urb, qh);
  803. if (ret == 0)
  804. uhci_add_fsbr(uhci, urb);
  805. return ret;
  806. }
  807. static int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb,
  808. struct uhci_qh *qh)
  809. {
  810. int ret;
  811. /* USB 1.1 interrupt transfers only involve one packet per interval.
  812. * Drivers can submit URBs of any length, but longer ones will need
  813. * multiple intervals to complete.
  814. */
  815. if (!qh->bandwidth_reserved) {
  816. int exponent;
  817. /* Figure out which power-of-two queue to use */
  818. for (exponent = 7; exponent >= 0; --exponent) {
  819. if ((1 << exponent) <= urb->interval)
  820. break;
  821. }
  822. if (exponent < 0)
  823. return -EINVAL;
  824. qh->period = 1 << exponent;
  825. qh->skel = uhci->skelqh[UHCI_SKEL_INDEX(exponent)];
  826. /* For now, interrupt phase is fixed by the layout
  827. * of the QH lists. */
  828. qh->phase = (qh->period / 2) & (MAX_PHASE - 1);
  829. ret = uhci_check_bandwidth(uhci, qh);
  830. if (ret)
  831. return ret;
  832. } else if (qh->period > urb->interval)
  833. return -EINVAL; /* Can't decrease the period */
  834. ret = uhci_submit_common(uhci, urb, qh);
  835. if (ret == 0) {
  836. urb->interval = qh->period;
  837. if (!qh->bandwidth_reserved)
  838. uhci_reserve_bandwidth(uhci, qh);
  839. }
  840. return ret;
  841. }
  842. /*
  843. * Fix up the data structures following a short transfer
  844. */
  845. static int uhci_fixup_short_transfer(struct uhci_hcd *uhci,
  846. struct uhci_qh *qh, struct urb_priv *urbp)
  847. {
  848. struct uhci_td *td;
  849. struct list_head *tmp;
  850. int ret;
  851. td = list_entry(urbp->td_list.prev, struct uhci_td, list);
  852. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  853. /* When a control transfer is short, we have to restart
  854. * the queue at the status stage transaction, which is
  855. * the last TD. */
  856. WARN_ON(list_empty(&urbp->td_list));
  857. qh->element = LINK_TO_TD(td);
  858. tmp = td->list.prev;
  859. ret = -EINPROGRESS;
  860. } else {
  861. /* When a bulk/interrupt transfer is short, we have to
  862. * fix up the toggles of the following URBs on the queue
  863. * before restarting the queue at the next URB. */
  864. qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1;
  865. uhci_fixup_toggles(qh, 1);
  866. if (list_empty(&urbp->td_list))
  867. td = qh->post_td;
  868. qh->element = td->link;
  869. tmp = urbp->td_list.prev;
  870. ret = 0;
  871. }
  872. /* Remove all the TDs we skipped over, from tmp back to the start */
  873. while (tmp != &urbp->td_list) {
  874. td = list_entry(tmp, struct uhci_td, list);
  875. tmp = tmp->prev;
  876. uhci_remove_td_from_urbp(td);
  877. uhci_free_td(uhci, td);
  878. }
  879. return ret;
  880. }
  881. /*
  882. * Common result for control, bulk, and interrupt
  883. */
  884. static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
  885. {
  886. struct urb_priv *urbp = urb->hcpriv;
  887. struct uhci_qh *qh = urbp->qh;
  888. struct uhci_td *td, *tmp;
  889. unsigned status;
  890. int ret = 0;
  891. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  892. unsigned int ctrlstat;
  893. int len;
  894. ctrlstat = td_status(td);
  895. status = uhci_status_bits(ctrlstat);
  896. if (status & TD_CTRL_ACTIVE)
  897. return -EINPROGRESS;
  898. len = uhci_actual_length(ctrlstat);
  899. urb->actual_length += len;
  900. if (status) {
  901. ret = uhci_map_status(status,
  902. uhci_packetout(td_token(td)));
  903. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  904. /* Some debugging code */
  905. dev_dbg(&urb->dev->dev,
  906. "%s: failed with status %x\n",
  907. __FUNCTION__, status);
  908. if (debug > 1 && errbuf) {
  909. /* Print the chain for debugging */
  910. uhci_show_qh(urbp->qh, errbuf,
  911. ERRBUF_LEN, 0);
  912. lprintk(errbuf);
  913. }
  914. }
  915. } else if (len < uhci_expected_length(td_token(td))) {
  916. /* We received a short packet */
  917. if (urb->transfer_flags & URB_SHORT_NOT_OK)
  918. ret = -EREMOTEIO;
  919. /* Fixup needed only if this isn't the URB's last TD */
  920. else if (&td->list != urbp->td_list.prev)
  921. ret = 1;
  922. }
  923. uhci_remove_td_from_urbp(td);
  924. if (qh->post_td)
  925. uhci_free_td(uhci, qh->post_td);
  926. qh->post_td = td;
  927. if (ret != 0)
  928. goto err;
  929. }
  930. return ret;
  931. err:
  932. if (ret < 0) {
  933. /* In case a control transfer gets an error
  934. * during the setup stage */
  935. urb->actual_length = max(urb->actual_length, 0);
  936. /* Note that the queue has stopped and save
  937. * the next toggle value */
  938. qh->element = UHCI_PTR_TERM;
  939. qh->is_stopped = 1;
  940. qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL);
  941. qh->initial_toggle = uhci_toggle(td_token(td)) ^
  942. (ret == -EREMOTEIO);
  943. } else /* Short packet received */
  944. ret = uhci_fixup_short_transfer(uhci, qh, urbp);
  945. return ret;
  946. }
  947. /*
  948. * Isochronous transfers
  949. */
  950. static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb,
  951. struct uhci_qh *qh)
  952. {
  953. struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */
  954. int i, frame;
  955. unsigned long destination, status;
  956. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  957. /* Values must not be too big (could overflow below) */
  958. if (urb->interval >= UHCI_NUMFRAMES ||
  959. urb->number_of_packets >= UHCI_NUMFRAMES)
  960. return -EFBIG;
  961. /* Check the period and figure out the starting frame number */
  962. if (!qh->bandwidth_reserved) {
  963. qh->period = urb->interval;
  964. if (urb->transfer_flags & URB_ISO_ASAP) {
  965. qh->phase = -1; /* Find the best phase */
  966. i = uhci_check_bandwidth(uhci, qh);
  967. if (i)
  968. return i;
  969. /* Allow a little time to allocate the TDs */
  970. uhci_get_current_frame_number(uhci);
  971. frame = uhci->frame_number + 10;
  972. /* Move forward to the first frame having the
  973. * correct phase */
  974. urb->start_frame = frame + ((qh->phase - frame) &
  975. (qh->period - 1));
  976. } else {
  977. i = urb->start_frame - uhci->last_iso_frame;
  978. if (i <= 0 || i >= UHCI_NUMFRAMES)
  979. return -EINVAL;
  980. qh->phase = urb->start_frame & (qh->period - 1);
  981. i = uhci_check_bandwidth(uhci, qh);
  982. if (i)
  983. return i;
  984. }
  985. } else if (qh->period != urb->interval) {
  986. return -EINVAL; /* Can't change the period */
  987. } else { /* Pick up where the last URB leaves off */
  988. if (list_empty(&qh->queue)) {
  989. frame = qh->iso_frame;
  990. } else {
  991. struct urb *lurb;
  992. lurb = list_entry(qh->queue.prev,
  993. struct urb_priv, node)->urb;
  994. frame = lurb->start_frame +
  995. lurb->number_of_packets *
  996. lurb->interval;
  997. }
  998. if (urb->transfer_flags & URB_ISO_ASAP)
  999. urb->start_frame = frame;
  1000. else if (urb->start_frame != frame)
  1001. return -EINVAL;
  1002. }
  1003. /* Make sure we won't have to go too far into the future */
  1004. if (uhci_frame_before_eq(uhci->last_iso_frame + UHCI_NUMFRAMES,
  1005. urb->start_frame + urb->number_of_packets *
  1006. urb->interval))
  1007. return -EFBIG;
  1008. status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
  1009. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  1010. for (i = 0; i < urb->number_of_packets; i++) {
  1011. td = uhci_alloc_td(uhci);
  1012. if (!td)
  1013. return -ENOMEM;
  1014. uhci_add_td_to_urbp(td, urbp);
  1015. uhci_fill_td(td, status, destination |
  1016. uhci_explen(urb->iso_frame_desc[i].length),
  1017. urb->transfer_dma +
  1018. urb->iso_frame_desc[i].offset);
  1019. }
  1020. /* Set the interrupt-on-completion flag on the last packet. */
  1021. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  1022. /* Add the TDs to the frame list */
  1023. frame = urb->start_frame;
  1024. list_for_each_entry(td, &urbp->td_list, list) {
  1025. uhci_insert_td_in_frame_list(uhci, td, frame);
  1026. frame += qh->period;
  1027. }
  1028. if (list_empty(&qh->queue)) {
  1029. qh->iso_packet_desc = &urb->iso_frame_desc[0];
  1030. qh->iso_frame = urb->start_frame;
  1031. qh->iso_status = 0;
  1032. }
  1033. qh->skel = uhci->skel_iso_qh;
  1034. if (!qh->bandwidth_reserved)
  1035. uhci_reserve_bandwidth(uhci, qh);
  1036. return 0;
  1037. }
  1038. static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
  1039. {
  1040. struct uhci_td *td, *tmp;
  1041. struct urb_priv *urbp = urb->hcpriv;
  1042. struct uhci_qh *qh = urbp->qh;
  1043. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  1044. unsigned int ctrlstat;
  1045. int status;
  1046. int actlength;
  1047. if (uhci_frame_before_eq(uhci->cur_iso_frame, qh->iso_frame))
  1048. return -EINPROGRESS;
  1049. uhci_remove_tds_from_frame(uhci, qh->iso_frame);
  1050. ctrlstat = td_status(td);
  1051. if (ctrlstat & TD_CTRL_ACTIVE) {
  1052. status = -EXDEV; /* TD was added too late? */
  1053. } else {
  1054. status = uhci_map_status(uhci_status_bits(ctrlstat),
  1055. usb_pipeout(urb->pipe));
  1056. actlength = uhci_actual_length(ctrlstat);
  1057. urb->actual_length += actlength;
  1058. qh->iso_packet_desc->actual_length = actlength;
  1059. qh->iso_packet_desc->status = status;
  1060. }
  1061. if (status) {
  1062. urb->error_count++;
  1063. qh->iso_status = status;
  1064. }
  1065. uhci_remove_td_from_urbp(td);
  1066. uhci_free_td(uhci, td);
  1067. qh->iso_frame += qh->period;
  1068. ++qh->iso_packet_desc;
  1069. }
  1070. return qh->iso_status;
  1071. }
  1072. static int uhci_urb_enqueue(struct usb_hcd *hcd,
  1073. struct usb_host_endpoint *hep,
  1074. struct urb *urb, gfp_t mem_flags)
  1075. {
  1076. int ret;
  1077. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1078. unsigned long flags;
  1079. struct urb_priv *urbp;
  1080. struct uhci_qh *qh;
  1081. spin_lock_irqsave(&uhci->lock, flags);
  1082. ret = urb->status;
  1083. if (ret != -EINPROGRESS) /* URB already unlinked! */
  1084. goto done;
  1085. ret = -ENOMEM;
  1086. urbp = uhci_alloc_urb_priv(uhci, urb);
  1087. if (!urbp)
  1088. goto done;
  1089. if (hep->hcpriv)
  1090. qh = (struct uhci_qh *) hep->hcpriv;
  1091. else {
  1092. qh = uhci_alloc_qh(uhci, urb->dev, hep);
  1093. if (!qh)
  1094. goto err_no_qh;
  1095. }
  1096. urbp->qh = qh;
  1097. switch (qh->type) {
  1098. case USB_ENDPOINT_XFER_CONTROL:
  1099. ret = uhci_submit_control(uhci, urb, qh);
  1100. break;
  1101. case USB_ENDPOINT_XFER_BULK:
  1102. ret = uhci_submit_bulk(uhci, urb, qh);
  1103. break;
  1104. case USB_ENDPOINT_XFER_INT:
  1105. ret = uhci_submit_interrupt(uhci, urb, qh);
  1106. break;
  1107. case USB_ENDPOINT_XFER_ISOC:
  1108. urb->error_count = 0;
  1109. ret = uhci_submit_isochronous(uhci, urb, qh);
  1110. break;
  1111. }
  1112. if (ret != 0)
  1113. goto err_submit_failed;
  1114. /* Add this URB to the QH */
  1115. urbp->qh = qh;
  1116. list_add_tail(&urbp->node, &qh->queue);
  1117. /* If the new URB is the first and only one on this QH then either
  1118. * the QH is new and idle or else it's unlinked and waiting to
  1119. * become idle, so we can activate it right away. But only if the
  1120. * queue isn't stopped. */
  1121. if (qh->queue.next == &urbp->node && !qh->is_stopped) {
  1122. uhci_activate_qh(uhci, qh);
  1123. uhci_urbp_wants_fsbr(uhci, urbp);
  1124. }
  1125. goto done;
  1126. err_submit_failed:
  1127. if (qh->state == QH_STATE_IDLE)
  1128. uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */
  1129. err_no_qh:
  1130. uhci_free_urb_priv(uhci, urbp);
  1131. done:
  1132. spin_unlock_irqrestore(&uhci->lock, flags);
  1133. return ret;
  1134. }
  1135. static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
  1136. {
  1137. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1138. unsigned long flags;
  1139. struct urb_priv *urbp;
  1140. struct uhci_qh *qh;
  1141. spin_lock_irqsave(&uhci->lock, flags);
  1142. urbp = urb->hcpriv;
  1143. if (!urbp) /* URB was never linked! */
  1144. goto done;
  1145. qh = urbp->qh;
  1146. /* Remove Isochronous TDs from the frame list ASAP */
  1147. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  1148. uhci_unlink_isochronous_tds(uhci, urb);
  1149. mb();
  1150. /* If the URB has already started, update the QH unlink time */
  1151. uhci_get_current_frame_number(uhci);
  1152. if (uhci_frame_before_eq(urb->start_frame, uhci->frame_number))
  1153. qh->unlink_frame = uhci->frame_number;
  1154. }
  1155. uhci_unlink_qh(uhci, qh);
  1156. done:
  1157. spin_unlock_irqrestore(&uhci->lock, flags);
  1158. return 0;
  1159. }
  1160. /*
  1161. * Finish unlinking an URB and give it back
  1162. */
  1163. static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh,
  1164. struct urb *urb)
  1165. __releases(uhci->lock)
  1166. __acquires(uhci->lock)
  1167. {
  1168. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  1169. /* When giving back the first URB in an Isochronous queue,
  1170. * reinitialize the QH's iso-related members for the next URB. */
  1171. if (qh->type == USB_ENDPOINT_XFER_ISOC &&
  1172. urbp->node.prev == &qh->queue &&
  1173. urbp->node.next != &qh->queue) {
  1174. struct urb *nurb = list_entry(urbp->node.next,
  1175. struct urb_priv, node)->urb;
  1176. qh->iso_packet_desc = &nurb->iso_frame_desc[0];
  1177. qh->iso_frame = nurb->start_frame;
  1178. qh->iso_status = 0;
  1179. }
  1180. /* Take the URB off the QH's queue. If the queue is now empty,
  1181. * this is a perfect time for a toggle fixup. */
  1182. list_del_init(&urbp->node);
  1183. if (list_empty(&qh->queue) && qh->needs_fixup) {
  1184. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  1185. usb_pipeout(urb->pipe), qh->initial_toggle);
  1186. qh->needs_fixup = 0;
  1187. }
  1188. uhci_free_urb_priv(uhci, urbp);
  1189. spin_unlock(&uhci->lock);
  1190. usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb);
  1191. spin_lock(&uhci->lock);
  1192. /* If the queue is now empty, we can unlink the QH and give up its
  1193. * reserved bandwidth. */
  1194. if (list_empty(&qh->queue)) {
  1195. uhci_unlink_qh(uhci, qh);
  1196. if (qh->bandwidth_reserved)
  1197. uhci_release_bandwidth(uhci, qh);
  1198. }
  1199. }
  1200. /*
  1201. * Scan the URBs in a QH's queue
  1202. */
  1203. #define QH_FINISHED_UNLINKING(qh) \
  1204. (qh->state == QH_STATE_UNLINKING && \
  1205. uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
  1206. static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1207. {
  1208. struct urb_priv *urbp;
  1209. struct urb *urb;
  1210. int status;
  1211. while (!list_empty(&qh->queue)) {
  1212. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1213. urb = urbp->urb;
  1214. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1215. status = uhci_result_isochronous(uhci, urb);
  1216. else
  1217. status = uhci_result_common(uhci, urb);
  1218. if (status == -EINPROGRESS)
  1219. break;
  1220. spin_lock(&urb->lock);
  1221. if (urb->status == -EINPROGRESS) /* Not dequeued */
  1222. urb->status = status;
  1223. else
  1224. status = ECONNRESET; /* Not -ECONNRESET */
  1225. spin_unlock(&urb->lock);
  1226. /* Dequeued but completed URBs can't be given back unless
  1227. * the QH is stopped or has finished unlinking. */
  1228. if (status == ECONNRESET) {
  1229. if (QH_FINISHED_UNLINKING(qh))
  1230. qh->is_stopped = 1;
  1231. else if (!qh->is_stopped)
  1232. return;
  1233. }
  1234. uhci_giveback_urb(uhci, qh, urb);
  1235. if (status < 0 && qh->type != USB_ENDPOINT_XFER_ISOC)
  1236. break;
  1237. }
  1238. /* If the QH is neither stopped nor finished unlinking (normal case),
  1239. * our work here is done. */
  1240. if (QH_FINISHED_UNLINKING(qh))
  1241. qh->is_stopped = 1;
  1242. else if (!qh->is_stopped)
  1243. return;
  1244. /* Otherwise give back each of the dequeued URBs */
  1245. restart:
  1246. list_for_each_entry(urbp, &qh->queue, node) {
  1247. urb = urbp->urb;
  1248. if (urb->status != -EINPROGRESS) {
  1249. /* Fix up the TD links and save the toggles for
  1250. * non-Isochronous queues. For Isochronous queues,
  1251. * test for too-recent dequeues. */
  1252. if (!uhci_cleanup_queue(uhci, qh, urb)) {
  1253. qh->is_stopped = 0;
  1254. return;
  1255. }
  1256. uhci_giveback_urb(uhci, qh, urb);
  1257. goto restart;
  1258. }
  1259. }
  1260. qh->is_stopped = 0;
  1261. /* There are no more dequeued URBs. If there are still URBs on the
  1262. * queue, the QH can now be re-activated. */
  1263. if (!list_empty(&qh->queue)) {
  1264. if (qh->needs_fixup)
  1265. uhci_fixup_toggles(qh, 0);
  1266. /* If the first URB on the queue wants FSBR but its time
  1267. * limit has expired, set the next TD to interrupt on
  1268. * completion before reactivating the QH. */
  1269. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1270. if (urbp->fsbr && qh->wait_expired) {
  1271. struct uhci_td *td = list_entry(urbp->td_list.next,
  1272. struct uhci_td, list);
  1273. td->status |= __cpu_to_le32(TD_CTRL_IOC);
  1274. }
  1275. uhci_activate_qh(uhci, qh);
  1276. }
  1277. /* The queue is empty. The QH can become idle if it is fully
  1278. * unlinked. */
  1279. else if (QH_FINISHED_UNLINKING(qh))
  1280. uhci_make_qh_idle(uhci, qh);
  1281. }
  1282. /*
  1283. * Check for queues that have made some forward progress.
  1284. * Returns 0 if the queue is not Isochronous, is ACTIVE, and
  1285. * has not advanced since last examined; 1 otherwise.
  1286. *
  1287. * Early Intel controllers have a bug which causes qh->element sometimes
  1288. * not to advance when a TD completes successfully. The queue remains
  1289. * stuck on the inactive completed TD. We detect such cases and advance
  1290. * the element pointer by hand.
  1291. */
  1292. static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1293. {
  1294. struct urb_priv *urbp = NULL;
  1295. struct uhci_td *td;
  1296. int ret = 1;
  1297. unsigned status;
  1298. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1299. goto done;
  1300. /* Treat an UNLINKING queue as though it hasn't advanced.
  1301. * This is okay because reactivation will treat it as though
  1302. * it has advanced, and if it is going to become IDLE then
  1303. * this doesn't matter anyway. Furthermore it's possible
  1304. * for an UNLINKING queue not to have any URBs at all, or
  1305. * for its first URB not to have any TDs (if it was dequeued
  1306. * just as it completed). So it's not easy in any case to
  1307. * test whether such queues have advanced. */
  1308. if (qh->state != QH_STATE_ACTIVE) {
  1309. urbp = NULL;
  1310. status = 0;
  1311. } else {
  1312. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1313. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  1314. status = td_status(td);
  1315. if (!(status & TD_CTRL_ACTIVE)) {
  1316. /* We're okay, the queue has advanced */
  1317. qh->wait_expired = 0;
  1318. qh->advance_jiffies = jiffies;
  1319. goto done;
  1320. }
  1321. ret = 0;
  1322. }
  1323. /* The queue hasn't advanced; check for timeout */
  1324. if (qh->wait_expired)
  1325. goto done;
  1326. if (time_after(jiffies, qh->advance_jiffies + QH_WAIT_TIMEOUT)) {
  1327. /* Detect the Intel bug and work around it */
  1328. if (qh->post_td && qh_element(qh) == LINK_TO_TD(qh->post_td)) {
  1329. qh->element = qh->post_td->link;
  1330. qh->advance_jiffies = jiffies;
  1331. ret = 1;
  1332. goto done;
  1333. }
  1334. qh->wait_expired = 1;
  1335. /* If the current URB wants FSBR, unlink it temporarily
  1336. * so that we can safely set the next TD to interrupt on
  1337. * completion. That way we'll know as soon as the queue
  1338. * starts moving again. */
  1339. if (urbp && urbp->fsbr && !(status & TD_CTRL_IOC))
  1340. uhci_unlink_qh(uhci, qh);
  1341. } else {
  1342. /* Unmoving but not-yet-expired queues keep FSBR alive */
  1343. if (urbp)
  1344. uhci_urbp_wants_fsbr(uhci, urbp);
  1345. }
  1346. done:
  1347. return ret;
  1348. }
  1349. /*
  1350. * Process events in the schedule, but only in one thread at a time
  1351. */
  1352. static void uhci_scan_schedule(struct uhci_hcd *uhci)
  1353. {
  1354. int i;
  1355. struct uhci_qh *qh;
  1356. /* Don't allow re-entrant calls */
  1357. if (uhci->scan_in_progress) {
  1358. uhci->need_rescan = 1;
  1359. return;
  1360. }
  1361. uhci->scan_in_progress = 1;
  1362. rescan:
  1363. uhci->need_rescan = 0;
  1364. uhci->fsbr_is_wanted = 0;
  1365. uhci_clear_next_interrupt(uhci);
  1366. uhci_get_current_frame_number(uhci);
  1367. uhci->cur_iso_frame = uhci->frame_number;
  1368. /* Go through all the QH queues and process the URBs in each one */
  1369. for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) {
  1370. uhci->next_qh = list_entry(uhci->skelqh[i]->node.next,
  1371. struct uhci_qh, node);
  1372. while ((qh = uhci->next_qh) != uhci->skelqh[i]) {
  1373. uhci->next_qh = list_entry(qh->node.next,
  1374. struct uhci_qh, node);
  1375. if (uhci_advance_check(uhci, qh)) {
  1376. uhci_scan_qh(uhci, qh);
  1377. if (qh->state == QH_STATE_ACTIVE) {
  1378. uhci_urbp_wants_fsbr(uhci,
  1379. list_entry(qh->queue.next, struct urb_priv, node));
  1380. }
  1381. }
  1382. }
  1383. }
  1384. uhci->last_iso_frame = uhci->cur_iso_frame;
  1385. if (uhci->need_rescan)
  1386. goto rescan;
  1387. uhci->scan_in_progress = 0;
  1388. if (uhci->fsbr_is_on && !uhci->fsbr_is_wanted &&
  1389. !uhci->fsbr_expiring) {
  1390. uhci->fsbr_expiring = 1;
  1391. mod_timer(&uhci->fsbr_timer, jiffies + FSBR_OFF_DELAY);
  1392. }
  1393. if (list_empty(&uhci->skel_unlink_qh->node))
  1394. uhci_clear_next_interrupt(uhci);
  1395. else
  1396. uhci_set_next_interrupt(uhci);
  1397. }