omap3-igep0020.dts 5.1 KB

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  1. /*
  2. * Device Tree Source for IGEPv2 board
  3. *
  4. * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
  5. * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include "omap3-igep.dtsi"
  12. / {
  13. model = "IGEPv2";
  14. compatible = "isee,omap3-igep0020", "ti,omap3";
  15. leds {
  16. pinctrl-names = "default";
  17. pinctrl-0 = <&leds_pins>;
  18. compatible = "gpio-leds";
  19. boot {
  20. label = "omap3:green:boot";
  21. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  22. default-state = "on";
  23. };
  24. user0 {
  25. label = "omap3:red:user0";
  26. gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
  27. default-state = "off";
  28. };
  29. user1 {
  30. label = "omap3:red:user1";
  31. gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  32. default-state = "off";
  33. };
  34. user2 {
  35. label = "omap3:green:user1";
  36. gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
  37. };
  38. };
  39. vddvario: regulator-vddvario {
  40. compatible = "regulator-fixed";
  41. regulator-name = "vddvario";
  42. regulator-always-on;
  43. };
  44. vdd33a: regulator-vdd33a {
  45. compatible = "regulator-fixed";
  46. regulator-name = "vdd33a";
  47. regulator-always-on;
  48. };
  49. /* HS USB Port 1 Power */
  50. hsusb1_power: hsusb1_power_reg {
  51. compatible = "regulator-fixed";
  52. regulator-name = "hsusb1_vbus";
  53. regulator-min-microvolt = <3300000>;
  54. regulator-max-microvolt = <3300000>;
  55. gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
  56. startup-delay-us = <70000>;
  57. };
  58. /* HS USB Host PHY on PORT 1 */
  59. hsusb1_phy: hsusb1_phy {
  60. compatible = "usb-nop-xceiv";
  61. reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
  62. vcc-supply = <&hsusb1_power>;
  63. };
  64. };
  65. &omap3_pmx_core {
  66. pinctrl-names = "default";
  67. pinctrl-0 = <
  68. &hsusbb1_pins
  69. >;
  70. hsusbb1_pins: pinmux_hsusbb1_pins {
  71. pinctrl-single,pins = <
  72. 0x5aa (PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
  73. 0x5a8 (PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
  74. 0x5bc (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
  75. 0x5be (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
  76. 0x5ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
  77. 0x5ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
  78. 0x5b0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
  79. 0x5b2 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
  80. 0x5b4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
  81. 0x5b6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
  82. 0x5b8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
  83. 0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
  84. >;
  85. };
  86. };
  87. &leds_pins {
  88. pinctrl-single,pins = <
  89. 0x5c4 (PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
  90. 0x5c6 (PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
  91. 0x5c8 (PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
  92. >;
  93. };
  94. &i2c3 {
  95. clock-frequency = <100000>;
  96. /*
  97. * Display monitor features are burnt in the EEPROM
  98. * as EDID data.
  99. */
  100. eeprom@50 {
  101. compatible = "ti,eeprom";
  102. reg = <0x50>;
  103. };
  104. };
  105. &gpmc {
  106. ranges = <0 0 0x00000000 0x20000000>,
  107. <5 0 0x2c000000 0x01000000>;
  108. nand@0,0 {
  109. linux,mtd-name= "micron,mt29c4g96maz";
  110. reg = <0 0 0>;
  111. nand-bus-width = <16>;
  112. ti,nand-ecc-opt = "bch8";
  113. gpmc,sync-clk-ps = <0>;
  114. gpmc,cs-on-ns = <0>;
  115. gpmc,cs-rd-off-ns = <44>;
  116. gpmc,cs-wr-off-ns = <44>;
  117. gpmc,adv-on-ns = <6>;
  118. gpmc,adv-rd-off-ns = <34>;
  119. gpmc,adv-wr-off-ns = <44>;
  120. gpmc,we-off-ns = <40>;
  121. gpmc,oe-off-ns = <54>;
  122. gpmc,access-ns = <64>;
  123. gpmc,rd-cycle-ns = <82>;
  124. gpmc,wr-cycle-ns = <82>;
  125. gpmc,wr-access-ns = <40>;
  126. gpmc,wr-data-mux-bus-ns = <0>;
  127. #address-cells = <1>;
  128. #size-cells = <1>;
  129. partition@0 {
  130. label = "SPL";
  131. reg = <0 0x100000>;
  132. };
  133. partition@80000 {
  134. label = "U-Boot";
  135. reg = <0x100000 0x180000>;
  136. };
  137. partition@1c0000 {
  138. label = "Environment";
  139. reg = <0x280000 0x100000>;
  140. };
  141. partition@280000 {
  142. label = "Kernel";
  143. reg = <0x380000 0x300000>;
  144. };
  145. partition@780000 {
  146. label = "Filesystem";
  147. reg = <0x680000 0x1f980000>;
  148. };
  149. };
  150. ethernet@5,0 {
  151. pinctrl-names = "default";
  152. pinctrl-0 = <&smsc911x_pins>;
  153. compatible = "smsc,lan9221", "smsc,lan9115";
  154. reg = <5 0 0xff>;
  155. bank-width = <2>;
  156. gpmc,mux-add-data;
  157. gpmc,cs-on-ns = <0>;
  158. gpmc,cs-rd-off-ns = <186>;
  159. gpmc,cs-wr-off-ns = <186>;
  160. gpmc,adv-on-ns = <12>;
  161. gpmc,adv-rd-off-ns = <48>;
  162. gpmc,adv-wr-off-ns = <48>;
  163. gpmc,oe-on-ns = <54>;
  164. gpmc,oe-off-ns = <168>;
  165. gpmc,we-on-ns = <54>;
  166. gpmc,we-off-ns = <168>;
  167. gpmc,rd-cycle-ns = <186>;
  168. gpmc,wr-cycle-ns = <186>;
  169. gpmc,access-ns = <114>;
  170. gpmc,page-burst-access-ns = <6>;
  171. gpmc,bus-turnaround-ns = <12>;
  172. gpmc,cycle2cycle-delay-ns = <18>;
  173. gpmc,wr-data-mux-bus-ns = <90>;
  174. gpmc,wr-access-ns = <186>;
  175. gpmc,cycle2cycle-samecsen;
  176. gpmc,cycle2cycle-diffcsen;
  177. interrupt-parent = <&gpio6>;
  178. interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
  179. vmmc-supply = <&vddvario>;
  180. vmmc_aux-supply = <&vdd33a>;
  181. reg-io-width = <4>;
  182. smsc,save-mac-address;
  183. };
  184. };
  185. &usbhshost {
  186. port1-mode = "ehci-phy";
  187. };
  188. &usbhsehci {
  189. phys = <&hsusb1_phy>;
  190. };